JPH0531333B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field This invention relates to a digital signal transmission system, particularly
The present invention relates to a digital signal transmission system suitable for use when transmitting digital audio signals using a CATV (cable television) line.

Background technology and its problems A four-level VSB (residual sideband) digital signal that transmits digital audio signals using a CATV line and can also use parts of television receivers currently in use as its hardware. A transmission method was previously proposed by the present inventors.

FIGS. 1 to 3 show the signal formats used in this case, and FIGS. 4 and 5 show the specific circuit configuration thereof.

First, to explain the signal format, Fig. 1A shows, for example, L channel (16 bits), R channel (16 bits), and here 34 service bits (2 bits) used as address signals.
One stereo channel consisting of bits, Figure 1B
For example, channels A, B, C and D (all
One word consists of 162 bits (34 bits), BCH code (16 bits), and synchronization (SYNC) code (10 bits); Figure 1C is 32 words (5184 bits)
The signal format of each frame is shown. The transmission capacity (transmission speed) using two signal formats (i.e., four levels) is 44.1×10 ³ × {(16×2+2)×
4+16+10}×2=14.2884MBPS. This is approximately 3dB at the 3.58MHz color subcarrier level.
Transmission speed at 4 values of a filter with attenuation of 3.58
×10 ⁶ ×2 × 2 = 14.32MBPS, which is within the allowable range of 1 channel of television, i.e.
It can be seen that sufficient transmission is possible with a 6MHz transmission line.

Also, most of the errors in CATV lines are due to intersymbol interference. Therefore, an error correction code is added to each word. For example, as shown in Fig. 6, the (225, 239) BCH code has a 2-bit correction capability, and the (152, 136) BCH code is shortened. A BCH code is used, in which 136 bits are information bits,
16 bits are check bits.

As for the signal distribution, for example, as shown in Figure 2A, among the channels A to D that make up one series, channel A has digital audio program (stereo) P1 (44.1KHz, 16 bits for one channel), Channel B has digital audio program (stereo) P2 (44.1KHz, 16 bits per channel), and channel C has announcement information (monaural) (22.1KHz 8 bits) P3 and guidance information (monaural) (22.1KHz 8 bits) P4. Facsimile P5 and facsimile P6 are inserted into channel D in a time-division manner. Furthermore, when two programs P3 and P4 are selected at the same time, one of them is prioritized depending on the importance and urgency of the content. For example, here, P3 is prioritized over P4. It is made to be done. or,
Regarding P5 and P6, one can be given priority over the other. The transmitting side is also determined by the service bits (SB) of channels C and D.

and the four stereo channels A to D mentioned above.
When transmitting four other stereo channels in addition to the one series, they are inserted on the side B of FIG. 2, which represents the other one series.

FIG. 3 exemplarily shows the case of obtaining a signal format for transmission at four-level levels. In other words, Fig. 3A shows the signal configuration from channel A to channel D forming one series (corresponding to Fig. 2A).
In FIG. 3B, signal configurations from channel E to channel H forming another series (corresponding to FIG. 2B) are arranged. and these third
The binary levels in Figures A and B are converted to a four-level level, and channels A and E, channels B and F, channels C and G, and channels D and H are mixed together as shown in Figure 3C. It is designed to configure two signal formats. Furthermore, in this case, the error correction codes of both series also have a four-value level. In this case, the synchronization signal SYNC is set to a binary level for reasons to be described later, and is not converted to a four-level level.

Next, a specific circuit configuration will be explained with reference to FIGS. 4 and 5. FIG. 4 shows the configuration of the transmitting side, and FIG. 5 shows the configuration of the receiving side.

First, to explain Fig. 4, input terminals 1 to 1
Information on the programs P1 to P6 as described above is supplied to 6, respectively, and audio analog signals from input terminals 1 to 4 are input to analog-to-digital converters (hereinafter referred to as A/D converters) 7 to 10. The analog signal is converted into a digital signal and supplied to the multiplexer 13 via the interface circuit 11. On the other hand, input terminals 5 and 6
For example, a facsimile signal, which is a digital signal, is supplied to a multiplexer 13 via an interface circuit 11. Further, an address signal from the address switch circuit 12 is supplied to the multiplexer 13 via the interface circuit 11. This address signal specifies the address of at least one receiver. Here, these signals are distributed to each corresponding channel as described above, and an error correction code, a synchronization signal, etc. are added and output. The output signal from the multiplexer 13 is converted to a four-level level by a digital-to-analog converter (hereinafter referred to as a D/A converter) through the BTF 14 in order to match the frequency characteristics of the entire transmitting and receiving system so that intersymbol interference is eliminated. is supplied to circuit 15, where
The 7.15MBPS x 2 data series is converted to a four-level baseband signal. Note that when the data series to be transmitted is only one series (equivalent to 7.15 MBPS), it is sufficient to fix the level of the other one series to "1" or "0". The output signal of the conversion circuit 15 is supplied to the AM modulator 16, where the oscillator 1
For example, the 38.9MHz carrier wave from 7 is transmitted to conversion circuit 1.
It is modulated by the output signal of 5. Therefore modulator 1
A signal with an intermediate frequency f _if =38.9MHz is obtained on the output side of 6, and this signal is supplied to a mixing circuit 19 through a vestigial sideband filter (VSBF) 18.
Here, it is mixed with a signal of a local oscillation frequency, for example, f ₁ from the local oscillation circuit 20, frequency-converted, and outputted as a signal of a frequency f ₁ -f _if . Note that the local oscillation frequency of the oscillation circuit 20 is set to a frequency higher than the transmission frequency of the arbitrary channel by f _if . Therefore, it is determined by selecting the local oscillator frequency of the transmission channel.

The output signal from the mixing circuit 19 is taken out to an output terminal 22 through a bandpass filter 21.
The signal from this output terminal 22 is supplied to a so-called head end (not shown) of the CATV system.
And the signal from the head end is
It is supplied to the receiving side via the CATV line. Note that 23 is an input device for other series data CH.E to CH.H.

The signal thus transmitted via the CATV line is supplied to the front end 32 from the receiving side input terminal 31 shown in FIG. 5, where it is amplified and then converted into an intermediate frequency signal such as 58.75 MHz. is converted to This intermediate frequency signal is
The signal is supplied to a detector, for example, a PLL detector 33, where a four-level baseband signal is demodulated.
Although the AM detector used in conventional television systems may be used, in order to avoid waveform distortion, it is necessary to use a PLL like the one described above.
It is preferable to use a detector.

The output signal from the PLL detector 33 is supplied to a level comparator 34, which identifies the level at an open eye pattern, extracts digital data, and supplies it to a demultiplexer 35 at the next stage. Then, signal processing such as data rearrangement, error correction, and synchronization signal (SYNC) extraction is performed here. When the address decoder 38 detects that the address value specified on the transmitting side matches the setting address value individually set in advance on the receiving side (receiver), the demultiplexer 3
The digital signal from 5 is sent to address decoder 38
switch circuit 36 under the control of the output signal from
D/A converter 3 via switches 36 ₁ and 36 ₂
9 and 40, where the digital signal is converted into an analog signal and then output to output terminals 42 and 43, respectively. When the switch 36 ₁ is on the contact a side, the program P1 is on, and when the switch 36 1 is on the contact b side, the program is _P2 .
When is on the contact a side, program P3, contact b
When the program P4 is on the side, the program P4 is switched and taken out by the output signal from the address decoder 38, respectively. On the other hand, the facsimile signal is taken out to the output terminal 44 via the switch circuit 37 and the facsimile interface circuit 41. In this case as well, when the switch contact a side of the switch circuit 37 is on, program P5 is taken out.
When it is on the contact b side, program P6 is switched and taken out. When this receiving side (receiver) is not addressed by the transmitting side, that is, when the address value of the transmitting side and the set address value of the receiving side do not match, a mutating signal is sent from the address decoder 38. As a result, each switch in the switch circuits 36 and 37 is switched to the contact c side, and the receiving side can no longer receive information from the transmitting side.

Further, the bit clock used in these signal processing is performed by referring only to the period of the synchronizing signal in order to reproduce the bit clock without being affected by jitter. That is, since the output side of the PLL detector 33 receives an output signal which is a binary level signal only during the synchronizing signal SYNC period and a four-level signal at other times, the synchronizing signal SYNC from the demultiplexer 35 and level comparator 34
The data from the bit clock is supplied to the clock regenerator 45, and the data, which is at a binary level only during the period of the synchronization signal SYNC, is extracted as a bit clock and supplied to the demultiplexer 35. In other words, by referring to the binary level signal during the synchronization signal period, a bit clock with less jitter can be reproduced. Also, since the pattern is always constant during this synchronizing signal period, the AGC circuit 46 generates an AGC voltage by referring to the signal voltage during this synchronizing signal period, and supplies this to the front end 32. This makes it possible to always obtain stable AGC operation.

By the way, in the case of the circuits shown in Figures 4 and 5, the receivers can be individually enabled via broadcast radio waves.
In order to provide the so-called ADDRESSABLE function, which allows the user to display images or make sounds, or DISABLE (disable images or make sounds), the sending side must use the above-mentioned In this case, it is necessary to provide a bit dedicated to address designation, as in the case where the service bit is used as an address signal, which results in an inconvenience that the number of bits per block increases and the bit rate of data transmission becomes high.

Furthermore, on the receiving side, it is necessary to provide an address decoder for decoding bits dedicated to address designation, which has disadvantages such as a complicated configuration.

OBJECTS OF THE INVENTION In view of the above, the present invention provides a digital signal transmission system that can achieve a desired addressable function without transmitting bits dedicated to address designation.

SUMMARY OF THE INVENTION In this invention, unnecessary information bits are used when the error correction code is shortened, and the error is zero for the receiver to which the address is desired, and a predetermined error, for example, for the receiver to which the address is not desired, is generated. By providing an error that exceeds the input threshold level, the addressable function can be easily achieved with a simple configuration without increasing the bit rail of data transmission. To explain more specifically, for example, as shown in FIGS. 6 and 9, on the transmitter T side, unnecessary information bits are added to the information bits and error correction coding is performed, and the information bits and error correction are In a digital transmission system for transmitting codes, the unnecessary information bits are used as address values for specifying the receiver R side.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail based on FIGS. 7 to 9.

7 and 8 show the configuration of this embodiment, with FIG. 7 showing the transmitting side and FIG. 8 showing the receiving side, respectively. In addition, in each figure, Figures 4 and 5
Portions corresponding to those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted.

In the present invention, the unnecessary information bits when shortening the error correction code, that is, the left side part in FIG.
103 unnecessary information bits that are used only when creating the BCH code, are not used as actual information bits, and are never transmitted are used for addressing. In addition, unnecessary information bits [00...
01], the reason why the LSB is set to 1 is because if all of these unnecessary information bits are 0, when all 136 bits of information are 0, the BCH code will also be all 0, and no information will be transmitted or the line will be interrupted. Since it is no longer possible to distinguish that the wire is disconnected, we consciously make it possible to distinguish it as 1. By the way, for unnecessary information bits [00...01]
When all 136 bits of information are 0, the BCH code is [0111111010110110]. Then, the error is set to 0 for the receiver to be addressed, and the error for the receiver not to be addressed is set to exceed, for example, a muting threshold level. For example, in Fig. 6, unnecessary information bits [00...01] are set as the setting address value of the receiver to be addressed, while unnecessary information bits [00...01] are set as the setting address value of the receiver to be addressed.
...01], invert any number of bits in the 0 part to 1, and set a value that has an error exceeding at least the mutating threshold level for the unnecessary information bits [00...01]. If the address value is set for a receiver that does not want to be addressed, by transmitting the BCH code generated on the transmitting side with unnecessary information bits [00...01] as the address value,
On the receiving side, if a receiver does not want to be addressed, a signal with an error exceeding the mutating threshold level is given to the receiver.
On the other hand, the same signal appears as zero error to the receiver that wants to specify the address, so the receiver enters the ENABLE state. Therefore, it is possible to have an addressable function without sending any bits dedicated to address specification. That's why.

Note that if the receiving side's muting threshold level is set to 2 or more bit errors that occur many times in a row, then the number of addresses that can be specified (2
The number that causes a bit error is ₁₀₃ C ₂ = 5253.

Therefore, in FIG. 7, an address switch circuit 24 is provided for the multiplexer 13, and the above-mentioned
Set the address value using 103 unnecessary information bits. This address value can be arbitrarily set by the address switch circuit 24 using unnecessary information bits.

On the other hand, on the receiving side, the demultiplexer 35 of the receiver as shown in FIG. If the same address value is set and the receiver does not want to be addressed, a predetermined error, such as an error exceeding the mutating threshold level, will occur.
In other words, an address value different from the address value on the sending side is set.

On the transmitting side, the setting address value of each receiver on the receiving side is known in advance, so by setting the address value on the transmitting side arbitrarily, it is possible to freely set any receiver to the ENABLE state. This provides addressable functions such as , or setting it to DISABLE state.

If the receiving side (receiver) is currently addressed by the transmitting side, the control signal from the demultiplexer 35 causes the switch circuits 36 and 37 to be addressed.
Each switch has contact a depending on the program information.
Or connected to the b side, the digital output signal from the demultiplexer 35 is converted into an analog signal by the D/A converters 39 and 40 in the case of a digital audio signal, and then outputted to the output terminals 42 and 43 to generate a facsimile signal. In this case, the signal is output to the output terminal 44 through the interface circuit 41. In other words, the receiver is placed in the BNABLE state.

If this receiving side is not addressed, a control signal (muting signal) from the demultiplexer 35 causes the switch circuit 3 to
The switches 6 and 37 are all switched to the contact c side to cut off the digital output signal from the demultiplexer 35. In other words, the receiving side
It is set to DISABLE state.

For example, in FIG. 9, consider a single transmitter T that can set an address value corresponding to the address value of the address switch circuit 24 described above, and a plurality of receivers R each having a predetermined set address value. In this case, if the set address value of the transmitter T is "B", only the receiver R set to this address value "B" will be in the ENABLE state, and the address value "B" will be set.
Receivers R set to address values other than "A" and "C" are in the DISABLE state. Also, if the set address value of the transmitter T is "A", only the receiver R set to this address value "A" will be in the ENABLE state, and the receivers set to the address values "B" and "C" will be in the ENABLE state. It becomes DISABLE state. Address value “C”
The same applies to .

Application Example In the above embodiment, an example was explained in which address signals are added to digital audio signals and facsimile signals and multiplexed transmission is performed using a CATV line, but the present invention is not limited to this.
The present invention is similarly applicable to the transmission of other digital signals including at least address signals.

Effects of the Invention As described above, according to the present invention, the unnecessary information bits when shortening the error correction code are provided with an addressable function, so there is no need to provide bits dedicated to address designation as in the past, and data transmission is improved. The bit rate can be lowered. Furthermore, since there is no need to provide an address decoder for decoding bits dedicated to address designation on the receiving side, the configuration becomes simpler.

[Brief explanation of drawings]

1 to 3 are diagrams showing the signal format according to the prior art of the present invention, FIGS. 4 and 5 are block diagrams showing the specific circuit configuration thereof, and FIG. 6 is provided for explanation of the present invention. 7 and 8 are block diagrams showing an embodiment of the present invention,
FIG. 9 is a block diagram for explaining the present invention. 7 to 10 are analog-to-digital converters, 11
1 is an interface circuit, 12 and 24 are address switch circuits, 13 is a multiplexer, 14 is a binary transversal filter (BTF), 1
5 is a four-level level conversion circuit, 16 is an AM modulator, 1
7 is an oscillator, 18 is a vestigial sideband filter (VSBF), 19 is a mixing circuit, 20 is a local oscillation circuit, 21 is a band pass filter, 23 is an input device for other series data, 32 is a front end, 33 is a
PLL detector, 34 is a level comparator, 35 is a demultiplexer, 36 and 37 are switch circuits, 38
is an address decoder, 39 and 40 are digital-to-analog converters, 41 is a facsimile interface circuit, 45 is a clock regeneration circuit, and 46 is a clock regeneration circuit.
It is an AGC circuit.

Claims (1)

[Claims] 1 The transmitter adds unnecessary information bits to the information bits and performs error correction encoding, transmits the information bits and error correction code, and the receiver converts the data with the same pattern as the unnecessary information bits and the transmitted error. A digital signal transmission system for correcting errors in the transmitted information bits using a correction code, characterized in that patterns of the unnecessary information bits are set differently for each receiver in advance.