JPH0531775B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for counting a predetermined count clock,
The present invention also relates to a counting device including a hardware counter that generates a processing request, a memory unit that stores programs and various data, and a central processing unit that selectively executes processing based on the processing request and processing according to the program.

[Conventional technology]

FIG. 3 is a block diagram of a conventional counting device of this type, and FIG. 4 is a time chart thereof.

The microcomputer 100 includes an execution unit 10
1. Program memory 102, data memory 10
3. Upper m bits and lower n bits for counting interrupt control unit 104 and count clock 105-1
Hardware counter 10 with period T ₀ in bits
5, which are interconnected via an internal bus 106. A program counter (hereinafter referred to as PC) 101-1 that stores the address where the currently executed instruction is stored, a program status word (hereinafter referred to as PSW) 101-2 that indicates the operating state of the execution unit 101, and An execution unit 101 having a general-purpose register set 101-3 sequentially reads instruction codes from a program memory 102 and executes them, and processing data is stored on a data memory 103.

Next, the operation of the hardware counter 105 will be described below. The hardware counter 105 performs a count-up operation every time the count clock 105-1 is input. The time T ₁ from the start of the counting operation to the generation of curies from the lower n bits is T ₁ =T ₀ ×2 ⁿ , and this time T ₁ becomes the increment period of the upper m bits. That is, the cycle in which the upper m bits are incremented is once every T ₀ ×2 ⁿ when a carry occurs from the lower n bits.
When the time T ₀ ×2 ^(m+n) has elapsed since the hardware counter 105 started its counter operation, the hardware counter 105 generates an overflow.
Activate the interrupt request signal line 105-2. Upon detecting that the interrupt request signal line 105-2 has become active, the interrupt control unit 104 activates the interrupt processing execution request line 104-1 to the execution unit 101. The execution unit 101 interrupts the currently running program, and
01-2 and the general-purpose register set 101-3, the processing stored in the program memory 102 is executed.

[Problem that the invention seeks to solve]

In the conventional counting processing device described above, the number of bits in the counter is determined by the cycle to be measured, that is, the time until the counter overflows, and the count lock frequency. The number of counts increases because it is necessary to increase the frequency of the clock used to perform the measurement, and if you try to measure a long period, the number of counts also increases and the number of bits in the counter must be increased. As a result, the circuit scale increases, which is undesirable from a cost standpoint. However, as mentioned earlier, the cycle in which the upper bits of the counter are incremented is much longer than that of the lower bits, and it is difficult to say that the increments are being used effectively. It is not being used effectively given the heavy burden it places on people.

[Means for solving problems]

The counting device of the present invention includes a hardware counter that counts clocks and outputs an overflow signal, a memory section that has a count storage area that stores a predetermined count, and a central processing unit that executes a program in a program memory. and a counter processing control unit that controls processing for a special interrupt request issued to the central processing unit or processing for a normal interrupt request from a peripheral device, and the counter processing control unit controls processing for a special interrupt request issued to the central processing unit, and the counter processing control unit When the overflow signal is received, the states of the program counter, program status word, and general-purpose registers constituting the central processing unit are maintained as they are, and the processing of the central processing unit by the program is interrupted, and the count number storage area is After reading out the contents of and incrementing them in the central processing unit and writing them again to the count storage area, the program restarts the processing of the central processing unit, and when receiving an interrupt request from the peripheral device, It is characterized by performing interrupt processing.

When an I/O request from a hardware counter occurs, the macro service interrupts the processing up to that point, performs increment and transfer processing while retaining the program counter, PSW, general-purpose register set, etc. in the execution section, and then resumes the macro service. Since the macro service resumes execution of the interrupted program when the program is finished, there is no need to add any special hardware, and the series of processes are all automatically performed by the execution control unit, so the processing for the macro service is There is no need to create any software.

If you try to reduce the number of bits in the hardware counter using only the conventional interrupt function, the PC,
PSW, general-purpose register set save/restore processing,
It is necessary to perform branch processing to the interrupt program and read instructions (hereinafter, the above processing will be referred to as overhead). As a result, the CPU spends more time due to overhead than the original processing of incrementing and transferring the count data value, and the more the number of bits is reduced, the less I/O requests occur. become more
CPU efficiency decreases. However, in the present invention, even if the number of bits of the hardware counter is reduced, the area in the data memory is used as the count value storage area of the upper side counter, and by having a macro service function, no overhead is required. It is possible to increment and transfer the value of count data, minimizing the decrease in CPU processing performance. Furthermore, if the macro service described in this embodiment is applied to an information processing device equipped with multiple counters, the amount of hardware that can be reduced will decrease as the number of counters increases. As the number increases, the burden on the hardware can be significantly reduced, and the practical effects will be even greater.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the counting device of the present invention.

In this embodiment, the conventional interrupt processing request is broadly interpreted as a processing request from a peripheral device or an internal circuit (hereinafter, the interrupt request is referred to as an I/O request).
Take it as

A hardware counter 105 with the number of bits n counts the count clock 105-1, and when an overflow occurs, an overflow signal 105-2 is sent.
Output. A counter processing control unit 500 that controls processing performed due to the occurrence of an overflow,
an I/O request control unit 205 that controls I/O requests;
An I/O processing execution request line 205-1 that requests processing to the central processing unit, an I/O processing execution form specification line 205-2 that specifies an I/O processing form, and an I/O processing execution request line 205-. 1 and an I/O processing execution mode designation line 205-2, the I/O request receiving unit 206 controls the operation of a central processing unit (hereinafter referred to as CPU) 510. CPU510
is a PC 101-1 that indicates the address of the program memory 102 to be executed next, a PSW 101-2 that indicates the operating status of the entire CPU 510, a general-purpose register set 101-3 that holds data being processed, and an arithmetic logic register that has an arithmetic logic operation function. Arithmetic unit (hereinafter referred to as ALU) 201, instruction register 202 that holds instructions to be executed, instruction register 202
By the output of the instruction coder 203 and instruction decoder 203, which decode the contents and generate various control signals,
Execution control unit 2 that controls the overall operation of the CPU 510
It has 04. The data memory section 103 also has a count data storage area 103-- which stores m-bit count data as a software counter.
1. All of the above sections are connected to an internal bus 106.

Next, the operation in counter processing will be described.

The n-bit hardware counter 105 counts the count clock 105-1, and when an overflow occurs as a result, an overflow signal 1 is generated.
Outputs 05-2. The I/O request control unit 205 receives the overflow signal 105-2 and sends an I/O processing execution request line 2 to the I/O request reception unit 206.
05-1 is the active level, and at the same time I/O
The process execution mode designation line 205-2 is set to high level. When the I/O processing execution request line 205-1 becomes active, the I/O request receiving unit 206 detects that the I/O processing execution mode specification line 205-2 is at a high level, and executes the processing by the macro service. Detects that the In order to process this I/O request using the macro service, the I/O request receiving unit 206 controls the execution control unit 204 to
-1 increment is prohibited, PC101-1,
PSW101-2, general-purpose register set 101-
While maintaining the value of 3, start the process shown below.

First, the I/O request control unit 205 reads the data in the software counter 103-1, then increments the read data and stores it in the software counter 103-1 again. The above series of processes completes the software counter data increment and transfer process in one macro service. and hardware counter 10
The above-mentioned macro service is repeated every time an overflow occurs in the software counter 103-1, and when the execution control unit 204 detects that an overflow has occurred from the software counter 103-1, the execution control unit 204 performs the conventional interrupt processing described below. Software counter overflow signal 204 from execution control unit 204
-1 becomes active, the I/O request control unit 2
05 activates the I/O processing execution request line 205-1 again and also connects the I/O processing execution mode specification line 205-2 to generate a conventional interrupt request.
is the low level. Then, the I/O request accepting unit 206 starts the interrupt processing program and executes the interrupt processing by software similar to that when an overflow occurs in the conventional (n+m) bit counter.

FIG. 2 shows the count clock 105-1, bit n of the hardware counter 105, and the overflow signal 105-1 of the hardware counter 105.
2. This is a timing chart of bit m of the software counter 103-1 and the overflow signal of the software counter 103-1. Let the period of count clock 105-1 be _T0 . The most significant bit n of the hardware counter 105 is the time.
Incremented once to T ₀ ×2 ^n-1 , time T ₀ ×
An overflow signal 105-2 of the hardware counter 105 is generated at intervals of ²ⁿ , and the macro service is executed. As the software counter 103-1 continues to be incremented by the macro service, the most significant bit m of the software counter 103-1 is incremented once every time T ₀ ×2 ^n+m-1 , and as a result, the time T An overflow signal of the software counter 103-1 is generated at intervals of ₀ ×2 ^n+m .

〔Effect of the invention〕

As explained above, in accordance with the present invention, the execution unit automatically accesses the count value in the count data storage area used as the upper counter in the data memory in response to an I/O request generated from the hardware counter. By storing the count value back into the original count data storage area, even if the number of bits in the hardware counter is reduced, the count data value can be incremented and transferred without any overhead, reducing CPU processing. It has the effect of suppressing the decline in ability as much as possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the counting device of the present invention, FIG. 2 is a time chart thereof, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a time chart of a conventional example. 100...Microcomputer, 101...
Execution unit, 101-1...Program counter (PC), 101-2...Program status word (PSW), 101-3...General-purpose register set, 102...Program memory, 103
...Data memory, 103-1...Software counter, 104...Interrupt control unit, 104-1
...Interrupt request line, 105...Hardware counter, 106...Internal bus, 201...Arithmetic logic unit (ALU), 202...Instruction register, 203...Instruction recorder, 204...Execution control section, 204 -1...Software counter 10
3-1 overflow signal, 205... I/O request control unit, 205-1... I/O processing execution request line, 205-2... I/O processing execution mode specification line,
206...I/O request reception unit, 500...Count data processing control unit, 510...Central processing unit (CPU).

Claims (1)

[Claims] 1. A hardware counter that counts clocks and outputs an overflow signal, a memory unit having a count storage area that stores a predetermined count, a central processing unit that executes a program in a program memory, and the central processing unit. and a counter processing control section that controls processing for a special interrupt request issued to the computer or processing for a normal interrupt request from a peripheral device, and the counter processing control section receives the overflow signal as a special interrupt signal. a program counter that constitutes the central processing unit when
The state of the program status word and general-purpose registers is maintained as is, the processing of the central processing unit by the program is interrupted, and the contents of the count number storage area are read out and incremented in the central processing unit, and then stored in the count number storage area. A counting device characterized in that after rewriting, the processing of the central processing unit by the program is resumed, and when an interrupt request from the peripheral device is received, normal interrupt processing is performed.