JPH0531864B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image sensor that converts optical information into electrical signals.

[Technical background of the invention and its problems]

Various types of image sensors are known for use in image input devices such as facsimiles and OCR, but in recent years there has been active development of elongated one-dimensional image sensors that have a light-receiving width that is approximately the same as the width of the document. .

It has a configuration in which a plurality of photoelectric conversion elements such as one-dimensional image sensors are arranged in an array,
For example, information for one line is obtained by sequentially selecting individual photoelectric conversion elements using switching elements and reading out signals.

The problem here is noise on the optical information signal. Noise during driving of the switching element has a large effect. Furthermore, in recent years, there has been a demand for higher definition image reading, and photoelectric conversion elements have been subdivided accordingly. Therefore, the light receiving area is reduced and the photocurrent is further reduced. Furthermore, there is a demand for faster reading speed, for example, the accumulation time when reading signals in accumulation mode is shortened, and the accumulated photocharges are further reduced.

As described above, as the photocurrent decreases with higher definition and higher speed, the above-mentioned noise problem becomes more prominent.

To deal with this problem, we first read signal A containing optical information as a signal from the photoelectric conversion element, then read out signal B containing noise that does not contain optical information, and then perform differential amplification (A-B). A method of canceling the noise (hereinafter referred to as the double pulse method) by taking
H Contact Linear Image Sensor “Kajiwara”
Yuji et al.).

Although this kind of double-pulse method certainly cancels noise, compared to reading with a single pulse, if reading is performed at the same speed, the switching element is required to have twice the switching speed, and the high-frequency characteristics There were also problems such as this, and there was a limit to high speed. Further, in addition to the drawback that the circuit configuration is complicated because a means such as sample and hold is required, the sample and hold circuit also has a drawback in increasing the speed.

Research is also being conducted on a configuration that uses a CMOS configuration switch to reduce switching noise and performs differential amplification to cancel the noise (“Design And Evaluation of A4 Amorphous
Si Hybrid Image Sonsor”T.Ozawa et.al.：
PROC.of the 1982IMC P.132-137). This is because it is difficult to cancel switching noise by simply using a switch with a CMOS configuration, and although it may be superior to the double-pulse method in terms of readout speed, it is difficult to cancel the switching noise by simply using a switch with a CMOS configuration. However, the drawback was that the noise could not be canceled completely.

[Purpose of the invention]

The present invention was made in consideration of the above points, and
An object of the present invention is to provide an image sensor with reduced noise and capable of high-speed reading.

[Summary of the invention]

The present invention provides an optical sensor including a plurality of photoelectric conversion elements and a plurality of switching means connected to the plurality of photoelectric conversion elements,
As the switching means, source electrodes and drain electrodes of two field effect transistors having the same product of gate capacitance and gate voltage change and complementary conduction types are connected to each other, and the field effect transistors are simultaneously turned on. The image sensor is characterized in that it uses a switching circuit that is in a conductive state, and has a resistance value of 0.8 to 10 KΩ when the switching circuit is in a conductive state.

As the photoelectric conversion element, for example, one having a so-called sandwich structure in which a photoelectric conversion layer is sandwiched between a lower electrode and a transparent electrode is used.

As the photoelectric conversion layer, inorganic photosensitive materials such as amorphous Si (a-Si), amorphous SiC, and poly-Si, which are generally known as materials that convert the amount of light into electrical quantities such as changes in charge and conductivity, and merocyanine, Those using organic dyes such as phthalocyanine, pyrylium, squarium, etc., and organic photoconductive materials using porphyrin, ruthenium trispipyrine complex, titanium oxide and methyl viologen, etc. can be used. It is preferable to use a-Si from the viewpoint of photoresponsiveness.

As the light-transmitting electrode, it is possible to use a material that has conductivity and allows light to pass through, such as a generally known NESA film, an ITO film, or a thin gold film.

In addition, as the lower electrode, commonly used
Those in which various metals such as Al, Cr, Ti, V, and In are provided by vapor deposition, sputtering, etc. are used.

In the image sensor of the present invention, p-ch and n-ch field effect transistors (hereinafter referred to as FETs) are simultaneously turned on (hereinafter referred to as FETs) as switching means.
ON) using a switching circuit (hereinafter referred to as a complementary switch), the resistance value of this conduction state (hereinafter referred to as ON) is used.
Use one with a resistance (Ron) of 0.8 to 10KΩ.

When a complementary switch is used, the noise charge Qp and the n-
The noise charge Q _N of chFET is n-chFET, p-
It is known that by turning on the chFETs at the same time, they cancel each other out and reduce noise (Japanese Patent Publication No. 14925/1983). This is because voltages with opposite phases are applied to n-ch and p-ch, so Qp and Q _N
This is because they have opposite signs and are canceled out. here
Since it is required that Qp=-Q _N , it is sufficient to make the product of gate capacitance and gate voltage change equal. When voltages with opposite phases and the same absolute value are used as gate voltages, it is sufficient that the gate areas are equal. Although there are many manufacturing errors, if they are substantially the same, the same effect will be obtained.

As described above, as the definition of image sensors progresses, the signal current becomes minute, and the influence of switching noise on this signal becomes greater. According to the present invention, by increasing the on-resistance to 0.8-10KΩ, the absolute amount of switching noise is reduced.

RoN is determined by the gate area, but general switching elements are usually designed to have a small RoN, so the gate area is made as large as possible, and general-purpose devices have _RoN = 50 ~
It is about 500Ω. In the present invention, in order to minimize the amount of switching noise, _RoN is
We used a complementary switch with a large resistance of 0.8 to 10KΩ and a small gate area. In the case of the above-mentioned general-purpose switch, the amount of noise is about 16 to 200 times higher, and a means such as differential amplification as mentioned above is required, but in the present invention, the absolute amount of noise is smaller, so a new Since there is no need to perform differential amplification, it is also very effective in terms of circuit configuration.

The lower limit of Ro _N is set to 0.8KΩ because if it is too small, the gate area will become large and the absolute amount of noise will become large. Also preferably
A range of 1.5KΩ or more is desirable.

Furthermore, the upper limit is set to 10KΩ because if it is too large, the switching speed will become slow.

For example, when using a public electricity conversion element in storage mode, if Ro _N is too large, the rise of the signal current will be delayed due to the relationship with the capacitance (Cs) of the photoelectric conversion element. Considering variations in the switching means, etc., the signal is read out after 4τ (τ=Cs・Ro _N ) has elapsed (approximately 98% of the final value). However, if the rise is slow, that is, if τ is large, the time required to read the signal will be longer. It gets long. Therefore, it is desirable that RoN≦10KΩ, preferably _RoN ≦5KΩ.

It also varies depending on the Ro _N applied voltage, etc., but usually
Since it is used near the maximum value of Ro _N ((Ro _N )max), (Ro _N )max is 0.8 to 10KΩ, preferably 1.5 to
It is desirable to satisfy 5KΩ.

〔Effect of the invention〕

As described above, according to the present invention, by setting the ON resistance of the complementary switch for reading to 0.8 to 10 KΩ, it is possible to obtain an image sensor that reduces the amount of noise and is capable of high-speed reading. It is particularly suitable as an image sensor that operates in an accumulation type with a small signal.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 1 is a circuit diagram of an image sensor in accumulation mode showing this embodiment.

A plurality of photoelectric conversion units D _o (n = 1 to N) that generate a signal current corresponding to the amount of incident light, and a capacitance unit Cn (n = 1 to N) that accumulates the signal current as a charge.
A plurality (N) of photoelectric conversion elements An (n=1 to N) having N) are provided. One end of the photoelectric conversion element An is commonly connected to the bias power source E, and the other end is connected to the common output line C via switching means B _o (n=1 to N). This switching means B _o is sequentially selected by the shift register S and turned ON.
The signal from each photoelectric conversion element A _o passes through the common output line C and is read out via the amplifier P and the feedback resistor R.

The switching means B _o has a CMOS configuration,
Behind the leased key between N channel FET (QnN; n=1~N) and P channel FET (QnP; n=1~N),
The drain electrodes are connected to each other, and voltages of opposite phases are applied simultaneously by an inverter circuit (In; n=1 to N).

This figure shows a structure using C-MOS FET as a switching means. Figure 2 a is a cross-sectional view, b is pch-
FIG. 3 is a plan view showing gate dimensions of a MOS FET.

This C-MOS FET is formed by a normal CMOS process as shown in FIG. 2a. That is, a p-well diffusion layer (p
- well), P ⁺ diffusion layer (P ⁺ ), N ⁺ diffusion layer (N ⁺ ), and oxide film a such as SiO ₂ are provided, and gate electrode ( ), source/drain contact electrode ( ), and wiring pattern are provided. is usually made from Al.
For the gate electrode, polysilicon, highly doped amorphous silicon, or the like may be used in addition to Al. In b, the gate dimensions are represented by l and w, and the value of on-resistance is proportional to l and inversely proportional to w. The capacitance of the gate is proportional to the product of l and w as a zeroth order approximation, and is inversely proportional to the thickness t of the oxide film under the gate electrode. t
Since it affects the threshold voltage of FET,
Usually around 1000Å is chosen. In this example, nch−
The gates of MOS and pch-MOS have the same shape and area, and voltages with the same absolute value and opposite phase are applied as gate voltages. In order to reduce noise, it is sufficient to reduce l and w. as l
Using 5μm, which is the normal wiring rule for CMOSIC,
By setting w=60μm, the on-resistance is equal to the gate,
It depends on the voltage between the source and drain, but it is about 2KΩ. By using the 2μ rule, both l and w can be made smaller, ensuring the necessary on-resistance, while also reducing the gate capacitance to about 1/5 compared to the 5μ rule, resulting in a more suitable image sensor.

Generally, to read out an image sensor that operates in accumulation mode, Cn and the on-resistance of the switching means Ro _N
The readout time constant τ is determined by the product of
It has reached 98%.

High speed and high speed required for facsimile OCR etc.
As an example of high resolution and long length, 1ms/line, 16
readout clock frequency 5MHz required for A3 (approximately 300 width), i.e. clock period 200ns
In this case, the required τ is preferably 4τ or later, considering circuit delay time, Ro _N variation, facsimile, A/D conversion time when used for OCR, etc., and 4τ = about 100ns. is desirable. On the other hand, in a photoelectric conversion element using amorphous silicon, for example, the Cn is about 3 to 40 pF, and the switching means is formed as an integrated circuit chip on the same substrate as the photoelectric conversion element, resulting in less noise. Applying the implementation method,
A suitable value for Cn is about 10 pF. Calculating R from this, 4Cs・Ro _N = 100ns, Ro _N =
2.5KΩ, Ro _N
=0.83~10KΩ.

FIG. 3 shows a circuit diagram of one photoelectric conversion element A1 in FIG. ₁ . The symbols in the figure are the same as those in FIG. 1, and their explanation will be omitted. In addition, R, C
is wiring resistance and stray capacitance. Figure 4 is a voltage conversion diagram, where a is the gate voltage V _Go of Q _1N , b is the switching noise V _NN of Q _1N , and C is the gate voltage of Q _1p .
V _Gp , d is the switching noise V _Np of Q _1p , e is the noise (V _h =V _NN +V _Np ), and f is the output voltage V ₀ .
For convenience, the times t in FIGS. 4a to 4f are aligned. Since Q _1N and Q _1p are simultaneously driven via the inverter circuit τ ₁ , some deviation occurs, but as shown in Fig. 4c, this deviation is as small as t ₀ = 5ns, so it is shown in Fig. 4e. As shown, the noise of V _N coexists temporarily, but due to the wiring resistance R and stray capacitance C shown in Fig. 3, or the filter effect due to the amplifier bandwidth that has an equivalent effect, the RC integration circuit, etc.
Naturally, the low noise output voltage as shown in Figure 4f
V becomes ₀ .

As described above, by using a complementary switch and setting Ro _N to 0.8 to 10 KΩ as in the present invention, the gate area is reduced and the amount of switching noise is reduced. Furthermore, the time required for switching is approximately 100 ns, allowing high-speed reading.

Further, an amplifier circuit P _o (n=1 to N) may be provided between the photoelectric conversion element An and the switching means B _o shown in FIG. 1, respectively. Generally, since the signal generated by photoelectric conversion is small, the S/N ratio can be further improved by once amplifying the signal and then passing it through the switching means B _o . This circuit diagram is shown in FIG. Photoelectric conversion element
An amplifier circuit Pn is interposed between An and the switching means Bn, and a reset switching means B'n (n=1 to N) is provided between the photoelectric conversion element An and this amplifier circuit Pn.
It is the same as in FIG. 1 except that .

In the circuit shown in FIG. 4, the switching means
The feature is that an amplifier circuit Pn is individually provided before Bn. By amplifying the signal before the switching means Bn, which is the source of noise, the S/N ratio is improved as described above. Further, an amplifier circuit may be further provided at the final stage of the common output line as in FIG. 1. When such an amplifier circuit Pn is provided, a means for once returning the photoelectric conversion element An to its initial state after signal reading may be required. This can be returned to, for example, the ground potential after the signal is read out by, for example, the reset switching means B'n. This reset switching means Bn is a switching means B'n
For example, B′n is driven using a signal that drives B _o+1 . In this way, after An is read out, An will return to the reference potential when A _o+1 is read out. Furthermore, in the circuit shown in FIG. 4, a complementary switch similar to the switching means Bn is used as the reset switching means B'n to prevent the switching noise of this B'n from being superimposed on the signal.

Generally, the shift register S, switching means, etc. are grouped together as an integrated circuit element (IC).
Figure 6 shows the layout diagram of the IC.

The periphery of this IC is divided into two areas.
In the first region 1, for example, on three of the four sides of the IC chip, only connection terminal portions 2a for input from a photoelectric conversion element are formed, and other connection terminal portions 2b are formed, for example, for power supply, input signals of a shift register, etc. A clock signal and the like are formed in the second region 3, for example on the other side. Note that the connection terminal portions 2a are arranged in a staggered manner, and noise is reduced by separating the connection terminal portion 2a for input from the photoelectric conversion element from the other connection terminal portions. Furthermore, since the input connection terminal section 3-1 is formed in one area of the integrated circuit element, there is no need for multilayer wiring, and mounting on the board becomes easy.

In general, the input signal from a photoelectric conversion element is very small, on the order of mV, compared to about 5V of a shift register clock signal, for example, and is therefore easily influenced by such a clock signal. However, by separating the connection terminal section for input signals from other connection terminal sections in this way, the above-mentioned influence can be reduced, so that noise can be reduced.

Furthermore, a switching means 4, a power supply wiring 5a, a common output line 6, a power supply wiring 5b, a common output line 6, a power supply wiring 5b, and a shift register 7 are formed in this order inside the first region. The state of each connection is omitted. By configuring the common output line 6 in such a manner that the power supply wiring lines 5a and 5b are narrowed, capacitive coupling with the pulses etc. that drive the switching means 4 and the shift register 7 is prevented.
Noise caused by this is reduced. Further, the power supply wirings 5a and 5b have a second effect on the first region 1.
In order to prevent the influence of the region 3, it is preferable to extend it to the boundary between the first region 1 and the second region 3 (5a', 5b' in the figure).

Of course, it is also possible to form an amplifier circuit on this IC, and in particular, by forming and integrating the amplifier circuit Pn on the same substrate as shown in Figure 5, variations in offset voltage can be minimized. Can be made smaller. In addition, the final stage amplifier P shown in FIG.
It goes without saying that these may be formed on the same substrate, but separate amplifier circuits may be connected.

Next is the wiring pattern on the board on which the IC shown in FIG. 6 is mounted.

Ceramic in which IC and photoelectric conversion block are formed,
A wiring pattern is formed on an insulating substrate such as glass by, for example, photolithography technology.

The process of creating the wiring pattern on this board will be explained using FIG. 7. FIGS. 4a to 4g are cross-sectional views showing the formation of a wiring pattern on the substrate 101 in the order of steps.

To avoid adverse effects on photoelectric conversion element characteristics
Alkali-free glass substrate 10 such as Corning 7095
Cr101 with a thickness of 100 to 300 nm is placed on the top of 0 (Fig. 6a) as an adhesive layer with the glass and as a lower electrode of the photoelectric conversion element.
Vapor deposition is performed on the entire surface (Fig. 6b).

Next, using the mask vapor deposition jig 102, Cr104 (10 to 50n
m) Evaporate Au105 (0.8 to 1.5 μm) (6th
Figure c). This film can be continuously deposited by electron beam evaporation without breaking the vacuum. A recess 102' is provided on the lower surface of the mask deposition jig 102 so as not to damage the lower electrode 103.

Next, a photoresistor 106 is provided by a spin coating method, a roll coating method, etc. (FIG. 6d),
A desired resist pattern is obtained by exposing through a photomask (not shown) (FIG. 6e).

Next, Au105 is etched with a normal etching solution such as iodine and potassium iodide, and then Cr10
4,101 is etched with an etching solution such as ceric ammonium nitrate and perchloric acid diluted in water (Fig. 6g), and then the resist 106 is peeled off to obtain the desired wiring pattern (Fig. 6g). .

Moreover, Cu and Au may be used instead of Au105. In this case, the underlying Cu is 1 to 3 μm thick, and the Au is 0.1 to 3 μm thick.
By setting the thickness to 0.3 μm, it is possible to create an image sensor with high conductivity and high bonding reliability at extremely low material costs. This is because Cu has higher conductivity than Au. If Au is too thin, there will be problems with bonding strength, and if Cu is too thin, it will have little effect on increasing conductivity. Therefore, the above range is preferable. In this case, since Cu can be etched simultaneously with Au using an aqueous solution of iodine and potassium iodide, no problems arise in the process. However, the above Cr
In the etching solution (perchloric acid diluted with ceric ammonium nitrate), sand etching occurs because the etching rate of Cu is faster than that of Cr, but this is due to potassium ferricyanide.
By using an aqueous solution of NaOH or KOH
Since only Cr can be etched, this is not a problem.

A photoelectric conversion layer and a transparent electrode are formed on the substrate on which the wiring pattern is formed in this manner, thereby forming a photoelectric conversion element. For example, an a-Si layer is formed on the lower electrode 103 shown in FIG. 7 by CVD method,
A photoelectric conversion layer is formed, and a light-transmitting electrode is formed by sputtering an ITO film to form a photoelectric conversion element with a so-called sandwich structure. At this time,
By dividing the lower electrode into a plurality of parts, an array of photoelectric conversion elements is formed.

Next, the IC 10 shown in FIG. 6 is mounted on the board. FIG. 8 shows a partial plan view of the substrate. Positive power supply wiring pattern 12- formed on substrate 11
The IC 10 is fixed onto the substrate 1 using, for example, a thermosetting conductive epoxy resin. Positive power wiring pattern 1
What was fixed on 2-1 was an N-type substrate C-MOS IC.
This can be changed as appropriate depending on the conductivity type of the IC. The location where this IC 10 is fixed has approximately the same dimensions as the IC 10 in order to keep the substrate potential stable.

Bonding pads 12-2' of lead-out wiring patterns 12-2 drawn out from the electrodes of each photoelectric conversion element are formed on the substrate 11 so as to face the connection terminals 2a for input from the photoelectric conversion elements of the IC 10. are formed and connected by bonding wires 13, respectively. For example, an Au wire with a diameter of 30 μm is generally used as the bonding wire 13, and the dimensions required for the bonding pad are 100 μm to 130 μm.
It is about m square. Bonding pad 12-2'
Since the photoelectric conversion elements are arranged in a staggered manner, for example, even if the photoelectric conversion elements are 16 elements/mm, they can be formed at a density of 8 elements/mm.

Further, as in the case of the above-described IC, the common output line 12-3 is separated from the input signal pattern 12-4 and clock signal pattern 12-5 of the shift register by a power wiring pattern on the substrate 11. In other words, the common output line 12-3 is the ground wiring 12-
It is located between 6 and 12-7. In particular, since the negative power supply wiring pattern 12-8 is further interposed between the clock signal pattern 12-5 and the clock signal pattern 12-5, noise reduction is more effective. Also, the common output line 12- is connected to the ground wiring 12-6, 12-7.
3, it is possible to prevent the superposition of DC leakage current due to dirt, moisture, etc. on the surface of the substrate 11, for example, without forming a new protective film or the like.

Furthermore, in order to stabilize the substrate potential of IC10, the positive power supply wiring pattern 12-1 and the ground wiring pattern 1
A chip capacitor 13-1 of about 0.1 μF is fixed as close to the IC 10 using conductive resin or the like between 2 and 6 to absorb spike noise superimposed on the power supply. In the negative power supply wiring pattern 12-8, a chip capacitor 13-2 is similarly connected between the ground wiring 12-6.

The effect of the chip capacitors 13-1 and 13-2 for absorbing spike noise becomes even more effective by making the power supply wiring pattern and the ground wiring thicker and lowering the wiring impedance.

In addition, since the lead wiring pattern 12-2 is also separated from the shift register signal, clock signal, etc. by the power supply wiring pattern 12-1, noise is reduced. Furthermore, as mentioned above, IC1
Since the input connection terminal portion from the photoelectric conversion element is formed in one area of 0, the wiring distance can be minimized, which is very effective in reducing noise.

In an actual image sensor, one chip
By assigning multiple photoelectric conversion elements to an IC, this IC
A long image sensor for one line is constructed by using a plurality of . This situation is shown in FIG. For example _, an IC _o (n= _{1 to} M) having _the configuration shown in FIG. element
The input from An is connected to the common output line C. IC _o is multiple photoelectric conversion elements
An, switching means Bn and a shift register, and an amplifier circuit Pn as required.

When a plurality of ICs are mounted on a substrate in this manner, it is possible to easily make the wiring pattern longer by repeatedly manufacturing the wiring pattern for one IC chip as shown in FIG. The photomask in this case can be easily manufactured by repeating a pattern for one IC chip as described above using, for example, CAD technology.

Furthermore, it is possible to distribute electrodes alternately on both sides of the photoelectric conversion elements arranged in an array, and to mount ICs on the left and right sides of this row of photoelectric conversion elements. This situation is shown in FIG. 10 as a plan view.

From the photoelectric conversion element group 21 formed on the substrate 20, lead lines 22 are formed alternately on the left and right.
Therefore, even if the photoelectric conversion element group 21 is formed with, for example, 16 pieces/mm, the number of bonding pads for connection with the IC 23 will be 8 pieces/mm, making the connection easy.

Furthermore, if the clock signals of the shift registers input to the IC 23 located in the left half and the IC 23 located in the right half of FIG. 10 are shifted by 180 degrees, one column of optical information can be sequentially read out.

In the image sensor according to the present invention, switching noise is reduced by setting Ro _N of the complementary switch to 0.8 to 10KΩ, but as shown in this example, the layout on the IC and the wiring pattern on the board are further improved. By devising this method, noise caused by wiring can be further reduced, which is effective.

In addition, in this example, the photoelectric conversion element and the IC were mounted on one substrate, but the photoelectric conversion element part and the IC mounting part were formed on separate substrates, and then fixed on one substrate to be integrated. It may be changed into By separately manufacturing the photoelectric conversion element, the photoelectric conversion element can be manufactured without any extra steps, so that deterioration of characteristics can be prevented.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the image sensor of the present invention, Figure 2 is a cross-sectional view and plan view of the IC of the image sensor of the present invention, Figure 3 is a circuit diagram of the image sensor of the present invention, and Figure 4 is an image of the present invention. 5 is a circuit diagram of the image sensor of the present invention; FIG. 6 is a plan view of the IC of the image sensor of the present invention; FIG. 7 is a sectional view showing the image sensor of the present invention in the order of manufacturing steps; FIG. 8 is a partial plan view of the image sensor of the present invention, FIG. 9 is a circuit diagram of the image sensor of the present invention, and FIG. 10 is a partial plan view of the image sensor of the present invention. A ₁ ...A _N ...Photoelectric conversion element, B ₁ ...B _N ...Switching means, Q _1N ...Q _NN ...n-ch FET, Q _1p ...
Q _Np ... p-ch FET, I ₁ ... I _N ... inverter circuit, S ... shift register, P, P ₁ ... P _N ... amplifier circuit.

Claims (1)

[Scope of Claims] 1. An optical sensor comprising a plurality of photoelectric conversion elements and a plurality of switching means connected to the plurality of photoelectric conversion elements, wherein the switching means is configured to change gate capacitance and gate voltage. A switching circuit is used in which the source electrodes and drain electrodes of two field effect transistors having the same product and complementary conduction types are connected to each other, and the field effect transistors are simultaneously rendered conductive. An image sensor characterized by a resistance value in a conductive state of 0.8 to 10KΩ. 2. The image sensor according to claim 1, wherein the field effect transistors having conductivity types complementary to each other have the same gate area. 3. The image sensor according to claim 1, wherein the resistance value is 1.5 to 5KΩ.