JPH0532935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase locked circuit for burst signals.

Conventionally, phase-locked circuits have been widely used for carrier wave regeneration in wireless communications, regardless of whether the input signal is continuous or burst-like. If the input signal is continuously input, there is no particular problem because the synchronization state once established is stably maintained. On the other hand, when the input signal is in the form of a burst, the synchronization state that has been established for a certain period of time from the beginning of a certain burst will be disturbed at the end of that burst. That is, reception noise is input to the phase locked circuit, and an equivalent noise shift θ _o (t) caused by this noise appears at the output of the phase difference detector. Ideally, the average value E{θ _o (t)} of the same sitter
Since is zero, it is smoothed by the loop filter, and the output frequency of the voltage controlled oscillator (VCO) maintains the value at the time of synchronization. However, in reality, the short-term E{θ _o (t)} is not zero, and in cases where there is a DC offset in the loop filter, and when the loop filter includes a perfect integrator, These DC imbalances cause drifts in the loop filter output. This drift directly appears as an output frequency drift of the voltage controlled oscillator. Therefore, when the next burst signal is received, a large frequency difference will occur between the input signal and the voltage controlled oscillator frequency, and a long pull-in time will be required again.

An object of the present invention is to suppress the frequency drift of a voltage controlled oscillator when there is no signal between bursts.

This invention includes two storage elements in the loop filter.
In a synchronization circuit that synchronizes with the phase of a burst signal using one or more of the following phase synchronization circuits, the storage contents of the storage element are allowed to be changed only when the burst signal is applied to the input, and the burst signal is applied to the input. The phase synchronized circuit for burst communication is characterized in that when no voltage is applied, the operation of the storage element is stopped, and a voltage controlled oscillator is controlled by a variable output of a phase difference detector and a fixed output of the storage element.

According to this invention, the frequency drift of the voltage controlled oscillator when there is no signal between bursts is suppressed, and when the next burst starts, only the phase difference is absorbed, so that it is possible to avoid the occurrence of a long unnecessary pull-in time. can.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a block diagram of a commonly used second-order phase-locked circuit. In the figure, 1 is a multiplier that functions as a phase difference detector, 2 is a voltage controlled oscillator, and 3 is a loop filter that includes a perfect integrator 30 and transmits it together with coefficient circuits 31 and 32 that multiply inputs by α and β, and an adder 33. The function constitutes a filter of F(s)=β+α/s. Here, the average output frequency information of the voltage controlled oscillator is stored in this perfect integrator 30.

Figure 2 shows the perfect integrator 3 for burst-like input.
This represents a change in the content of 0, that is, a change in the output frequency of the voltage controlled oscillator. Figure a-1
00, 101, 102 and 103 are burst input signals. Figure b shows changes in the frequency difference Δf between the input signal and the output of the voltage controlled oscillator in an ideal case. In this case, as described above, the established synchronization state is maintained even in the inter-burst no-signal periods 200, 201, and 202. In other words, Δf remains at 0.

On the other hand, in actual cases, as described above, due to various imperfections, a voltage controlled oscillator frequency drift occurs in the inter-burst no-signal periods 200, 201 and 202 as shown in c in the figure. Therefore, Δf will move away from zero in this section. Therefore, a very large Δ f occurs at the beginning of the burst 102, and a new long pull-in time is required.

FIG. 3 is a diagram showing a block diagram of one embodiment of the present invention. Headache 1, 2, 30, 31, 32, 3
3 is identical to the same reference numbered element in FIG.

Information indicating the end of the burst is input to the input terminal 301. For example, Intelsat's Spade system uses the End of Message (EOM) signal. Therefore, by opening the switch 34 when the same signal is input, the subsequent operation of the perfect integrator can be stopped. Since large frequency changes are not expected within a relatively short period of time between bursts, once a synchronized state is maintained, it is sufficient to apply to the next burst. Integrator 30
is dormant, but its output continues to be applied to the voltage controlled oscillator input. switch 34
When the fuse lock loop is open, it operates as a primary system. During this operation, the phase difference can be quickly absorbed at the beginning of the next burst signal without significantly changing the frequency of the voltage controlled oscillator. Information indicating that a new burst has been applied to the input is again applied to input terminal 301, causing switch 34 to close and continue phase locking operation on the burst signal as a secondary fuse lock loop. For example, in Intelsat's Spade System, the Start of Message (SOM) signal can be used as burst start information.

As explained above, according to the present invention, the frequency drift of the voltage controlled oscillator when there is no signal between bursts is suppressed, the function of tracking only the phase difference as a primary loop is suspended during that period, and the function of tracking only the phase difference is suspended at the beginning of the next burst. , it is possible to configure a phase synchronization system that quickly completes phase pull-in.

Normally, even in a frequency synchronized state, the input signal and the synchronized system do not completely match in frequency, and therefore, if the uncontrolled state continues, phase errors caused by this frequency error will accumulate.

In the present invention, in order to promptly synchronize this phase error as soon as the beginning of the next burst signal is received,
The primary loop is designed not to stop its operation. The frequency synchronization condition in question continues because the operation of the loop filter is suppressed.

Although the example of the second-order fuse lock loop was explained in the embodiment shown in FIG. 3, the operation of all memory elements (integrators) other than the voltage-controlled oscillator will also be explained in the case of a second-order or higher order. The same effect is expected by suspending.

In addition, although we have only explained loop filters that include perfect integrators, loop filters that include leaky integrators made of ordinary CR circuits can also retain the contents of their memory elements between bursts. Therefore, similar effects can be obtained.

A gated system that operates a phase locking system only when an input signal is present is similar to the same invention.
Fuyuz Rock Loop (Gated Phase)
Loched Loop), but this stops all operations of the Loop when there is no input signal, or fixes the output of the phase difference detector, including the currently remaining phase difference. This is essentially different from the present invention because it attempts to keep the behavior of the voltage controlled oscillator as close to its current state as possible.

In addition, for each station that the TDMA receiving station should receive,
Some attempts have been made to shorten the pull-in time by inputting separate memory contents to the memory elements prior to synchronization, but this is not practical because the phase synchronization system does not perform meaningful synchronization between each TDM burst. Different from invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a secondary phase-locked circuit, FIG. 2 is a diagram for explaining the operation of the phase-locked circuit in response to a burst signal, and FIG. 3 is a block diagram of an embodiment of the present invention. Figure shown. In the figure, 1 is a multiplier, 2 is a voltage controlled oscillator, 3 is a loop filter, 30 is a perfect integrator as a storage element, and 34 is a switch for stopping the operation of the perfect integrator.

Claims (1)

[Claims] 1. Phase for burst communication that synchronizes with the phase of a burst signal using a phase synchronization circuit of secondary or higher order consisting of a phase difference detector, a loop filter having a memory element, and a voltage control oscillator. In the synchronous circuit, the phase difference detector detects a phase difference between the burst signal and the output signal of the voltage controlled oscillator, and the loop filter includes opening/closing means at a stage before the storage element, and the loop filter is configured to detect the burst signal. When the input is applied, the opening/closing means is closed to allow the storage contents of the storage element to be changed, and when the burst-like signal is not applied to the input, the opening/closing means is opened to allow the storage contents of the storage element to be changed. A phase synchronized circuit for burst communication, wherein the voltage controlled oscillator is controlled by a fluctuating output of the phase difference detector and an output of the storage element.