JPH0533541B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement of a master slice type semiconductor integrated circuit having a functional block area.

[Technical background of the invention and its problems]

In a master slice type semiconductor integrated circuit equipped with functional blocks, a plurality of functional blocks and a plurality of cell rows, which are a collection of basic cells composed of a plurality of elements, are arranged in advance on a semiconductor substrate to form a master chip. The desired logic function is realized by applying metal wiring to the logic circuit. In conventional master slice type semiconductor integrated circuits that are equipped with functional blocks, the spacing between opposing cell rows is determined by the master chip, similar to the conventional master slice type integrated circuits that do not have functional blocks. It has a constant width, and in this area, metal wiring is used to connect each cell and between each cell and a functional block.

In such a conventional structure, a vacant area is more likely to occur in the wiring area where the cell row length is short than in the wiring area where the cell row length is long. There is a strong correlation between the number of cells included in one cell column and the wiring area between that cell column and the opposing cell column, and this is generally necessary for wiring as the number of cells included in one cell column increases. This is due to an increase in the number of areas. Therefore, since the spacing between each cell column is made the same in both the long and short cell column length sections as in the conventional method, there is a problem in that empty areas tend to occur in the wiring area of the short cell column length sections.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type semiconductor integrated circuit having functional blocks that can be highly integrated without reducing the chip utilization rate by reducing the amount of free space in the wiring area.

[Summary of the invention]

The gist of the present invention is to narrow the interval between opposing cell rows in a portion where the cell row length is short compared to a portion where the cell row length is long.

In general, there is a close relationship between the number of cells included in one cell row and the number of wires parallel to the cell row, that is, the number of tracks required for wiring between that cell row and the opposing cell row. It has been known. Furthermore, the present inventors found that when the number of cells included in one cell column doubles, the number of tracks between that cell column and the opposing cell column tends to increase by 1.3 to 1.4 times. . Focusing on this point, the inventors have conducted intensive research and found that in master slice type semiconductor integrated circuits equipped with functional blocks, there is wasted space between opposing cell rows in short portions of cell rows. It turned out to be. Therefore, it is thought that if this wasted space is eliminated, chip utilization efficiency will be increased and higher integration will be achieved.

That is, the present invention provides a collection of cell rows in which basic cells each consisting of a plurality of elements are arranged in rows in advance on a semiconductor substrate, and a block region that realizes a desired function by waiting for a shape different from the collection of cell rows. In a master slice type semiconductor integrated circuit that realizes a desired logic function using metal interconnections, for a portion where the cell string length of the collection of cell strings is short, the length of the other cell strings is long. In comparison, the spacing between opposing cell rows is narrower.

〔Effect of the invention〕

According to the present invention, since the spacing between opposing cell rows in the short cell row length portion is narrower than that in the long cell row length portion, the free space in the wiring area is minimized. be able to. For this reason,
It is possible to improve chip utilization and achieve high integration.

[Embodiments of the invention]

FIG. 1 is a schematic diagram showing a schematic configuration of a master slice type semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 11 and 13 are cell columns, 12 and 14 are channels, 15 is a functional block, and 16 is a master chip including these. Here, memory circuits such as ROM and RAM, PLA, etc. are used as the functional blocks. Wiring between cells is 2 layers
Taking Al wiring as an example, wiring is performed such that the direction perpendicular to the channel is the first layer Al, and the longitudinal direction is the second layer Al. In the figure, 17 is the first cell lead-out wiring.
Layer Al, 18 is the second layer Al that connects this. 1st
A first channel 12 adjacent to the cell row 11 in the figure has a channel width equivalent to that provided in a normal master slice type integrated circuit, and is adjacent to a second cell row 13 having a shorter cell row length than the cell row 11. The second channel 14 is formed to have a narrower channel width than the channel 12. The channel width depends on the size of the target master chip and the size of the functional blocks included, but it also depends on the number of cells included in one column, so it is preferable to set it appropriately. However, if you decide the size of the master chip and specify the size (especially the width) of the functional block to be used,
The spacing between each cell column can be determined.

Thus, according to this embodiment, the spacing between opposing cell rows in a portion where the cell string length is long is equal to that of a conventional master slice type integrated circuit, and the spacing between opposing cell rows in a portion where the cell string length is short is By making the spacing narrower than the spacing between the cell rows described above, the vacant space in the wiring area can be reduced. Therefore, the cell can be used more effectively by the narrower area, and there are advantages such as improved chip utilization and higher integration.

Note that the present invention is not limited to the embodiments described above. For example, the number of cells, the number of elements in a cell row, etc. may be determined as appropriate according to specifications. Further, the width of the channel between cell rows may be determined based on the number of elements in the cell row adjacent to the channel. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a schematic configuration of a master slice type semiconductor integrated circuit according to an embodiment of the present invention. 11, 13... cell row, 12, 14... channel,
15...Function block, 16...Master chip, 1
7...First layer Al wiring, 18...Second layer Al wiring.

Claims (1)

[Claims] 1. On a semiconductor substrate, a collection of cell rows in which basic cells each consisting of a plurality of elements are arranged in rows, and a block region having a shape different from the collection of cell rows and realizing a desired function are configured. Regarding the portion where the cell string length of the collection of cell strings is shortened in a master slice type semiconductor integrated circuit that realizes a desired logic function by metal wiring,
A semiconductor integrated circuit characterized in that the spacing between opposing cell rows is narrower than in other parts where the cell rows are long.