JPH0533564B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an intermediate frequency amplification circuit for a receiver in a mobile radio device or the like, and more particularly to an intermediate frequency amplification circuit having a function of detecting the received electric field strength of the receiver.

Prior Art As prior art to the present invention, for example, Micro-
electronics and reliability, vol.16, PP.345~
366. Pergamon Press, 1977.

Figure 3 shows CA3089 shown in the above document.
It is a block diagram of a conventional intermediate frequency amplification circuit, which is a part of an IC extracted, and is equipped with a reception field strength detection function. This intermediate frequency amplification circuit includes three stages of cascaded amplifiers. The first stage amplifier consists of transistors Q1' to Q10', the second stage amplifier consists of transistors Q11' to Q19',
The third stage amplifier consists of transistors Q20'-Q27'. The strength of the input IF signal, that is, the received electric field strength, is determined by connecting the output of each stage to capacitor C.
8, C9, and C10, the rectified electric fields of each stage are added together, detected, and outputted from terminal 5.

Problems to be Solved by the Invention However, in this conventional circuit, the rectified voltage of each stage is connected to the transistors Q39', Q40', Q41',
Although Q42' is added, the linearity of this added portion deteriorates, and as shown in FIG. 4, it is often seen that unevenness appears in the electric field detection voltage.

In addition, signal rectification is performed using diodes Q28' and Q2.
9', Q30';Q32',Q33',Q34'; Q
35', Q36', and Q37', the disadvantage is that the temperature characteristics are particularly poor and the circuit becomes complicated to compensate for the temperature characteristics.

In addition, each rectifier has three capacitors C.
8, C9, and C10 are required. The required capacitance of these capacitors increases as the intermediate frequency is lowered. Therefore, these capacitors C8, C
9.C10 is converted into an IC because the intermediate frequency is
Generally, the frequency is 10.7MHz or higher. Lowering the intermediate frequency made it difficult to incorporate a capacitor into an IC, and each stage required a terminal for an external capacitor, making it disadvantageous to use an IC. Also, the intermediate frequency
If the frequency is set higher than 10.7MHz, the current consumption will increase because the amplification cannot be achieved unless current is passed through each stage of the amplifier.

Furthermore, in order to improve the linearity of the electric field detection voltage, it is generally necessary to lower the gain of each stage of the amplifier constituting the intermediate frequency amplifier, increase the number of amplifier stages, and increase the number of rectifier stages accordingly. In order to expand the dynamic range of the input electric field to be detected, it is necessary to increase the number of amplifier stages and the number of rectifier stages constituting the intermediate frequency amplifier. In particular, when the rectifier is composed of diodes and capacitors, since it is a passive element, the dynamic range of electric field detection can only be achieved up to the sum of the gains of the amplifiers in each stage that constitute the intermediate frequency amplifier circuit. For a large input signal level, the maximum input signal level is determined by the saturation level of the first stage amplifier, so expanding the dynamic range of the detectable input electric field is necessary when converting a conventional circuit into an IC. was particularly disadvantageous.

The present invention has been made in order to eliminate the above-mentioned disadvantages inherent in the conventional technology, and an object of the present invention is to provide excellent linearity and temperature characteristics of the electric field detection voltage, and in particular to improve the dynamic range of the detection electric field. over a wide range that exceeds the total gain of the intermediate frequency amplifier circuit,
Furthermore, it is an object of the present invention to provide a novel intermediate frequency amplifier circuit that requires fewer external components and can be realized with a small chip area when integrated into an IC, which has an input electric field detection function that can detect up to high input signal levels. It is in.

Means for Solving the Problems In order to achieve the above object, an intermediate frequency amplifier circuit with a field strength detection function according to the present invention provides differential Amplifiers are sequentially connected in cascade, a double balanced differential amplifier is connected to each of the first to nth stage differential amplifiers, and the first double balanced differential amplifier is connected to the first to nth differential amplifiers. (2m+1) (m is an integer) differential amplifiers connected in parallel, with the output signal of the differential amplifier in the first stage as the first input, and the input signal of the differential amplifier in the first stage as the second input; The i-th (i is an integer from 2 to (n-1)) double-balanced differential amplifier receives the output signal of the i-th stage differential amplifier as its first input; The input signal of the differential amplifier is received as the second input by two differential amplifiers connected in parallel, and the n-th double-balanced differential amplifier receives the output signal of the n-th stage differential amplifier. 1 input, and the second input is received by four differential amplifiers connected in parallel, two of the four differential amplifiers receive the input signal of the n-th differential amplifier, and the second input is received by four differential amplifiers connected in parallel. The other two differential amplifiers have a circuit that receives the output signal of the n-th stage differential amplifier and adds the positive-phase output currents of the n double-balanced differential amplifiers. In the intermediate frequency amplifier consisting of the first two
The gain ratio of the (2m+1) differential amplifiers connected in parallel constituting the double-balanced differential amplifier is
When the gain of the differential amplifier in the stage is g ₁ , they are respectively 1:√ ₁ :g ₁ :g ₁ ^3/2 :...:g ₁ ^m , and the i-th (i is from 2 to n-1) The gain ratio of two parallel-connected differential amplifiers constituting a double-balanced differential amplifier (an integer of
When the gain of the differential amplifier of the stage (an integer up to The gain ratio is 1:√, where gn is the gain of the n-th stage differential amplifier.

Examples of the invention Next, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes three stages of differential amplifiers A1, A2, A3 connected in series,
Three double balanced differential amplifiers B1, B2, B3
, adder 3, rectifying capacitor Crec, and IF
It consists of signal input terminals 1 and 1' and output terminals 2 and 2' for amplified IF signals.

The first stage differential amplifier A1 includes a constant current source _I10 , transistors Q1 and Q2, transistors Q3 and Q4 for level shifting, and a resistance element R.
It consists of 3, R4.

The same applies to the second and third stage differential amplifiers A2 and A3.

The first double balanced differential amplifier B1 includes transistors Q5 and Q6, transistors Q7 and Q8,
Transistors Q15 and Q16, transistors Q9 and Q10, resistance elements R5 and R6, and constant current source
a first differential amplifier with I ₁ and a transistor Q
11 and Q12, resistance elements R7, R8, and constant current source
a second differential amplifier with I ₂ and a transistor Q
13 and Q14, and a third differential amplifier having a constant current source _I3 .

The second double balanced differential amplifier B2 includes transistors Q21 and Q22, transistors Q23 and Q24, transistors Q29 and Q30, transistors Q25 and Q26, and resistance elements R13 and R4.
and a fourth differential amplifier having a constant current source _I4 , and a fifth differential amplifier having transistors Q27 and Q28 and a constant current source _I5 .

The third double balanced differential amplifier B3 includes transistors Q35 and Q36, transistors Q37 and Q38, transistors Q47 and Q48, transistors Q39 and Q40, and resistance elements R19 and R2.
0 and a constant current source I ₆ , a seventh differential amplifier with transistors Q41 and Q42 and a constant current I ₇ , and transistors Q43 and Q
44, resistance elements R21 and R22, and a constant current source _I8 , and a ninth differential amplifier having transistors Q45 and Q46 and a constant current source _I9 .

IF input signal applied between input terminals 1 and 1'
V _IN is amplified by the first stage differential amplifier A1, the second stage differential amplifier A2, and the third stage differential amplifier A3, and is output as the IF output signal V ₀ between the output terminals 2 and 2'. . As the IF input signal V _IN gradually increases, the differential amplifiers connected to the second inputs of the double-balanced differential amplifiers B1, B2, and B3 sequentially start from the ninth differential amplifier in the subsequent stage. It becomes saturated.

Here, the respective gains of the first-stage differential amplifier A1, the second-stage differential amplifier A2, and the third-stage differential amplifier A3 are assumed to be g ₁ , g ₂ , and g ₃ . Now, the gain ratio of the first to third differential amplifiers constituting the first double balanced differential amplifier B1 is 1:√ ₁ :g ₁ =I ₁ /2V _T +RE1I ₁ :I ₂ /2V _T +RE2I ₂ :I ₃
/2V _T ...(1) However, R5=R6=RE1 R7=R8=RE2 Here, V _T is given by the following formula.

V _T =kT/q...(2) Here, k is Boltzmann's constant, T is absolute temperature,
q is the unit charge of an electron.

The gain ratio of the fourth and fifth differential amplifiers constituting the second double-balanced differential amplifier B2 is 1:√ ₂ = I ₄ /2V _T +RE3I ₄ :I ₅ /2V _T ……(3) However, R13=R14=RE3 The gain ratio of the sixth to ninth differential amplifiers constituting the third double-balanced differential amplifier B3 is 1:√ ₃ :1:√ ₃ =I ₆ /2V _T +RE4I ₆ : I ₇ / 2V _T : I ₈
/2V _T +RE5I ₈ :I ₉ /2V _T ……(4) However, R19=R20=RE4 R21=R22=RE5 Now, for simplicity, g ₁ = g ₂ = g ₃ = g ₀ ……(5) I ₁ = I ₂ = I ₃ = I ₄ = I ₅ = I ₆ = I ₇ = I ₈ = I ₉ = I ₀ ……(6) RE1 = RE2 = RE3 = RE4 = RE5 = RE0 ……(7) IF input signal V _IN and adder 3 in Fig. 1 as
The relationship between the output average current and the output average current is shown in FIG. 2 so that the effect of each differential amplifier constituting each double-balanced differential amplifier can be seen.

However, G ₀ = 20log g ₀ ...(8) As is clear from Figure 2, the dynamometer of the input signal V _IN that can be detected for the total gain of 3G ₀ dB of the first to third stage differential amplifiers The power range is 9/4G ₀ dB, ensuring a wider dynamic range by 3/2G ₀ dB.

Furthermore, since each differential amplifier constituting each double-balanced differential amplifier sequentially saturates each time the IF input signal V _IN increases by 1/2G ₀ dB, the deviation from the log characteristic of the electric field detection voltage is Equivalently, 1/2G ₀ dB
It is possible to obtain characteristics equivalent to an electric field detection function consisting of nine stages of differential amplifiers connected in cascade and nine rectifiers connected to the output of each differential amplifier.

Effects of the Invention As described in detail above, the intermediate frequency amplification circuit of the present invention is constituted by a circuit consisting of a multi-stage differential amplifier and a multi-stage double balanced differential amplifier. This method detects the input electric field level V _IN of the intermediate frequency amplifier circuit by adding the positive phase outputs of the dynamic amplifiers and using the average output current of the adder output. In this intermediate frequency amplification circuit, the phases of the outputs of each double-balanced differential amplifier are matched, so addition can be performed without converting to direct current, and even if the stages are multistage, only one rectifier capacitor is required. Even if the intermediate frequency is low and a capacitor cannot be built in, it is sufficient to have one terminal for an external capacitor, and it can be shared with the output terminal. Therefore, there is no need to substantially increase the number of terminals. Therefore, by connecting only one capacitor externally to the output terminal, the intermediate frequency can be lowered, and the necessary gain can be achieved even if the current value flowing through each stage differential amplifier and each double-balanced differential amplifier is reduced. This makes it possible to reduce current consumption.

Furthermore, as described in detail above, the log characteristic of electric field detection is excellent, and the dynamic range of the detected electric field can be made several steps wider than the total gain of the intermediate frequency amplifier composed of cascade-connected differential amplifiers.

As for the circuit configuration, since it is configured with a differential pair, the temperature characteristics of electric field detection are also monotonous, so temperature compensation can be easily performed, which has many advantages.

In summary, according to the present invention, an intermediate device having an input electric field detection function has a wide dynamic range, has excellent electric field detection linearity and temperature characteristics, requires a small number of external parts when integrated into an IC, and has an input electric field detection function. A frequency amplification circuit can be easily provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
FIG. 2 is a characteristic diagram of this embodiment, FIG. 3 is a circuit diagram of a conventional intermediate frequency amplification circuit, and FIG. 4 is a characteristic diagram of this conventional circuit. 1, 1'...Intermediate frequency signal input terminal, 2, 2'...
...Intermediate frequency signal output terminal, 3...Adder, A1,
A2, A3...Differential amplifier, B1, B2, B3...
...double balanced differential amplifier, I ₁ , ..., I ₁₂ ... constant current source.

Claims (1)

[Claims] 1 Differential amplifiers from the first stage to the nth stage (n is an integer of 2 or more) are sequentially connected in cascade, and each of the first stage to the nth stage has a double-balanced differential amplifier. a first double-balanced differential amplifier is connected to the first double-balanced differential amplifier, which receives the output signal of the first-stage differential amplifier as a first input, and receives the input signal of the first-stage differential amplifier as a second input. input and connected in parallel (2m
+1) (m is an integer) differential amplifiers,
(where i is an integer from 2 to (n-1)), the double-balanced differential amplifier uses the output signal of the i-th stage differential amplifier as a first input, and the input signal of the i-th stage differential amplifier. The signal is received as a second input by two differential amplifiers connected in parallel, and the n-th double-balanced differential amplifier receives the output signal of the n-th stage differential amplifier as a first input; The second input is received by four differential amplifiers connected in parallel, and two of the four differential amplifiers receive the input signal of the n-th stage differential amplifier;
The other two differential amplifiers have a circuit that receives the output signal of the n-th stage differential amplifier and adds the positive-phase output currents of the n double-balanced differential amplifiers. In an intermediate frequency amplifier consisting of
The gain ratio of the (2m+1) parallel-connected differential amplifiers constituting the first double-balanced differential amplifier is, respectively, when the gain of the first stage differential amplifier is _g1 . 1:√ ₁ :g ₁ :g ₁ ^3/2 :...g ₁ ^m , and the i-th (i is an integer from 2 to n-1)
The gain ratio of the two parallel-connected differential amplifiers constituting the double-balanced differential amplifier is the gain of the i-th (i is an integer from 2 to n-1) stage differential amplifier gi. Then, 1:√, and the nth 2
The gain ratio of the other two parallel-connected differential amplifiers constituting the double-balanced differential amplifier is 1:√, where gn is the gain of the n-th stage differential amplifier. Intermediate frequency amplifier circuit with electric field strength detection function.