JPH0533749B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed detection circuit using a multipolar resolver mounted on a rotating shaft.

[Conventional technology and problems]

In machine tool spindle drive devices, the spindle position is detected by a pulse generator and arbitrary positioning control using a digital method is required for tool changes and the like.

To achieve this, stable slow speed operation is required just before stopping.

For example, for a main shaft motor rated speed of 6000 rpm,
It is necessary to be able to operate stably at 2 rpm.
If the speed detection voltage V ₀ at 6000 rpm is 10V,
At 2 rpm, 10 x 2/6000 = 3.33 mV.

Therefore, in order to maintain rotation with respect to the 2 rpm command, the temperature drift of the speed detection circuit must be suppressed to a sufficiently small value of 3.33 mV.

FIG. 3 is a block diagram of a conventional speed detection circuit.

1 is a crystal oscillator that generates a frequency of 4.608MHz, 2 is a digital monostable circuit, and 3 and 4 are
Switch by FET, 5 is low pass filter,
6 divides the input from crystal oscillator 1 to 1/256.
A frequency divider that outputs 18KHz, 7 is a two-phase sine wave generation circuit, 8 is a resolver (α, β are excitation windings, θ is a detection winding), 9 is a voltage comparator that converts the resolver detection signal into pulses, 10 is a frequency divider that divides the detection signal from the resolver 8 into 1/8.

In FIG. 3, the output of the two-phase sine wave generating circuit 7 is a 18 KHz sine wave signal, which excites the α and β phase excitation windings of the resolver 8. The detection winding θ of the resolver 8 generates a frequency f ₀ in the following (formula 1).

f ₀ =18+PN/120×1/1000 (KHz) (1 formula) where P is the number of poles of the resolver 8 (72P), and N is the number of rotations (rpm) of the resolver 8.

This detection signal B of frequency f ₀ is passed through the frequency divider 10 to
The frequency is divided by 1/8 to become a signal D, which is input to the digital monostable circuit 2.

This digital monostable circuit 2 counts 1024 4.608 MHz pulses after receiving the signal D. During this counting period, a high level signal is generated at the output Q, and a low level signal is generated at the inverted signal of the signal Q, and after the counting is completed, the level of the signal Q is inverted. The switches by FETs 3 and 4 are turned ON when the gate G is high level, and turned OFF when the gate G is low level.

Therefore, when the signal Q is at a high level, V _P is applied to the input of the low-pass filter 5, and when the signal Q is at a low level, V _N (-8V) is applied.

The input waveform of the low-pass filter 5 is as shown in FIG.

The high level time T _H is 1024/4608 (ms),
The low level time T _L is 8/f _{0 −TH} .

Therefore, the output voltage V ₀ of the low-pass filter 5 is
Since the voltage is the average voltage shown in FIG. 4, it is expressed as (Equation 2).

V ₀ = V _P × T _H + V _N × (8/f ₀ − T _H )/8/f ₀ = f ₀ × T _H /8 (V _P − V _N ) + V _N ……(Equation 2) Therefore, V ₀ = 1/36 (18±PN/120000) (V _P −V _N ) + V _N = 1/2 (V _P +V _N ) ±N/60000 (V _P −V _N ) ...(Equation 3) .

As the output of the low-pass filter 5, a voltage proportional to the speed N can be obtained, but as shown in equation (3), V _P , V _N
If V 0 changes with temperature and time, the output voltage V ₀ of the low-pass filter 5 also changes.

For example, if N=2 rpm in equation (3), the second term on the right side is 0.53 mV, so if the first term on the right side of equation (3) is 0.53 mV, operation is not possible.

From the above, it can be seen that it is difficult to support arbitrary positioning control using the conventional method.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a detection circuit using a resolver that overcomes the drawbacks of conventional devices and can perform high-precision speed control even at low speeds.

[Summary of the invention]

In order to achieve the above object, the present invention applies the principle of beat generation using two different frequencies to a speed detection circuit using a multipolar resolver.
This is a means of increasing detection sensitivity over a wide range.

〔Example〕

FIG. 1 shows a block diagram showing the circuit configuration in one embodiment of the present invention.

In FIG. 1, the same symbols as in FIG. 3 are the same or equivalent parts, 11 is a frequency dividing circuit for generating frequency divided signal A, and 12 is an exclusive OR circuit that receives signal A and signal B as input. , 13 is a low-pass filter, 14 is a voltage comparator, and 15 is a switch.

If the rated rotation speed of the resolver is 6000 rpm, the resolver detection signal θ〓 is 21, 6 KHz at 6000 rpm,
When reverse rotation is 6000 rpm, it becomes 14.4KHz. In other words, if the excitation frequency f _c and the rated modulation frequency f _r are θ〓=f _c ±
f _r /6000 rpm, and the output of the frequency divider 10 is D=
1/8fc±1/8fr/6000rpm. Therefore, the speed detection signal V ₀ is obtained with a frequency change of 1/8 _fr .

Next, a high-accuracy speed detection circuit at low speeds according to the present invention will be explained.

The frequency divider 11 inputs the signal from the crystal oscillator 1 and outputs a signal A having a frequency of 7/8 f _{c which is obtained by dividing the resolver excitation frequency f c} by _7/8 .

A signal B obtained by pulsing the signal A and the resolver detection signal θ〓 by the voltage comparator 9 is input to the exclusive OR circuit 12. As a result, the sum component and difference component of signal A and signal B are output. In other words, the low frequency component (1-7/8) f _c ±f _r and the high frequency component (1+7/8) f _c ±
It is _fr .

By passing this signal through a low-pass filter 13, high frequency components are cut off, so only low frequency components are extracted. Furthermore, the voltage comparator 14
The output signal D is made into a pulse and has the same level as the output signal D of the frequency divider 10. Furthermore, in order to make the modulation frequency the same as that of signal D, the number of rotations used for signal C is limited to ±750 rpm.

From the above, as shown in Figure 2, if signal D is used during normal operation and signal C is used during orientation, the speed detection voltage V ₀ = 10V/6000rpm and the speed detection voltage V ₀ = 10V/750rpm. Therefore, a wide range of speed detection signals and a low speed and high precision speed detection signal can be obtained using the same F/V (frequency→voltage) conversion circuit.

Furthermore, in the low speed range, the modulation frequency increases eight times, so that factors such as signal transmission time, reference voltage fluctuations, and drift are relatively compressed to 1/8.

As described above, in this embodiment, n=8 with the signal A divided into n-1/n, but n can be an integer of 1 or more depending on the purpose and application.

〔Effect of the invention〕

As described above, the present invention provides the following effects.

By increasing the level of the speed detection signal by n times, the adverse effects of drift are reduced.

By increasing the detection gain of the speed detection signal by n times, the speed loop gain can be increased.

As a result, position control over a wide range and with high precision becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a detection signal characteristic diagram of the circuit,
Figure 3 is a block diagram of a conventional speed detection circuit.
FIG. 4 is an input voltage waveform diagram of the low-pass filter. 1...Crystal oscillator, 2...Digital monostable circuit, 3, 4...Switch using FET, 5, 1
3... Low pass filter, 6, 10, 11... Frequency divider, 7... Two-phase sine wave generation circuit, 8... Multipolar resolver, 9, 14... Voltage comparator, 12... Exclusive OR Circuit, 15...Signal C, D changeover switch.

Claims (1)

[Claims] 1. Means for creating an exclusive OR signal AB using a signal A obtained by dividing the resolver excitation frequency into n-1/n and a resolver detection signal B; Through the low frequency device,
Means for extracting a speed detection signal C of a low frequency component; Means for switching and deriving the speed detection signal C and a signal D obtained by 1/n of the signal B; Speed detection circuit.