JPH0534844B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention uses elements with low junction breakdown voltages and transistors with relatively low breakdown voltages between source and drain or collector and emitter, and handles analog inputs higher than these breakdown voltages. electronic volume,
The present invention relates to a signal processing circuit suitable for a D/A converter circuit that handles high voltage.

Structure of a conventional example and its problems FIG. 1 shows a conventional example of an electronic volume. The analog signal input to input terminal 1 is output to output terminal 2.
While reaching , resistance R ₁₁ (resistance value r), R ₁₂ (resistance value 2r), R ₂₁
(same r), R ₂₂ (same 2r)... An r-2r resistor network consisting of transistors Q ₁₁ , Q ₁₂ , Q ₂₁ , Q ₂₂ ... and a control signal input for controlling them. It is given a predetermined attenuation by terminals 3 and 4 and inverters 5 and 6, and is output to output terminal 2 via operational amplifier 7. That is, the transistors _Q11 and _Q12 , which are configured to operate in opposite phases to each other, receive a control signal input from the control signal input terminal 3 that controls the amount of attenuation, and a signal inverted by the inverter 5. is applied. However, due to the propagation delay of the inverter 5, the gate voltage of the transistor _Q11 and the gate voltage of the transistor _Q12 do not have completely opposite phases, and a delay occurs in the gate voltage of the transistor _Q12 . Therefore, the transistor
When the gate of _Q11 changes from H level to L level, the gate of transistor _Q11 and _Q12 change from L level to H level.
Both gates of Q ₁₂ have an off time, and during this period, the same voltage as the input to input terminal 1 is applied between the sources and drains of transistors Q ₁₁ and Q ₁₂ . If the source-drain breakdown voltage of the transistors Q ₁₁ or Q ₁₂ is lower than this input terminal, breakdown occurs and abnormal operation occurs. Therefore, it was necessary for transistors _Q11 and _Q12 to be constructed of transistors having a withstand voltage higher than the input voltage. Also, transistors Q ₂₁ , Q ₂₂
The same thing exists for .

Generally, in circuit configurations such as electronic volumes, the maximum input voltage is often considered to be around 40V. Therefore, the breakdown voltage of the transistor is required to be higher than that value, and the element size becomes large, which is a disadvantage that is contrary to the improvement in the degree of integration.

Purpose of the Invention An object of the present invention is to provide a signal processing circuit suitable for electronic volume and D/A converter circuits, which can be constructed with transistors having a withstand voltage lower than the input voltage, and which does not cause the above-mentioned abnormal operation. .

Composition of the Invention The present invention is used in an electronic volume, etc., and in a signal processing circuit having a resistor network and a changeover switch, when a pair of transistors of the same polarity acting as a changeover switch is switched and controlled, both of the transistor pair are brought into a conductive state. A control circuit is provided on the control electrode side of the transistor pair.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a portion of an integrated electronic volume circuit according to one embodiment of the present invention. The operation will be explained in detail below.

In the figure, 1 is an analog signal input terminal, 2 is an output terminal that outputs an analog signal given a predetermined attenuation, 3 is a control signal input terminal that controls the attenuation of the largest digit, and 4 is the control signal input terminal that controls the attenuation of the next digit. Control signal input terminals 5 and 6 correspond to a first control circuit, an inverter 7 is an operational amplifier, and 8 is a virtual ground line that outputs a current connected to the operational amplifier 7 from the resistor network. 9, 10, 11, and 12 are all two-input NAND gates corresponding to the second control circuit.
R ₁₁ , R ₁₂ , R ₂₁ , R ₂₂ ... constitute a well-known r-2r resistance network, and R ₁₁ , R ₂₁ ... have a resistance value r,
Resistors R ₁₂ , R ₂₂ . . . each have a resistance value of 2r. Rf is the feedback resistance. _Q11 ,
Q ₁₂ , Q ₂₁ , Q ₂₂ ... are all n-channel MOS
It is a transistor (hereinafter referred to as a transistor).

NAND gates 9 and 10 form a latch circuit, and in a static state, the output of either one is high.
level, and the other is at L level. Therefore, one of transistors Q ₁₁ and Q ₁₂ is on and the other is off. transistor Q ₂₁
The same applies to _Q22 . transistor Q ₁₁
The sources of and _Q12 are connected to ground or virtual ground. That is, it becomes a ground potential.

In this embodiment, one of transistors Q ₁₁ and Q ₁₂ is in the on state, so the transistor
If the on-resistance of Q ₁₁ and Q ₁₂ is sufficiently smaller than 2r, then
The value of the voltage generated at the common drain of transistors Q ₁₁ and Q ₁₂ is sufficiently small compared to the magnitude of the analog signal applied to the input terminal 1.

Next, consider the case where transistors Q ₁₁ and Q ₁₂ are switched. Initially, when the control signal input terminal 3 is at L level, the output of NAND gate 9 is at H level,
The output of the NAND gate 10 becomes L level. Therefore, transistor Q ₁₁ is on and Q ₁₂ is off. The state at the moment when the control signal input terminal 3 changes from this state to the H level is as follows.
That is, one of the inputs of the NAND gate 9 is connected to the control signal input terminal 3 and shifts to the H level, while the other input is connected to the output of the NAND gate 10, that is, the L level.
level, so the output of transistor _Q11 does not change immediately. On the other hand, the output of the inverter 5 changes from H level to L level, one of the two inputs of NAND gate 10 becomes L level, and the output becomes H level. When the output of the NAND gate 10 becomes H level, the transistor _Q12 is turned on, and at this moment both transistors _Q11 and _Q12 are both turned on. After this transient state, the output of the NAND gate 10 becomes H level, so
The two inputs of the NAND gate 9 both go to H level, and the output goes to L level, so that the transistor
Q ₁₁ is turned off. That is, during the transition period corresponding to the propagation delay of NAND gate 9, transistor Q ₁₁ and
Q ₁₂ are both turned on and then the transistor
Q ₁₁ is turned off.

Also, when the control signal input terminal 3 changes from H level to L level, the output of NAND gate 9 immediately changes from L level to H level, and only after that change in output does the output of NAND gate 10 change from H level to L level. change to the level.

As described above, in the case of this embodiment, one or both of the six transistors Q ₁₁ and Q ₁₂ is on in any case, and there is no period in which both transistors are off. Therefore, the common drains of these transistors are always at a potential close to ground, and the transistors forming the electronic switch are not required to have a high breakdown voltage as in the prior art. The same applies to the inverter 6, NAND gates 11 and 12, and transistors Q ₂₁ and Q ₂₂ controlled by the control signal input terminal 4.

The virtual ground line 8 is a virtual ground and a transistor.
The input signal flows as a current to the feedback resistor Rf through the transistors Q ₁₂ , Q ₂₂ . . . which are turned on, and is taken out to the output terminal 2 as an analog voltage output. From the above explanation, it is clear that the transistors Q ₁₁ , Q ₁₂ , Q ₂₁ , Q ₂₂ .

Furthermore, by forming the ladder resistors such as resistors R ₁₁ , R ₁₂ , R ₂₁ , R ₂₂ . . . with a resistor film such as polysilicon formed on an insulating film, it can be used even at an input voltage higher than the withstand voltage of the junction. can. Further, polysilicon may be a material commonly used as a gate material in a MOS integrated circuit having a silicon gate structure, and there is no need to add any new process.

In the configuration of this embodiment, since the voltage at the output terminal 2 is opposite to that of the input terminal 1, it is preferable that the output terminal 2 is not integrated on the same chip, but is configured as a separate chip.

Furthermore, in this embodiment, transistors Q ₁₁ , Q ₁₂ ,
Q ₂₁ , Q ₂₂ ... are constructed using MOS transistors, but they can of course also be constructed using bipolar transistors, in which case the drain, gate, and source correspond to the collector, base, and emitter, respectively. .

Furthermore, although this embodiment has been described with respect to an electronic volume, it goes without saying that the present invention is not limited to electronic volumes and can be implemented in a wide variety of applications such as D/A converters and pattern generators.

The present invention is particularly effective in the changeover switch portions of the top girder and girders in its vicinity. This is because when the present invention is implemented in these digits, for example in an r-2r resistor network, the input is attenuated by half for each digit, so the required withstand voltage is also sequentially reduced by 2.
It relies on a factor of 1.

Effects of the Invention As explained above using the embodiments, according to the present invention, an element having a relatively low junction breakdown voltage, such as a source-drain breakdown voltage of an FET, or a relatively low collector-emitter breakdown voltage of a bipolar transistor, is used. It is possible to construct signal processing circuits such as electronic volumes and D/A converters with input voltages higher than these withstand voltages, and it is extremely effective for miniaturizing elements, that is, improving the degree of integration, and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a signal processing circuit diagram according to a conventional example, and FIG. 2 is a signal processing circuit diagram according to an embodiment of the present invention. 1...Input terminal, 2...Output terminal, 3, 4...
Control signal input terminal, 5, 6... Inverter, 7...
...Operation amplifier, 8...Virtual ground line, 9, 10, 1
1, 12...NAND gate, Q ₁₁ , Q ₁₂ , Q ₂₁ ,
Q ₂₂ ...transistor.

Claims (1)

[Claims] 1. A resistor network connected to a signal input terminal and provided with a plurality of branch points, and a transistor pair of the same polarity connected to at least one of the branch points,
means for maintaining the potentials of the respective output electrodes of the transistor pair at substantially the same potential; a control signal input terminal for inputting a signal to each control electrode of the transistor pair; and the control signal input terminal and the transistor. a first control circuit that is provided between the pair of transistors and applies control signals having mutually opposite phases to the control electrodes of each of the transistor pairs, and when the first control circuit switches the control signal, A signal processing circuit characterized in that a second control circuit that brings both of the transistor pair into a conductive state is provided between the first control circuit and the transistor pair.