JPH0535599B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A wiring pattern formed on a semiconductor device that connects a plurality of output pins that output a predetermined signal level to a plurality of corresponding input pins is opened in a predetermined combination, and those input The pin is read out by a scan circuit system and used to determine the semiconductor device number.

[Industrial application field]

The present invention relates to an LSI semiconductor device number reading circuit, and in particular, the present invention relates to an LSI semiconductor device number reading circuit, and in particular, it reads an individual number using an external electrical signal, such as an implementation board on which an LSI used in an information processing device or the like or a shelf on which multiple mounting boards are mounted. The present invention relates to an LSI semiconductor device number readout circuit that can be read out using an LSI semiconductor device number.

[Prior Art] In recent years, LSIs used in information processing devices have become highly integrated, and the substrates on which these LSIs are mounted have also become highly dense. For this reason, the functions integrated on boards on which LSIs are mounted are becoming more sophisticated year by year, and even the CPU of a computer is now being housed on a single board. As the functionality of a single mounted board or mounted body increases in this way,
It is required to be able to electrically read and identify the individual number of each mounted board, such as the serial number at the time of manufacture, from outside the board. That is, the ability to read the individual number has the following advantages.

(1) Manufacturing information and test information for individual mounted boards can be automatically collected and stored at factories.

(2) If a failure occurs at a customer's site, test information and manufacturing information for the relevant equipment can be communicated to the customer's site, contributing to failure recovery at the customer's site.

(3) To prevent software such as microprograms provided for a fee to individual users from being used without permission, they can be used as individual keywords for individual computer systems.

[Problem that the invention seeks to solve]

However, it is difficult to form a circuit inside an LSI for providing an individual number to a semiconductor device, and there has been a demand for a device that can read out a device-specific number from the outside with a simple configuration.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to be able to read out a device-specific number from inside the device with a simple configuration.
An object of the present invention is to provide an LSI semiconductor device number reading circuit.

[Means for solving problems]

In order to achieve the above object, as shown in FIG. 1, the present invention provides a _wiring pattern in which a plurality of output pins O ₁ .
The plurality of input pins I 1 are connected to the semiconductor device 1 connected to the plurality of input pins I ₁ ...I _o via W _{1 ...} W _o .
...an LSI semiconductor formed by forming a scan-out circuit system 2 capable of scanning out all or part of the signal level of _Io , and providing an open circuit to give a predetermined signal level combination to the wiring pattern to the input pin to be scanned. This is a device number readout circuit.

[Effect]

An open circuit is created in the wiring pattern connecting predetermined input/output terminals among the input/output terminals of the LSI, and the signal levels appearing at these input terminals are scanned out by a scan circuit system to determine the device-specific number. I made it possible for you to do it.

〔Example〕

FIG. 2 shows the configuration of a preferred embodiment of the present invention using an ECL circuit as an example. In the figure,
The board 10 is equipped with an LSI 12, a decoder 14, and the like. Output terminals of LSI12 O ₁ , O ₂ , O ₃ ,
...O _o are connected to input terminals I ₁ , I ₂ , I ₃ , . . . I _o via wiring patterns 16, respectively. Furthermore, terminating resistors R ₁ -Rn are connected to the input terminals I ₁ -In. The other end of this terminating resistor R ₁ to _{R o} is the terminating voltage V _T
(e.g. -2.0V). Each input terminal
_I1 to _Io are NOR gates _18-1 , _18-2 , _18-3
. . . is connected to the NOR gate 20 via 18- _o . The output of NOR gate 20 is connected to scanout terminal 22.

On the other hand, the output terminals O ₁ to O _o are connected to NOR gates _24-1 , _24-2 , _24-3, . . . 24- _o , respectively. The inputs of these NOR gates are equivalent depending on whether the base terminal of the input transistor is shorted to the emitter terminal as shown in Figure 3a, or to the V _EE power supply as shown in Figure 3b. As a result, the outputs of these NOR gates generate "1". Also, NOR gates 18-1 to ₁₈
− The output of _the address decoder 26 is connected to the other input of the address decoder 26.
A j-bit address line is connected to.

In the above configuration, each input/output terminal is connected via the wiring pattern 16, so normally
A signal of "1" is input to the NOR gates 18-1 to ₁₈ - _o . Therefore, when the wiring pattern 16 between predetermined input and output terminals is cut, the NOR gate corresponding to the cut terminal is
A “0” level signal equal to approximately −2.0V is input. Therefore, in order to identify the unique number of the board 10, if the wiring pattern 16 is cut between predetermined input/output terminals among the input/output terminals of the LSI 12, ²ⁿ individual numbers can be obtained depending on whether the wiring pattern 16 is connected or not. can be attached. This n-bit "0"/"1" information is sent to the scan out terminal 22.
It can be read out via . That is, the input signals of 1 to n bits are sent to the NOR gates _18-1 to 18- together with the scan address signal of j bits decoded by the address decoder 26.
n is input. (In this case, 2 ^j ≧n.)
Furthermore, the NOR gates _18-1 to 18-n function as OR gates due to the nyaed dots.
These outputs are decoded by the decoder 14 as a scan address signal consisting of i bits, and are sent to the NOR gate 20 along with the chip select signal.
The signal is outputted to the scan-out terminal 22 via. The signal of this scan-out terminal 22 is connected to the scan-out signal of another LSI and the outside of the mounting board or the mounting body via a wired dot OR gate. Therefore, by selecting the LSI 12 using the i-bit scan address from outside the mounting board or the mounting body, and selecting any one of bits 1 to bit n using the j-bit scan address, the selection can be made. The information on the bits can be read out to the outside of the mounting board or the mounting body using a scan-out circuit system. By sequentially switching the j-bit scan address from bit 1 to bit n and reading out each bit one by one, information on all bits can be read out. In other words, it is possible to read out the individual number of each LSI determined by the n specific bit configurations.

In the above embodiment, a short circuit is incorporated in the middle of the wiring pattern 16 connecting each input/output terminal, and depending on whether or not this short circuit is short-circuited, the wiring pattern 16 can be cut. It's okay.

〔Effect of the invention〕

As described above, according to the present invention, an excellent effect can be obtained in that an LSI-specific number can be read out from the LSI with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram of a NOR gate that generates a "1" output. In the figure, 10 is a board, 12 is an LSI, 14 is a decoder, 16 is a wiring pattern, and _24-1 to 24
- _o , 18- ₁ ~ 18- _o , 20 is a NOR gate, 2
6 is an address decoder.

Claims (1)

[Claims] 1. Wiring pattern _{W 1} ...W o to which a plurality of output pins O ₁ ...O _o correspond to which a predetermined signal level is applied
A scan-out circuit system capable of scanning out all or part of the signal level of the plurality of input pins I ₁ ...I _o to the semiconductor device 1 connected to the plurality of input pins I ₁ ...I _o via the semiconductor device 1. 2, and an open circuit is provided to give a predetermined combination of signal levels to a wiring pattern to the input pin to be scanned.