JPH0535602B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to television receivers, radio receivers, FM tuners, etc., which use a microcomputer to detect DC rise when the power is turned on.
This invention relates to a mute pulse generation circuit that generates mute pulses for muting noise.

Configuration of conventional example and its problems In a conventional mute device using a microcomputer, as shown in Figure 1, in contrast to the rise of the power supply voltage when the power is turned on, the rise of the voltage at the reset terminal of the microcomputer is connected to the microcomputer. Due to the external reset resistor and capacitor, the rising waveform will be similar to that of the external reset resistor and capacitor, and the internal reset of the microcomputer will be performed at time _t1 .

Therefore, after the power is turned on, the microcomputer does not start operating until the rising edge of the reset signal inside the microcomputer becomes "H", so the mute pulse output from the microcomputer is in an undefined state. Therefore, there is a problem in that the mute pulse of the microcomputer cannot mute unnecessary signals generated from the time the power is turned on until the microcomputer is reset.

OBJECT OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, resets the microcomputer from power-on, and mutes unnecessary signals generated during power-on until the time during which the microcomputer operates normally. The object of the present invention is to provide a mute pulse generation circuit that generates mute pulses that can generate mute pulses.

Structure of the Invention A mute pulse generation circuit according to the present invention connects the emitter of an NPN transistor to a port of a microcomputer that generates a mute pulse,
A pull-up resistor is connected between the collector of the NPN transistor and the power supply, and a parallel circuit of a first resistor and a capacitor is connected between the base of the NPN transistor and the ground,
Furthermore, a parallel circuit consisting of a second resistor and a diode is connected between the base of the NPN transistor and the power supply, the anode of the diode is connected to the base side, the cathode is connected to the power supply side, and the collector of the NPN transistor is connected to the power supply. This allows a mute pulse to be generated from when the power is turned on until the microcomputer is reset, making it possible to mute unnecessary signals when the power is turned on.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram of a mute pulse generation circuit in one embodiment of the present invention.

In Fig. 2, the timing at which the mute output port 2 of the microcomputer 1 starts to operate normally is determined by the external reset resistor 3 and capacitor 4 as shown in Fig. 3. Since it operates like the rising waveform of the internal reset of
The port 2 of the microcomputer 1 is in an undefined state until the point where the microcomputer 1 starts operating.

Therefore, this mute pulse generation circuit is connected to the collector (or drain) of the mute pulse generation transistor 5 of the port in the microcomputer 1.
The emitter of NPN transistor 6 is connected, and the collector of transistor 6 has a pull-up resistor 7.
is connected to the power supply line 8.

The circuit consisting of resistors 9 and 10 and capacitor 11 is used to delay the turning on of transistor 6 when the power is turned on, and the potential of its base is the same as that of the delay circuit of 9, 10, 11 in Figure 3. It has a voltage rise characteristic similar to ``rise characteristic''. Then,
When the power is turned on, the mute pulse is output to the line 12 as shown in FIG. Therefore, the mute pulse is controlled by the mute pulse generation transistor 5 of the microcomputer 1. Therefore, if the mute circuit 13 is controlled by this mute pulse,
Unnecessary signals at power-up can be muted.

Note that the diode 14 is for immediately discharging the charge in the capacitor 11 when the power is turned on.

Effects of the Invention As described above, according to the present invention, even if the output mute terminal of the microcomputer is in an undefined state when the power is turned on, unnecessary signals can be muted when the power is turned on, and the microcomputer is reset and becomes normal. After it starts operating, it can be operated by the mute output of the microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram of the operation of a microcomputer when the power is turned on in a conventional example, FIG. 2 is a block diagram of a mute pulse generation circuit in an embodiment of the present invention, and FIG. 3 is a timing diagram for explaining the operation of FIG. 2. It is a diagram. 1...Microcomputer, 2...Output port, 5...Mute pulse generation transistor, 6
...NPN transistor, 7...Pull-up resistor,
8...Power line, 9, 10...Resistor, 11...
Capacitor, 12... Output line, 13... Mute circuit, 14... Diode.

Claims (1)

[Claims] 1 Connect the emitter of the NPN transistor to the port that generates the mute pulse of the microcomputer, connect a pull-up resistor between the collector of the NPN transistor and the power supply, and
A parallel circuit of a first resistor and a capacitor is connected between the base of the NPN transistor and the ground, and a parallel circuit of a second resistor and a diode is connected between the base of the NPN transistor and the power supply. A mute pulse generation circuit characterized in that a diode is connected with an anode connected to the base side and a cathode connected to the power supply side, so that a mute pulse is obtained from the collector of the transistor.