JPH0535896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission control processor, and more particularly to a transmission control processor that executes a transmission control procedure.

[Conventional technology]

Traditionally, transmission control procedures are performed using a general-purpose CPU, e.g.
This was achieved through a software program using the 8086, 68000, etc. However, implementation using software has a limit in processing speed, making it difficult to meet the demands for high-speed transmission. Furthermore, the number of man-hours required for software development is extremely large.

In contrast, dedicated LSIs that execute transmission control procedures have recently appeared, making it possible to shorten the development period and realize high-speed transmission.

However, currently the CCITT standard X.25
Only the lower layers up to level 2 have been realized, and although it is desired to realize the upper layers, it is said to be difficult because there are so many parameters.
Also, in the lower layers, the only thing that has been implemented as a dedicated LSI is the X.25 frame layer standardized by CCITT, and dedicated LSIs for other transmission procedures have not yet been developed.

[Problem that the invention seeks to solve]

Examining the structure of the transmission control procedure, it has a structure in which predetermined processing is performed in response to an event and the current state, and at the same time a transition is made to a new state.

When using a general-purpose processor, the if code is used to identify which event has occurred and which state it is in, but the problem is that when the number of events and states is large, the time required for identification becomes extremely long. be. Furthermore, if there is a bug in this part, there is a problem in that strange results are sometimes produced and it takes a lot of man-hours to find out where the bug is.

An object of the present invention is to provide a transmission control processor that can instantly identify which event has occurred in which state.

[Means for solving problems]

The transmission control processor of the present invention includes an event register for setting only first event information;
an associative memory that stores a plurality of second event information and event codes in pairs and outputs the event code corresponding to the second event information that matches the first event information; A state register in which only the first state code is set, and a second state code of the state to which the pointer to the processing routine should transition next is set as contents, and the output of the associative memory and the first state code are used as addresses. It has a memory circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, only first event information is set in the event register 100, specifically, packet headers and timer events are written.

The associative memory 101 stores a plurality of possible second event information and event codes in pairs, and uses the first event information of the event register 100 as search data to search for the second event information stored in the associative memory 101. A match search for all words corresponding to the event information is performed simultaneously for all words, and an event code corresponding to the retrieved second event information is output.

By doing this, for example, even if the first event information is composed of information consisting of a large number of bits such as a non-continuous discontinuity, the information obtained as the output can be used as one of the addresses of the RAM 102. The event code to be displayed can be an event code with a reduced bit structure compared to the first event information itself.
The bit capacity of the associative memory used is ``(number of bits of event information + number of bits of event code) x
Event codes can be obtained instantly with a small memory capacity corresponding to the number of event information. This event code can use parameter information that can be freely changed and set depending on the system, and can be used flexibly even when changing or changing opaque and uncertain event information.

State register 103 sets the first state code of the current state.

The contents of the RAM 102 are the jump destination address and the second state code of the next state to be taken, and the addresses are the event code output from the associative memory 101 and the first state code of the state register 103.

This allows instantaneous pointers to new states and processing routines from events and current states.

Moreover, associative memory 101 and RAM 102
Since the contents of are expressed as a table rather than a program, debugging is very easy.

Next, a general-purpose register 104, an arithmetic unit 105, a program counter 106, an execution control circuit 107,
The instruction buffer 108 and the input/output control circuit 109 are included in a commercially available general-purpose CPU, and will be briefly explained below.

General purpose register 104 is a temporary storage circuit for multiple operations and transfers.

The arithmetic unit 105 performs the same arithmetic operations as the arithmetic unit in the general-purpose CPU.

Program counter 106 indicates a pointer to the next instruction to be executed.

The execution control circuit 107 extracts the instructions from the instruction buffer 108, decodes them, and sends them to the arithmetic unit 105 and the general-purpose register 10 to execute operations, transfers, etc.
4. Control the program counter 106.

The input/output control circuit 109 receives an address signal AD and data DT for instructing the address of the external memory.
Controls the input/output signals of the command buffer 10
Send to 8.

The execution control circuit 107 is a program counter 10
The pointer indicated by 6 is output as an address signal AD through the input/output control circuit 109, the data DT of the instruction indicated by the address is fetched from the input/output control circuit 109, and sent to the instruction buffer 108, and at the same time, the value of the program counter 106 is read. Count up by one.

The execution control circuit 107 takes out the instructions in the instruction buffer 108, decodes them, and sends them to the input/output control circuit 10.
9. Transfer data between the external memory and the general-purpose register 104 and perform data operations using the general-purpose register 104 and the arithmetic unit 105.

If the instruction in the instruction buffer 108 is an instruction to capture event information, the input/output control circuit 1
Event information is taken in from the outside through the event register 100 as the first event information.
Transfer to.

As a result, as described above, the state code output from the RAM 102 is set in the state register 103 as the first state code, and the jump destination address is set in the program counter 106. From then on, similar operations are performed from the set address.

〔Effect of the invention〕

As explained above, the transmission control processor of the present invention is capable of developing transmission control procedures by adding hardware that instantaneously determines what should be processed when an event in an abnormal state occurs using a table. This has the effect that the time can be shortened and high-speed processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 100...Event register, 101...Associative memory, 102...RAM, 103...State register, 104...General-purpose register, 105...
Arithmetic unit, 106...Program counter, 107
...Execution control circuit, 108...Instruction buffer, 1
09...Input/output control circuit.

Claims (1)

[Claims] 1 An event register for setting only first event information, storing a plurality of second event information and event codes in pairs, and storing a plurality of second event information and event codes corresponding to the second event information that matches the first event information. An associative memory that outputs an event code, a state register that sets only the first state code of the current state, and a state register that stores the pointer to the processing routine and the second state code of the next state. A transmission control processor having a memory output and a storage circuit whose address is the first status code.