JPH053768B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a configuration of a logic circuit integrated into an array in one chip.

In recent years, high voltage transistors, which are necessary to drive dot matrix display devices such as PDPs, ELs, and fluorescent display tubes, have been integrated into ICs along with logic circuits for control.
There is a movement to reduce the size or cost of devices by increasing the size of the device.

These display devices are composed of a large number of row and column electrodes having the same structure, and it is common to selectively drive each row or column electrode with the same drive waveform. For this reason, it is desirable for a driving IC to include many high-voltage transistors and control circuits with the same function on the same chip. In other words, integrating as many control circuits and high-voltage transistors as possible into an array of ICs will greatly contribute to the miniaturization and cost reduction of devices.

The factors that determine how many circuit blocks with the same function can be arranged in this IC are power consumption, integration density, and IC cost. If the power consumption is large, the performance of the element will deteriorate and reliability will be impaired. Furthermore, if the integration density is low, the chip size becomes large, leading to a decrease in yield and an increase in cost. Conversely, it is possible to reduce IC costs by increasing the number of built-in circuit blocks by increasing the integration density and reducing the number of circuits per unit function, and by reducing the chip area.

At present, the reality is that the number of circuit blocks that can be built in is determined by integration density rather than power consumption. Therefore, if the integration density cannot be changed, if a certain number of circuit blocks are incorporated, the chip area will increase and the yield will decrease.

FIG. 1 shows an example of the configuration of an array IC that incorporates a conventional control circuit that suffers from such problems. The figure shows a configuration using MOS transistors as an example. Basically, 21-2
7 input buffers, 11 shift registers, 12
latch circuit, 13 gate circuits, BFi (i=1
~n) output buffers and HVi (i=1~n) high voltage MOS transistors. Among these, the shift register 11, the latch circuit 12,
Gate circuit 13, output buffer BFi, high withstand voltage
The MOS transistors HVi are one unit of circuit block, and n pieces are integrated into an array on one chip. Each unit block is an output signal SRi (i=1 to n) of the i-th shift register 11.
are connected in series by being sent to the input of the i+1-th shift register 11.

Input data is sent to the shift register 11 constituting the first unit block from the DI terminal via the input buffer 21. In addition, a clock signal CL is applied to each shift register 11 via an input buffer 22 and an inverting input buffer 23.
Sent as cl. Each latch circuit 12 includes
A strobe signal St, which functions to send input data to the gate circuit 13 and disconnect it from the shift register 11, is sent as S via an input buffer 24 and an inverting input buffer 25. Furthermore, the gate circuit 13 receives signals OE and CP for controlling the gate through input buffers 26 and 2, respectively.
7 as OE' and CP'.

In the shift register 11, the control signal is “1”
When the state is reached (high level), switch _T1 is turned on (at this time, since cl is "0", _T2 is in the off state), input data is taken in, and the control signal is
When cl changes to "1" state, _T3 is turned on and data is sent to the output terminal SRi. In this case, the data input to the shift register and the output signal appearing at the output terminal SRi have the same phase. The data appearing at the final stage output SRn of the cascaded shift registers is waveform-shaped by the output buffer 28 and sent to the SOn terminal while being in phase.

In addition, in the latch circuit 12, the control signal S is set to "1" and the switch T5 is turned on (at this time,
Since S="0" is given to T6, switch T
6 is turned off), and the input data is passed through two inverters 35 and 37 and sent to the output terminal _L1 . When the latch state is desired, the control signal S is set to "0" (becomes "1") and the switch T5 is turned off (T6 is turned on). This way,
When the strobe signal St (in phase with S) transitions to "0", the data appearing at the output of the shift register is held at the _L1 terminal and enters the gate circuit 13. Similarly, the output SRi of each shift register 11 when St changes to "0" is held in the output Li of the other latch circuits. in this case,
The input signal and output signal of latch circuit 12 are in phase.

Furthermore, in the gate circuit 13, the output signal SRi of the latch circuit and the control signal OE' are connected at the gate 38.
NAND gate processing is performed, and gate 39 performs NOR gate processing between the output signal of gate 38 and control signal CP'.

The buffers BF1 to BFn provided at the final stage receive the output signal from the gate 39, improve the current supply output, and drive the transistors HV1 to HVn, respectively.

In addition, the normal rotation type input buffers 21, 23, 24,
26, 27 and the output buffer 28 are usually composed of two stages of inverters.

Further, each of the input buffers 21 to 27 and the output buffer 28 is formed in one stage in the IC chip.

In an IC configured in this way, until the data input from DI appears at the output terminal Li of the latch circuit 12, the in-phase state is maintained at the outputs of each circuit so that the system functions conveniently. It's summery. This means that the inverter 2 is connected to the input buffer 21.
It is realized using two inverter stages 35, 37 of the latch circuit 12. Furthermore, the in-phase state is maintained until the input data is sent to the output SRn of the final stage shift register and the output terminal SOn of the output buffer 28.

In such a conventional configuration, the area occupied by the inverter stage 37 constituting the latch circuit 12 is too large to be ignored within one circuit block.
Therefore, the larger the number of circuit blocks, the larger the absolute area occupied by the inverter 37 within the chip. For this reason, as the number of circuit blocks increases, the chip area only increases in proportion, and conventionally no reduction rate of the chip area has been taken. When the chip area increases in this way, there is a problem that the yield of IC chips decreases and costs increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide an array IC with a built-in control circuit that alleviates the above-mentioned conventional drawbacks. According to the present invention, the array IC has control circuits built in an array, and includes at least one of the components of a shift register, a latch circuit, a gate circuit, an output buffer, and a single transistor connected in cascade. According to the present invention, there is obtained an array IC incorporating a control circuit characterized in that a plurality of stages of circuit blocks each comprising a circuit including a latch circuit are provided, and the latch circuit is of a one-stage inverting type.

Hereinafter, the present invention will be explained in detail using the drawings. FIG. 2 shows an embodiment of the configuration of an array IC incorporating a control circuit according to the present invention.
Note that the same numbers and symbols as in FIG. 1 represent the same components. Further, in the present invention, an example will be described in which a transistor with a MOS structure is formed on a P-type semiconductor substrate, but the substrate may be of any type, and transistors with other structures such as ECL or bipolar, etc., other than MOS may be used. Even if the configuration is configured as follows, the gist of the present invention is not impaired.

One embodiment of the present invention is characterized in that the latch circuit, the input buffer provided for sending input data to the shift register, and the output buffer for shaping the waveform of the output of the final stage of the cascaded shift registers are of an inverting type. There is. That is, in addition to the non-inverting input buffer 21 and output buffer 28, inverters 21' and 28' are provided in series. Also,
As shown in the latch circuit 12', only one stage of inverter 35 is provided in the path through which the input signal SRi passes.
By doing so, the area of one latch circuit can be reduced to 70-80% of the conventional area. Although the area of the input/output buffer section increases by adding the inverters 21' and 28', since each stage has only one stage, it is small in terms of the overall chip area.

However, a single latch circuit can be used in an array, e.g.
Since 16 or 32 latch circuits are provided, the area of the entire latch circuit is reduced to 70-80% of the conventional latch circuit. This results in a larger absolute area reduction as the number of circuits increases. That is, since the chip area can be reduced, the yield of IC can be improved and the chip cost can be reduced.

The overall configuration and operation will be explained below. In addition, 2
The detailed operations and configurations of the input buffer, shift register, and gate circuit except for 1' have already been explained in FIG. 1, and are exactly the same in this embodiment, so a detailed explanation will be omitted.

A shift register 11 controlled by a clock signal CL, a latch circuit 12' controlled by a strobe signal St, a gate circuit 13 controlled by two signals CE and CP, an output buffer BFi and A circuit block consisting of transistors HVi is provided in n-stage cascade connection. However, only the shift registers 11 connected by SRi are actually connected in series, and the other component groups are arranged in parallel. Specifically, these circuit blocks are integrated into an array on an IC chip.

On the other hand, a first input buffer group 22 to 27, a second input buffer 21, 21', and a second output buffer are used to waveform shape the clock signal CL, strobe signal St control signals OE and CP, and input data signal DI. Only one each of 28 and 28' is provided in the IC chip.

In an IC having such a configuration, input data is inverted and taken in from the DI terminal to the input terminal of the shift register 11. In this case, since the non-inverting inverter 21 is constituted by a normal two-stage inverter, including the input buffer 21', the second input buffers 21, 21' are constituted by three stages of inverters. However, compared to the conventional method, the number of inverters is increased by one stage, which is negligible compared to the area of the circuit blocks formed in an array. The data taken in by the second input buffer is sampled by the clock signal CL in the shift register 11 (the data is sent to the output when CL is "1"), and the data is sent to the output terminal.
Output to SR1. This output data has a phase opposite to that of the input signal and is temporally shifted by one clock. Further, this data is sampled by the second stage shift register 11 when the next clock signal CL is in the "1" state, and is output in the same phase to the output terminal SR2. Every time the clock signal CL is applied thereafter, data is sequentially sampled in the 3rd to nth shift registers 11, and the output terminals of each stage are sampled.
Appears in SR3 to SRn. The signal of SRn is waveform-shaped and inverted by non-inverting type and inverting type output buffers 28, 28', and is inputted to the terminal of SOn.
Therefore, it is output to the SOn in phase with the input signal. In this case, only one stage of inverter 28' is added in the output buffer section compared to the conventional case, but this can be almost ignored compared to the area of the arrayed circuit block.

The data output to the output terminal SR1 is input into the latch circuit 12' by turning on the switch T5 when the signal S obtained by shaping the strobe signal St is in the "1" state (is in the "0" state). The signal is taken in, inverted and output to its output terminal L1. Therefore, the signal appearing at this output terminal L1 is also in phase with the input data. Of course, the signals generated at the output terminal L1 of other latch circuits are also in phase with the input data signal. Next, when the strobe signal St becomes "0", it changes to "1", turning on the switch T6, but conversely turning the switch T5 off. Therefore, the data taken into 12' during this state transition is output to the L1 terminal, inverted by the inverter 36, and returned to the input section of the inverter 35, but the stable state is maintained, so the signal at the L1 terminal is held. It remains as it was.

This signal is transmitted to the gate circuit 13 and the buffer circuit.
Sequentially sent to BFi to BFn and transistors HV1 to HVn.

Thus, the signal produced at the output terminal of the latch circuit is exactly the same as in conventional circuits. Therefore, I.C.
Its function remains the same as before. However, since the number of inverters can be significantly reduced compared to the conventional method, the chip area can be reduced. Therefore, the yield of ICs can be improved, greatly contributing to cost reduction.

Such an effect becomes greater as the number of circuit blocks increases.

Note that even if the gates 38 and 39 forming the gate circuit 13 are circuits having other gate functions such as NOR and OR, the output buffer BFi
Although the signals outputted to the output terminal Bi are different, this does not affect the purpose of configuring the IC of the present invention.

FIG. 3 shows another embodiment of the structure of an array IC incorporating a control circuit according to the present invention. In this figure, the same numbers and symbols as in FIG. 1 or 2 represent the same components. This embodiment is characterized in that only the latch circuit is of an inverting type. That is, the difference from the configuration shown in the embodiment shown in FIG. 2 is that only a non-inverting input buffer 21 is used for waveform shaping of data input from the DI terminal, and cascade-connected shift registers are used. Also, only a non-inverting type output buffer 28 is used for shaping the waveform of the final stage output. In this case, if the input data to be supplied to the DI terminal is inverted by providing one stage of external inverter before being supplied, the conventional function can be obtained.

In such a configuration, the configuration of the input buffer and output buffer is completely different from the conventional one, and the area of the latch circuit can be made smaller than the conventional one, so the step area can be made slightly smaller than the configuration shown in the example of FIG. can.

In an IC with this configuration, input data supplied to the DI terminal is sent to the shift register 11 by a clock signal.
Captured by control of CL, strobe signal St
is sent to the latch circuit 12' under the control of the latch circuit 12'. Since the latch circuit 12' is of an inverting type like the circuit of FIG. 2, the data output to L1 is an inverted signal of the input data. Therefore, the latched data is also an inverted signal of the input data. Other detailed operations and configurations are completely the same as in FIG. 2.

Even with the configuration of this embodiment, the chip area of the IC can be reduced compared to the conventional one, and the yield can be improved.

As explained above, according to the present invention, the chip area of an IC can be reduced, so that the cost of the IC can be sufficiently reduced. This effect becomes greater as the number of unit circuit blocks that are integrated into an array in the form of an IC increases, since the absolute area can be significantly reduced.

[Brief explanation of the drawing]

Figure 1 shows a conventional array IC with a built-in control circuit.
2 is a diagram showing an example of the configuration of an array IC incorporating a control circuit according to the present invention, and FIG. 3 is a diagram showing an example of the configuration of an array IC incorporating a control circuit according to the present invention. It is a figure showing another example. In each figure, 11...shift register, 12
... Latch circuit, 13 ... Gate circuit, 21-2
7...Input buffer, 28...Output buffer, 3
1 to 37 represent inverters, 38 represent NAND gates, and 39 represent NOR gates.

Claims (1)

[Claims] 1. An array IC incorporating control circuits in an array, including at least one of the following components: a shift register, a latch circuit, a gate circuit, a first output buffer, and a single transistor connected in cascade. 1. An array IC with a built-in control circuit, characterized in that a plurality of circuit blocks consisting of a circuit are provided, and the latch circuit is of a one-stage inversion type.