JPH0542693B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The technical outline of the present invention will be described below.

The clock synchronization circuit is used to synchronize a plurality of arithmetic units, such as microprocessor units (MPUs) each having a frequency dividing circuit, when they operate in parallel by synchronizing them to a common clock signal. This provides complete clock synchronization. The synchronization method uses a low-frequency clock signal obtained by dividing the regular clock signal to synchronize the phase of one of the arithmetic units with the other arithmetic units as a reference, and then switches to the regular clock signal. .

[Industrial application field]

The present invention relates to a circuit for synchronizing clock signals between a plurality of arithmetic units.

[Prior art and problems to be solved by the invention]

There are cases where it is desired to operate multiple arithmetic units in synchronization. For example, as shown in Figure 2, microprocessor units (MPU1, MPU
2) may be configured as a dual unit, fed with a common clock signal CLK, and operated in synchronization with this clock signal. For example, if the clock signal frequency is 8MHz, each MPU1 and MPU2
Inside the clock, this clock signal is divided by a clock state counter, for example by 1/4, to create multiphase clocks φ ₁ and φ ₂ , making it possible to output the internal state to the outside. ing. However, each of the multiphase clocks φ ₁ and φ ₂ has a frequency divided by 4, φ ₁₁
~ _φ14 , _φ21 ~ _φ24 , so for example, as shown in FIG. 3, _φ11 and _φ21 are outputted, respectively, in response to the first clock signal CLK. There are no guarantees. Therefore, even if φ ₁ and φ ₂ are simply compared, the timing on the MPU2 side may be φ ₂₃ compared to the timing of φ ₁₁ . Therefore, when used as a dual processor, simply applying a common clock signal and comparing the frequency-divided signals φ ₁ and φ ₂ does not guarantee that completely synchronous operations are performed.

The same applies when performing a functional comparison test of two MPUs.

Therefore, a clock synchronization circuit as shown in FIG. 4 has been proposed. That is, a circuit 6 for detecting the phase difference between the two frequency-divided signals φ ₁ and φ ₂ and an AND gate 3 are connected as shown in the figure to synchronize the clocks of both MPUs 1 and 2. FIG. 5 shows an operation timing diagram of the circuit shown in FIG. 4. clock signal
If the frequency of CLK is 8MHz, its period T is
It becomes 125nsec (Figure 5a). Clock signal CLK
A circuit 6 detects the phase difference between the signals φ ₁ and φ 2 output from the frequency dividing circuits of each MPU 1 and _{2 in response to the falling edge of the signal φ 1 , φ 2} . This detection signal inhibits AND gate 3, so if there is a phase difference, clock signal CLK is not applied to MPU1, and when the phases match, clock signal CLK is applied to MPU1 again, and from then on. , parallel synchronous operation becomes possible.

However, even if both MPUs 1 and 2 are manufactured using the same process, there will be variations in characteristics.
As shown in FIG. 5b, cases often arise in which φ ₁ occurs with a delay. There may also be cases where the difference in operating time between the MPUs 1 and 2 exceeds the period T described above. For example, for T=125nsec, the operating time difference=
When it comes to 130 nsec, a problem arises in that the circuit shown in FIG. 4 cannot synchronize.

Such problems have become more apparent as microprocessor units become faster. Therefore, it is impossible to construct a dual processor with complete clock synchronization. In addition, in comparison tests between microprocessor units, there are cases where it is unavoidable to temporarily use a low frequency clock signal CLK, making it impossible to perform sufficient tests at high frequencies. .

[Means to solve the problem]

In order to solve the above-mentioned problems caused by manufacturing variations in arithmetic units such as microprocessor units, the present invention provides a clock pulse selection circuit that selectively outputs either a regular clock pulse or a frequency-divided clock pulse obtained by dividing the clock pulse. , inputting a frequency-divided signal of the clock signal from at least two arithmetic units operating in parallel in response to the clock signal from the clock pulse selection circuit;
A circuit for detecting the phase difference or synchronization between the divided clock signals from these arithmetic units, and a circuit for detecting the phase difference or synchronization between the divided clock signals from the arithmetic unit, and when the output signal from the phase difference/synchronization detection circuit indicates that there is a phase difference, the arithmetic operation is performed from the clock pulse selection circuit. a clock signal disabling circuit for disabling a clock signal applied to one of the devices, and when the output signal from the phase difference/synchronization detection circuit indicates that synchronization has been achieved, the clock signal from the clock pulse selection circuit is To provide a clock synchronization circuit which switches a signal from a frequency-divided clock pulse to a regular clock pulse.

[Effect]

In the initial stage of synchronization, synchronization is achieved using a frequency-divided clock signal obtained by dividing the normal clock signal. Even if there are operational variations between arithmetic units, their values are fixed, so by lowering the frequency of the clock signal, the variations will be relatively small during synchronization, ensuring synchronization. You can take it.

Once synchronized, a regular clock signal causes parallel operation.

〔Example〕

Embodiments of the invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a clock synchronization circuit as an embodiment of the present invention. The circuit shown in FIG. 1 includes a clock pulse selection circuit 5 which selectively outputs either a regular clock pulse CLK or a frequency-divided clock pulse CLK' obtained by dividing the clock pulse in a frequency divider 51 via a switch circuit 52; The signals φ ₁ and φ 2 obtained by frequency-dividing the clock signals from at least two arithmetic units 1 and ₂ operating in parallel in response to the clock signal from the clock pulse selection circuit are input, and these arithmetic units 1 and 2 2
and a circuit 4 for detecting the phase difference Δθ or synchronization between the frequency-divided clock signals φ ₁ and φ ₂ from the clock pulse selection circuit 4, and when the output signal from the phase difference/synchronization detection circuit 4 indicates that there is a phase difference, the clock pulse is selected. a clock signal applied from circuit 5 to each one of said arithmetic units;
A clock signal prohibition circuit 3 for prohibiting CLK' is provided. Its basic operation is that when the output signal from the phase difference/synchronization detection circuit 4 indicates that synchronization has been achieved, the clock signal from the clock pulse selection circuit 5 is divided into clock pulses.
A switch circuit 52 switches from CLK' to the regular clock pulse CLK.

FIG. 6 shows a more specific example of the circuit shown in FIG. 1. In FIG. 6, the clock pulse selection circuit 5 shown in FIG. 1 includes a 1/8 frequency divider 51,
It consists of a switch circuit 52 in which NAND gates 521 to 523 and an inverter 524 are connected as shown. In addition, the phase difference/synchronization detection circuit 4
are D-type flip-flops 41, 42 and
NAND gates 43 are connected as shown.
A phase difference detection signal is taken out as the output of the NAND gate 43, and a synchronization detection signal is taken out from the output terminal of the D-type flip-flop 42.
The internal frequency signals φ ₁ and φ _{2 of MPU1 and 2} are respectively D
Clock terminals of type flip-flops 41 and 42
Applied to CK. Clock signal inhibition circuit 3
is an AND gate.

The operation of the circuit shown in FIG. 6 will be described below with reference to the timing shown in FIG.

In the initial state, D-type flip-flops 41, 4
It is assumed that the reset signal RST is applied to the flip-flops 41 and 42 and that the flip-flops 41 and 42 are reset. Therefore, the output signal S41 of the flip-flop 41 is at a low level (FIG. 7c), and the synchronization detection signal is at a high level (FIG. 7f).

Since the synchronization detection signal is at high level, the NAND gate 5 in the clock pulse selection circuit 5
The output of 23 is the 1/8 frequency divider 5 of the clock signal CLK.
A frequency-divided clock signal CLK' whose frequency is divided by 1 is output. Here, the frequency of the clock signal CLK is
If the frequency is 8MHz, the frequency of the divided clock signal CLK' will be 1MHz. Therefore, its period T' is 1 μsec. On the other hand, the period T of the regular clock signal CLK is
It is 125 nsec (Figure 7a).

Since the phase difference detection signal is at a high level (Fig. 7e), the frequency-divided clock signal CLK' is
2 is applied at the same time and starts operating. Internal frequency division clock signals φ 1 and φ 2 whose frequency is divided by a frequency division circuit (not shown) in each MPU ₁ and ₂ in response to the frequency division clock signal CLK' are shown in FIGS. 7b and 7d. Assume that there is a timing shift, that is, a phase difference, as shown in FIG. First, when the signal _φ1 falls, the output signal S41 of the flip-flop 41 becomes high level (FIG. 7b,
c). On the other hand, since the signal φ ₂ remains at a low level, the output of the flip-flop 42 remains at a high level. Therefore, at the same time as the synchronization detection signal remains at a high level, the phase difference detection signal P becomes a low level. (Figure 7e). As a result, the AND gate 3 is inhibited, and the divided clock signal CLK' is no longer applied to the MPU 1.

When the signal φ ₂ from the MPU 2 once goes to high level and then falls (Fig. 7d), the output of the flip-flop 42 goes to low level, that is, the synchronization signal goes to low level, and the phase difference detection signal goes to high level. (Fig. 7 e, f). As a result, it is detected that both MPUs 1 and 2 are synchronized with respect to the clock signal CLK'. That is, MPU
The first frequency-divided signal φ ₁₁ of the φ ₁ signal of MPU 2 coincides with the first frequency-divided signal φ ₂₁ of the φ ₂ signal of MPU2. This is done by AND gate 3.
Until the th frequency divided signal φ ₁₁ and φ ₂₁ match,
This is because the MPU1 side was stopped.

Once synchronization is established in this way, the output of the clock pulse selection circuit 5 is switched by the synchronization detection signal so that the normal clock signal CLK is output. Also, since the phase difference detection signal P is at high level, the regular clock signal CLK is applied to both MPU1 and
2 in parallel, MPUs 1 and 2 can operate synchronously under the regular clock signal CLK.
Once the two are synchronized as described above, they continue to be stably synchronized even with the high-frequency regular clock signal CLK.

During the above synchronization detection, even if there is a deviation in characteristics between MPUs 1 and 2, the frequency is set to a low frequency by the divided clock signal CLK', so that the ratio to the period T' is the ratio to the period T of the regular clock signal. It becomes 1/8 of that. Therefore, it becomes possible to achieve stable and reliable synchronization.

In the above embodiment, once synchronization is established, the phase difference/synchronization detection circuit 4 may be disconnected.

Further, the above synchronization and parallel synchronization operations are not limited to two MPUs, but can be expanded to multiple MPUs.

[Effects of the Invention] As described above, according to the present invention, synchronization can be achieved reliably even if there are variations in characteristics between arithmetic units, and multiple arithmetic units can be synchronized with a high-frequency clock signal. Parallel operation of devices becomes possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a clock synchronization circuit as an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional dual processor, FIG. 3 is a timing diagram of FIG. 2, and FIG. 4 is a conventional dual processor. Figure 5 is a signal timing diagram of the circuit in Figure 4, Figure 6 is a more specific circuit diagram of the circuit in Figure 1, and Figure 7 is a signal timing diagram of the circuit in Figure 6. . (Explanation of symbols), 1, 2...Microprocessor unit, 3...AND gate, 4...Phase difference, synchronization detection circuit, 5...Clock pulse selection circuit, 51...
Frequency dividing circuit, 52...switch circuit.

Claims (1)

[Claims] 1. A clock pulse selection circuit that selectively outputs either a regular clock pulse or a frequency-divided clock pulse obtained by dividing the clock pulse, which operates in parallel in response to a clock signal from the clock pulse selection circuit. A circuit that receives signals obtained by frequency-dividing the clock signals from at least two arithmetic units and detects a phase difference or synchronization between the divided clock signals from these arithmetic units, and from the phase difference/synchronization detection circuit. a clock signal inhibiting circuit that inhibits a clock signal from being applied from the clock pulse selection circuit to one of the arithmetic units when the output signal from the phase difference/synchronization detection circuit indicates that there is a phase difference; A clock synchronization circuit, wherein the clock signal from the clock pulse selection circuit is switched from a divided clock pulse to a regular clock pulse when the output signal indicates that synchronization has been established.