JPH0542701B2 - - Google Patents

Description

[Detailed description of the invention] The invention will be explained in the following order.

A. Field of industrial application B. Outline of the invention C. Prior art (Figs. 6 and 7) D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect (Fig. 1) (Figure 2) G Example (Figures 3 to 5) H Effect of the invention A Industrial field of application This invention is applicable to large-scale systems in which the CPU and I/O registers are provided on separate boards. The present invention relates to technology for transferring data from an I/O register to an I/O register.

B. Summary of the Invention This invention provides, when transferring data from a CPU to an I/O register on a separate board, a transfer control circuit and a buffer memory are provided on the CPU side, and an enable control circuit is provided on the I/O register side.
Data from the CPU is transferred to the I/O register side via the buffer memory, and a control signal is supplied from the transfer control circuit to the enable control circuit at the start of reading from the buffer memory.
By sequentially enabling the O registers and writing data into them, the number of connection lines between the CPU board and the I/O register board can be minimized.

C. Prior Art Data from the CPU is transmitted to external devices via I/O registers. In the case of large-scale systems, the CPU and I/O registers are installed on separate boards, but in this case, control signals are supplied from the CPU side to the I/O registers to control the I/O registers.
It must control the transfer of data from the CPU.

FIG. 6 shows a conventional example of such a data transfer device, where 1 is a board on which a CPU 10 is placed, and 2 is a board on which a plurality of I/O registers 5 ₀ , 5 ₁ , 5 ₂ . . . are placed. be. In this example, a latch enable control circuit 6 is also provided on the substrate 2 side.

The data bus 11 from the CPU 10 is connected to the input terminals of the I/O registers 5 ₀ , 5 ₁ , 5 ₂ .
It is supplied to O registers 5 ₀ , 5 ₁ , 5 ₂ . Further, both the address bus 12 and the control bus 13 from the CPU 10 are connected to the latch enable control circuit 6, and the address signal ADRS and the control signal CTL are supplied to the latch enable control circuit 6.

The data DATA is transferred from the CPU 10 as follows. That is, when data DATA is sent out from the CPU 10 through the data bus 11, address data ADRS of that data is sent out through the address bus 12 at the same time.

From the control signal CTL and the address data ADRS, the latch enable control circuit 6 obtains an enable signal that enables one I/O register among a plurality of registers to latch for data indicating a specific address, and determines the enable state. Data DATA is latched in the register. Similarly, when a different address is reached, data DATA is latched into a different register. In this way, data DATA from the CPU 10 is sent to a plurality of I/O registers 5 ₀ ,
Transferred to 5 ₁ , 5 ₂ .... In this case, the same number of I/O registers 5 ₀ , 5 ₁ , 5 ₂ . . . are provided as the number of addresses designated for transfer among the address data ADRS from the CPU 10, and each register 5 ₀ ,
Each of 5 ₁ , 5 ₂ . . . has a 1:1 relationship with each address. For example, data at address 0 is latched in register ₅₀ .

Note that the latch enable control circuit 6 may be provided on the board 1 on the CPU 10 side as in the example shown in FIG. In the case of this example in FIG _.
Connection lines 14 ₀ , 14 1 , 14 ₂ ... 14 n that transmit latch enable signals for the number of ₁ , _{5 2} ... 5n
It is.

D Problems to be solved by the invention In the case of the example in Figure 6, all buses of the CPU 10,
In other words, data bus 11, address bus 12, and control bus 13 are all driven to perform I/O.
It is controlled on the register side, and requires many signal lines as connection lines between the boards 1 and 2, which poses problems in terms of maintainability and reliability.

In addition, even in the case of the example in FIG. 7, one control line is required for each I/O register, and the I/O
When the number of registers becomes large, a problem similar to the example in FIG. 6 occurs.

E. Means for Solving the Problems FIG. 1 is a block diagram of an example of the apparatus of this invention.

That is, a buffer memory 20 and a transfer control circuit 300 are provided on the substrate 1 side. Furthermore, an enable control circuit 60 is provided on the substrate 2 side.

Address bus 12 and control bus 13 from CPU 10 are connected to transfer control circuit 300, and data bus 11 is connected to buffer memory 20.

Also, a predetermined clock pulse CK (this is
10 can be used) is supplied to the transfer control circuit 300.

A chip select signal CS and read and write address data of the memory 20 are obtained from the transfer control circuit 300 and supplied to the buffer memory 20. Furthermore, the transfer control circuit 300 sends an enable start signal in synchronization with the clock pulse CK at the start of reading from the buffer memory 20.
ES is obtained and supplied to the enable control circuit 60 on the board 2 side. This enable control circuit 60 is composed of, for example, a shift register, and has a signal
ES is applied to its data input. Also, the clock pulse CK is applied to this enable control circuit 60.
This signal is supplied to the clock terminal of the shift register that makes up the clock. The clock pulse supplied to this shift register 60 can be one generated on the substrate 2 side as long as it is synchronized with the pulse CK.

In addition, a write control signal is sent from the CPU10.
MWTC is supplied to buffer memory 20, and writing and reading of this memory 20 is controlled.

Then, the data read from the buffer memory 20 is transferred to the I/O registers ₅₀ , ₅₁ , ₅₂ ...5n.
is supplied to In this example, buffer memory 2
0 address and multiple I/O registers 5 ₀ , 5 ₁ ,
There is a 1:1 correspondence with 5 ₂ ...5n.

F. Effect Data DATA from the CPU 10 is written into the buffer memory 20 through normal memory access by the transfer control circuit 300. That is, the CPU 10 sends data DATA and address data ADRS, and furthermore, a write control signal MWTC is supplied to the buffer memory 20. Then, the transfer control circuit 300
Chip select signal to buffer memory 20
CS is supplied and address data ADRS
is supplied as is, and data DATA is written into this memory 20 in accordance with address data ADRS.

Next, when a read command is supplied to the transfer control circuit 300 via the control bus 13, the transfer control circuit 300 clocks the clock pulse CK (second
Address data ADRB (FIG. B) synchronized with FIG. A) is supplied to the buffer memory 20, and a chip select signal CS is also supplied. At this time, since the write control signal MWTC is not in the write state, the buffer memory 20 is in the read state, and the data DATA (FIG. 2C) is sequentially read out in accordance with the address data ADRB from the transfer control circuit 300.

At the start of this readout, the transfer control circuit 300 supplies the signal ES (FIG. 2D) to the enable control circuit 60 of the substrate 2. Therefore, the enable control circuit 60 outputs an enable signal that sequentially becomes, for example, a high level in synchronization with the clock pulse CK.
EN ₀ , EN ₁ , EN ₂ ... EN ₈ , EN ₉ ... (E,
F, G...H, I...) are obtained, and the I/O registers 5 ₀ , 5 ₁ , 5 ₂ ... are sequentially enabled in synchronization with the change in address data, and the read data DATA is obtained. are I/O registers 5 ₀ , 5 ₁ , 5 ₂
...is sequentially latched.

G. Embodiment FIG. 3 shows a specific embodiment of the example shown in FIG. 1 when this invention device is used for transferring image processing control data of an image processing system. In the figure, the left side of the broken line indicates the substrate 1 side. , the right side of the broken line indicates the image processing device side.

In this example, the buffer memory 20 is supplied with image control data DATA such as control signals and control parameters from the CPU 10 via the data bus 11 at its data input terminal.

It is also assumed that data is written to four addresses from address 0 to address 3 in this buffer memory 20. Therefore, of the address data ADRS on the address bus 12, those indicating addresses 0 to 3 are address data for this buffer memory 20.

On the board 2 side, in this example, on the image processing device side, four I/O registers 50 to 53 are provided corresponding to these four addresses. The read control data is supplied.

In addition, this buffer memory 20 has a CPU 10
A write control signal MWTC is supplied from the device, and when this signal MWCT is at a low level, it is in a writable state, and when it is at a high level, it is in a readable state. However, this buffer memory 20 can be accessed when the chip select signal CS, which will be described later, is at a low level, and at that time the signal
The state is read or written depending on whether MWTC is high or low.

31 is a multiplexer for switching address data, and address data ADRS from the CPU 10 via the address bus 12 is supplied to one input terminal A of the multiplexer.

Transfer control circuit 300 is numbered in the 30s.
30 is an address counter of the buffer memory 20, and address data ADRB from this counter 30 is supplied to the other input terminal B of the multiplexer 31.

Reference numeral 41 denotes an input terminal for the clock pulse CK supplied to the counter 30. In this example, the clock pulse CK is 5 MHz (period: 200 nsec).

32 is an address decoder, and address bus 12
When the address data specifies the address of the buffer memory 20, its output SE becomes low level. This output SE is supplied to the select terminal of multiplexer 31, and this output SE
When is at a low level, the address data ADRS supplied from the multiplexer 31 to the input terminal A is obtained at its output, and when this output SE is at a high level, the address data ADRB supplied from the multiplexer 31 to the input terminal B is obtained from the multiplexer 31. You get that output.

The output SE of address decoder 32 is also supplied to AND gate 38. The output of this AND gate 38 becomes a chip select signal CS, and this signal CS is supplied to the chip select terminal of the buffer memory 20.

33 is a start address generation circuit that generates data equal to the first address when sequentially specifying addresses in the buffer memory 20; 34;
is an end address generation circuit that generates data equal to the last address. In this example, address data indicating address 0 is obtained from the start address generation circuit 33, and address data indicating address 3 is obtained from the end address generation circuit 34.

Further, 35 is an end address match detection circuit,
It is detected whether the address data ADB from the counter 30 is equal to the end address from the end address generation circuit 34, and an output PI is obtained which becomes high level when the two do not match and becomes low level when the two match. .

This match detection output PI is the address counter 30
When the output PI becomes low level, the counter 30 stops counting.

The coincidence detection output PI is also connected to an AND gate 3 for forming a chip select signal CS via a latch circuit 36 for timing adjustment and a NOR gate 37.
8.

39 is a latch enable generation circuit, which receives address data ADB from address counter 30.
In response, enable signals EN ₀ -EN ₃ for registers 50 - 53 are formed, respectively. In this case, registers 50 to 53 correspond to addresses in the buffer memory 20, and register 5 corresponds to address 0.
A register 51 corresponds to addresses 0 and 1, a register 52 corresponds to address 2, and a register 53 corresponds to address 3.

In this example, data transfer is performed within the vertical blanking period in consideration of the influence on the image signal.

40 is a transfer start pulse generation circuit, to which a vertical synchronizing pulse is supplied through an input terminal 42, and a clock pulse CK is also supplied from an input terminal 41, from which a start pulse ST synchronized with this clock pulse CK is obtained. It will be done.

In the above configuration, the buffer memory 20 is
The operation of writing control data from the CPU 10 will be explained.

FIG. 4 is a time chart when writing from the CPU 10 to address 0 of the buffer memory 20, and will be explained below along with this.

First, information on address 0 is sent from the CPU 10 via the address bus 12 as address data ADRS (FIG. 4A). Then, the address decoder 32 determines this, and the buffer memory 2
It is determined that 0 has been accessed, and its output SE (B in the same figure) becomes low level. Therefore, address data ADRS from the CPU 10 is obtained from the multiplexer 31 (see C in the figure), and is supplied to the address input terminal of the buffer memory 20.

When the output SE of the address decoder 32 becomes low level, the chip select signal CS from the AND gate 38 (E in the figure) also becomes low level, and the buffer memory 20 becomes active. and,
The data DATA to be written to data bus 11 is
The data is sent from the CPU 10 (D in the figure), and then the write control signal MWTC (F in the figure) becomes low level, and the data is written to address 0 of the buffer memory 20.

Then, after this write is completed, the write control signal MWTC returns to high level and write is disabled, and when the address data ADRS from the CPU 10 changes to an address other than 0 to 3,
The output SE of the address decoder 32 becomes high level, the address data ADRB from the counter 30 is obtained from the multiplexer 31, and the output CS of the AND gate 38 becomes high level, the buffer memory 20 becomes inactive, and 1 One write cycle is completed.

Other addresses 1, 2, and 3 of buffer memory 20
Writing to the address is done in the same way. Note that it is also possible to sequentially write to multiple addresses in one write cycle.

Next, the operation of transferring the control data written in this way from the buffer memory 20 to the registers 50 to 53 will be explained.

When the vertical synchronizing pulse VD (Fig. 5 A and B, FIG. 5 B is an enlarged view) is supplied to the transfer start pulse generation circuit 40 through the input terminal 42, it is synchronized with the clock pulse CK (Fig. 5 C). A start pulse ST (D in the same figure) is obtained, which is supplied to the preset terminal of the address counter 30.
The counter 30 is preset to the start address count value from the address generation circuit 33, ie, "0".

Then, the address data ADRB becomes data at address 0, so the end address match detection circuit 3
At 5, the output PI (F in the figure) becomes high level, the counter 30 starts counting, counts the clock pulse CK, and sets the address data ADB (E in the figure) to addresses 0, 1, 2, and 3. Step by step.

At this time, the address data ADRS indicating addresses 0 to 3 is not sent from the CPU 10, and therefore,
Since the output SE of the address decoder 32 is at a high level, the count value output ADRB of the address counter 30 is obtained from the multiplexer 31.

Furthermore, since the output PI of the coincidence detection circuit 35 becomes high level, the output of the NOR gate 37 becomes low level, and therefore the chip select signal CS (G in the same figure) which is the output of the AND gate 38 also becomes low level. Memory 20 becomes accessible.

And in this vertical blanking period,
Since the write control signal MWTC from the CPU 10 is at a high level, the buffer memory 20 is in the read state, and the buffer memory 20 reads 0, 1, 2, 3 according to the address data ADRB.
Address data D0, D1, D2, D3 (FIG. 5H) are read out.

On the other hand, at this time, the address data ADRB is
It is also supplied to the latch enable generating circuit 39, and when data at address 0 is detected therein, an enable start signal ES (FIG. 5I) is obtained. This is then supplied to a shift register 61 as an enable control circuit. Therefore, in this shift register 61, the start signal ES is sequentially transferred by the clock pulse CK, and the I/O registers 50 to 53 are shifted for one cycle of the clock pulse CK in correspondence with each read address of the buffer memory 20. Enable signals EN ₀ , EN ₁ , EN ₂ , EN ₃ for each period (J, K, L,
M) becomes low level, and data D0, D1, D2,
D3 is register 50, 51, 52, 53 respectively
will be written to. That is, for example, during the period of address data at address 0, the enable signal EN ₀ becomes low level, and the data D0 read from the memory 20 is written into the register 50.

When the output data ADB of the counter 30 reaches the data at address 3, the output PI (5th address) of the coincidence detection circuit 35
Figure F) becomes low level. However, the output of the latch circuit 36 is less clock pulsed than this output PI.
Since it becomes low level with a delay of one cycle of CK, the chip select signal CS from the AND gate 38 reads the data at address 3 from the memory 20 and writes it to the register 53, and then becomes high level and becomes disabled.

Then, the counter 30 stops counting due to the output PI, and the output data ADRB remains at address 3 until it is preset to the start address by the start pulse ST of the next vertical blanking period.

The above data transfer operation is performed in about 1 μsec from the leading edge of the vertical synchronization pulse VD, and the CPU 10
The transfer ends while detecting the vertical synchronization pulse. Therefore, buffer memory 2
0 is in a state where control data can be written by the CPU 10 at any time.

In the above example, the transfer start pulse is a case where the device of the present invention is applied to an image processing device, so
Although the vertical blanking period is formed based on a vertical synchronizing pulse from outside the CPU, the present invention is not limited to this, and a transfer start pulse may be obtained from the CPU 10.

Furthermore, it goes without saying that the enable control circuit 60 is not limited to a shift register.

Furthermore, as described above, if a clock synchronized with the clock pulse CK is obtained on the board 2 on the I/O register side, it is not necessary to transmit this clock pulse CK from the board 1 side to the board 2 side.

Of course, the clock pulse CK may be generated on the board 2 side and transmitted to the board 1 side.

H Effects of the Invention According to this invention, multiple pieces of data from the CPU are written to the I/O register via the buffer memory, so writing to the I/O register is possible without controlling the writing of each piece of data. be able to. In this case, the control line from the CPU to the I/O register side only needs to be a line for supplying start pulses to the enable control circuit of the I/O register, and there are more I/O registers than in the conventional system. It also requires very little.

Furthermore, since the number of wires between the boards is reduced, reliability is improved and maintainability is also improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the device of this invention, FIG. 2 is a time chart for explaining the same, FIG. 3 is a block diagram of an example of a specific configuration of the device of this invention, and FIGS. 4 and 5 are A time chart for explaining the same, and FIGS. 6 and 7 are block diagrams of an example of a conventional device. 1 is the board on the CPU side, 2 is the board on the I/O register side, 5 ₀ , 5 ₁ , 5 ₂ ... is the I/O register, 1
0 is a CPU, 11 is a data bus, 12 is an address bus, 13 is a control bus, 20 is a buffer memory, 60 is an enable control circuit, 61 is a shift register, and 300 is a transfer control circuit.

Claims (1)

[Claims] 1. A CPU and a plurality of I/O registers are provided on separate boards, and data from the CPU is transmitted to the plurality of I/O registers.
In the device for transferring data to the O register, the CPU side is provided with a transfer control circuit and a buffer memory, and the plurality of I/O registers is provided with an enable control circuit that controls the supply of enable signals to the plurality of registers. is provided, and the transfer control circuit operates according to a predetermined clock signal, thereby controlling the buffer memory to the CPU.
Data is written in accordance with the address from the CPU, and the written data is read out at the timing of the clock signal, and at the start of reading, the enable control signal is sent from the transfer control circuit to the enable control circuit. A signal is supplied to the circuit and sequentially enables the plurality of I/O registers from the enable control circuit in accordance with a clock signal synchronized with the clock signal, whereby the data read from the buffer memory is The above multiple I/Os
A data transfer device that stores data sequentially in registers.