JPH0543115B2 - - Google Patents

Description

Detailed Description of the Invention "Industrial Application Field" This invention is characterized in that a plurality of display electrodes are formed on the inner surface of one transparent substrate constituting a liquid crystal cell, a thin film transistor is connected to each of the display electrodes, and the thin film transistor is selected. The present invention relates to a liquid crystal display element in which display electrodes are selectively displayed by selectively controlling switching.

"Prior Art" A conventional liquid crystal display element of this type has transparent substrates 11 and 12 made of glass, for example, as shown in FIG.
are provided in close opposition to each other, a spacer 13 is interposed at the peripheral edge thereof, and a liquid crystal 14 is sealed between these transparent substrates 11 and 12. One transparent substrate 1
A plurality of display electrodes 15 are formed on the inner surface of the display electrode 1, and a thin film transistor 16 is formed as a switching element in contact with each display electrode 15, and the drain of the thin film transistor 16 is connected to the display electrode 15.
It is connected to the. A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12, facing the plurality of display electrodes 15.

The display electrodes 15 are, for example, pixel electrodes, and as shown in FIG. 8, square electrodes are arranged close to each other in rows and columns, that is, in a matrix, on the transparent substrate 11. Gate buses 18 are formed along these lines, and source buses (data lines) 19 are formed adjacent to and along each column arrangement of display electrodes 15. A thin film transistor 16 is provided at the intersection of each gate bus 18 and source bus 19, and the gate of each thin film transistor 16 is connected to the gate bus 18 at the intersection of both buses.
, each source is connected to a source bus 19, and each drain is connected to a display electrode 15.

By selecting each one of the gate bus 18 and the source bus 19 and applying a voltage between them, only the thin film transistor 16 to which the voltage has been applied becomes conductive, and the display is connected to the drain of the thin film transistor 16 that has become conductive. Charge is accumulated in the electrode 15 and the liquid crystal 1 in the portion between the display electrode 15 and the common electrode 17 is
By applying a voltage only to the display electrode 15, only the display electrode 15 becomes light transparent or light blocked, and selective display is performed. By discharging the charges accumulated in the display electrodes 15, the display can be erased.

The thin film transistor 16 has conventionally been constructed as shown in FIGS. 9 and 10, for example. That is, a display electrode 15 and a source bus 19 are formed on a transparent substrate 11 using a transparent conductive film such as ITO, and an amorphous silicon film is formed across parallel adjacent portions of the display electrode 15 and source bus 19. A semiconductor layer 21 is formed, and a gate insulating film 22 made of silicon nitride or the like is further formed thereon. On this gate insulating film 22, the display electrode 15 and the source bus 1 are connected via the semiconductor layer 21.
A gate electrode 23 is formed to partially overlap with each other. One end of the gate electrode 23 is connected to the gate bus 18
connected to. In this way, the display electrode 15 and the source bus 19 respectively facing the gate electrode 23
are the drain electrode 15a and the source electrode 19, respectively.
The electrodes 15a, 19a, the semiconductor layer 21, the gate insulating film 22, and the gate electrode 23 constitute the thin film transistor 16. Gate electrode 23 and gate bus 18 are formed simultaneously,
For example, it is made of aluminum.

"Problems to be Solved by the Invention" In this conventional liquid crystal display element, the gate electrode 23 and the drain electrode 1 of each thin film transistor 16 are
Electrostatic (parasitic) capacitances C _gd and C _sg exist between the gate electrode 23 and the drain electrode 15a and the source electrode 19a, respectively. Parasitic resistance R _s whose resistance value changes depending on the area of
There is. These capacitances C _gd , C _sg , and parasitic resistance R _s greatly affect the characteristics of the thin film transistor 16, but if the position of the gate electrode 23 is slightly shifted when forming the gate electrode 23, the capacitance C _gd etc. will directly change. Therefore, variations occur in the characteristics of the thin film transistor 16. For example, if the design value of the width of the overlapping part of these electrodes is 3 microns, and the channel width is w, then if the design value is followed, the capacitances C _gd and C _sg are each proportional to 3 times w. However, if the gate electrode 23 is shifted by 1 micron toward the source electrode 19a, C _gd and C _sg become proportional to twice w and four times w, respectively, and the gate electrode 23
3 is shifted 2 microns toward the source electrode 19a side,
C _gd and C _sg are proportional to 5 times w and 1 times w, respectively. Therefore, the misalignment of the gate electrode 23 has a large effect on the characteristics of the thin film transistor 16. Thin film transistor 16 in liquid crystal display element
If there are variations in the characteristics, display unevenness will occur.

Therefore, an object of the present invention is to provide a liquid crystal display element in which thin film transistors have uniform characteristics.

``Means for Solving the Problems'' According to the present invention, rectangular display electrodes are formed in a matrix on the inner surface of one transparent substrate constituting a liquid crystal cell, and each row of display electrodes is arranged on both sides thereof. A source bus is formed along each row of display electrodes, a gate bus is formed along each row of display electrodes, and between one side of each display electrode and one of the adjacent source buses, a gate bus is formed along one side of each display electrode. The drain electrode is connected to the source bus, and the source electrode is connected to the source bus.
first thin film transistors each having a gate electrode connected to the gate bus;
Between the opposite side of the one side of each display electrode and the other side of the source bus close to it, a drain electrode is placed on one side of the display electrode, a source electrode is placed on the source bus, and a gate electrode is placed on the gate bus. connected second thin film transistors are respectively formed, the second thin film transistors are the same in size, shape and characteristics as the first thin film transistors, and each channel width is set to the same width as when only one thin film transistor is connected to one element electrode. The maximum channel width allowed for the thin film transistor is approximately one-half, and both ends of the source buses on both sides are connected to each other. Since thin film transistors are provided on both sides of the display electrode in this way, even if mask misalignment occurs, when the capacitance of one thin film transistor decreases, the corresponding capacitance of the other thin film transistor increases. ,
The overall capacitance is the same, that is, as designed.

In this way, both thin film transistors are connected in parallel, but if source buses are provided on both sides of each display electrode and both source buses are connected in a loop, one of the source buses can be disconnected. can also be used, and the incidence of defects will be lower accordingly.

"Embodiment" FIG. 1 schematically shows an example of a liquid crystal display element according to the present invention, in which display electrodes 15 are arranged in a matrix, and display is performed in the same manner as in FIGS. 8 and 9. A source bus 19a is formed on one side corresponding to each column of electrodes 15, and the source bus 19a and the display electrode 1 of that column
5 are connected to each other through thin film transistors 16. In this embodiment, each display electrode 15
On the side opposite to the side to which the thin film transistor 16 is connected, there is a thin film transistor 2 on the left side in the figure.
5 are connected to display electrodes 15, respectively. The thin film transistors 25 have their source electrodes connected to the source buses 26 corresponding to each array of display electrodes 15, and both ends of the corresponding pair of source buses 19, 26 are mutually connected for each column array of display electrodes 15. In other words, it is connected in a loop. Although not shown in the figure, the thin film transistor 25
The gate electrode of the display electrode 15 is connected to a gate bus 18 to which the gate electrode of the thin film transistor 16 connected to the display electrode 15 is connected. Therefore, for each display electrode, both thin film transistors 16, 25 are connected in parallel.

As shown in FIGS. 2 and 3 by assigning the same reference numerals to parts corresponding to those in FIGS. 7, 9, and 10, a source bus 26 is formed on the side opposite to the source bus 19 of each display electrode 15. and its source bus 26
A semiconductor layer 27 such as amorphous silicon is formed between the display electrode 15 and the semiconductor layer 2
A gate insulating film 22 is formed on the thin film transistor 25 , and a gate electrode 28 is formed on the gate insulating film 22 .
is configured. The gate electrode 28 is connected to the gate bus 18
connected to.

In the thin film transistor 25 having this structure, as shown in FIG.
A capacitance C _gd2 exists between the overlapping portion with the source bus 26, that is, the drain electrode 15b, and a capacitance C _sg2 exists between the overlapping portion with the source bus 26, that is, the source electrode 26a. However, in this way, two thin film transistors 16 and 25 are formed on both sides of one display electrode 15, respectively.
Moreover, since these are connected in parallel to each other, if the capacitances of the gate electrode 23, display electrode 15, and source bus 19 are C _gd1 and C _sg1 , the capacitances C _gd1 and C _gd2 , and C _sg1 and C _sg2 are each connected in parallel.

Therefore, the capacitances when the gate electrodes 23 and 28 overlap as designed are C _gd1 + C _gd2 , C _sg1 +
Assume that C _sg2 are each 3 times w. That is, the width of the overlap between each gate electrode, drain electrode, and source electrode is 3 microns, and the channel width is w/2. At this time, for example, in FIGS. 2, 3, and 4, if the gate electrode 23 is shifted to the right in the figure, the gate electrode 23 and the gate electrode 28 of the thin film transistor 25 are made by the same mask, so the gate electrode 23 shifts to the right by the same amount, and as a result, the source-to-gate capacitance C _sg1 of the thin film transistor 16 increases, but the source-to-gate capacitance of the thin film transistor 25 increases by the same amount as this increase.
C _sg2 decreases, and the source-gate capacitance of both thin film transistors 16 and 25 becomes three times w, which is the same as the design value. This is also true between the gate-drain capacitance C _gd1 of the thin film transistor 16 and the gate-drain capacitance C _gd2 of the thin film transistor 25; when one increases, the other decreases, and their sum is always equal to constant. Therefore, even if there is mask displacement, the capacitance will always be as designed. Therefore, even if the mask shift during formation of the gate electrode in each part of the display surface of the liquid crystal display element is not uniform, the characteristics of each thin film transistor can be made equal. If the parasitic resistance R _s increases on the thin film transistor 16 side, then the thin film transistor 2
5 side decreases and the sum is always constant.

As shown in FIG. 5, a gate bus 31 is provided for each display electrode 15 on the opposite side of the gate bus 18 in parallel with the row arrangement of each display electrode, and the gate electrode 23 of the thin film transistor 16 is connected to the gate bus 31. , the gate electrodes 28 of the thin film transistors 25 are connected to the gate bus 18, and the gate buses 18 and 31 corresponding to each row array are connected to each other at both ends to form a loop. In this way, the thin film transistors 16 and 25 are provided on both sides of the display electrode 15, and the gate buses 18 and 31 are also connected in a loop like the source buses 19 and 26, thereby making them strong against disconnection. be able to.

Further, as shown in FIG. 6, source buses 19 and 26 are provided for each display electrode 15, and a connection line 33 is provided to connect these source buses 19 and 26, and this source bus connection is provided on both sides of the display electrode 15. Thin film transistors 16 and 25 may be formed between the line 33 and the display electrode 15, respectively. In this case, the semiconductor layer 21 can be formed in common for the two thin film transistors 16 and 25 between display electrodes adjacent in the column direction. In other words, in this example, the source buses 19 and 26 are connected by the connection line 33 between the adjacent display electrodes for each column arrangement of each display electrode 15, that is, the source buses are formed in the shape of a ladder, and the source buses 19 and 26 are connected to each other by the connection line 33, and the source buses 19 and 26 are connected to each other by the connection line 33. By the way, the thin film transistors 16 and 25 are formed on both sides of the display electrode by the connection line 33. As a result, two thin film transistors can be provided without impairing the aperture ratio, and even if the source bus is disconnected at multiple locations, it is unlikely to become a defect, and even if one gate bus is disconnected, it will not be a defect.

However, even if the source bus 26 is omitted in FIG. 6 where the source bus is configured in a ladder shape,
A thin film transistor with uniform characteristics can be obtained without being affected by misalignment of masks. Furthermore, in this configuration, two thin film transistors are connected to both sides of one display electrode 15 and these are controlled simultaneously, but in addition, thin film transistors are connected not only to one opposing line of the display electrode but also to two opposing lines. In other words, four thin film transistors may be formed and these four may be controlled simultaneously. Further, in the above description, the transparent substrate 11 on which the thin film transistor is formed
In contrast, a semiconductor layer and a gate insulating film were formed and then a gate electrode was formed, but conversely, a gate electrode was formed on the transparent substrate side, a gate insulating film was formed thereon, and then a semiconductor layer was formed. The present invention can also be applied to a thin film transistor in which a source electrode and a drain electrode are formed thereon.
Furthermore, although the above example is applied to black and white display, the present invention can also be applied to color display.
The display electrode 15 is not limited to a pixel electrode, but may be a display electrode of other shapes, such as a display electrode of seven rod-shaped segments arranged in a figure eight shape to selectively display numbers.

"Effects of the Invention" As described above, according to the liquid crystal display element of the present invention, it is possible to easily obtain thin film transistors with the same characteristics in each part regardless of mask misalignment during manufacturing, and the parasitic capacitance C _gd , C _sg and parasitic resistance R _s are canceled out by each other because multiple thin film transistors are connected, and variations in the overall characteristics of thin film transistors per display electrode are extremely reduced, and display unevenness is reduced accordingly. .

Furthermore, even if there is such a geometrical deviation, the parasitic capacitance does not increase or decrease unilaterally, so when designing a thin film transistor, the channel width w can be increased to the maximum limit, and at the same time, the injection charge capacity of the thin film transistor can be kept at the design value. You can obtain products with similar characteristics.

Furthermore, as mentioned above, if two source buses are provided for each display electrode and connected to each other at both ends to form a loop, there is no risk of the liquid crystal display element becoming a problem even if one of the source buses is disconnected. This results in a higher yield with a lower defect occurrence rate. Similarly, if two gate buses are provided for each display electrode and their ends are connected to each other, a disconnection of one gate bus will not cause a defect.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing a liquid crystal display element according to the present invention, FIG. 2 is a plan view showing a part of the arrangement of thin film transistors and display electrodes, FIG. 3 is a cross-sectional view taken along line AA in FIG. 2, and FIG. The figure shows thin film transistor 1
6 and 25, FIG. 5 is a plan view corresponding to FIG. 2 showing another example of the liquid crystal display element of the present invention, and FIG. 6 is still another example of the liquid crystal display element of the present invention. FIG. 7 is a partial cross-sectional view of the general structure of a matrix liquid crystal display element, FIG. 8 is an electrical equivalent circuit diagram of a matrix liquid crystal display element, and FIG. 9 is a diagram of a conventional matrix liquid crystal display element. FIG. 10 is a plan view showing part of the arrangement of display electrodes and thin film transistors of a matrix liquid crystal display element, and FIG. 10 is a sectional view taken along the line BB of FIG. 8. 11, 12: transparent substrate, 14: liquid crystal, 15: display electrode, 16, 25: thin film transistor, 18,
31: Gate bus, 19, 26: Source bus.

Claims (1)

[Claims] 1. Two transparent substrates are disposed close to each other, liquid crystal is sealed between these transparent substrates, and rectangular display electrodes are formed in a matrix on the inner surface of one of the transparent substrates. A source bus is formed along both sides of each column arrangement of display electrodes, a gate bus is formed along each row arrangement of display electrodes, and one side of each display electrode and one side of the source bus near this are formed. A first thin film transistor having a drain electrode connected to one side of the display electrode, a source electrode connected to the source bus, and a gate electrode connected to the gate bus is formed between the first thin film transistor and the first thin film transistor. In a liquid crystal display element in which display electrodes are selectively displayed by switching control, a drain is connected to one side of each display electrode between the opposite side of the one side of each display electrode and the other side of the source bus close to this side. A second thin film transistor is formed in which an electrode is connected to the source bus, a source electrode is connected to the source bus, and a gate electrode is connected to the gate bus, and the second thin film transistor has the same dimensions, shape, and characteristics as the first thin film transistor. can be,
and the width of each channel is approximately half of the maximum channel width allowed for a thin film transistor when only one thin film transistor is connected to one display electrode, and both ends of the source buses on both sides are connected to each other. A liquid crystal display element characterized by: