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JPH0543281B2 - - Google Patents
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JPH0543281B2 - - Google Patents

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Publication number
JPH0543281B2
JPH0543281B2 JP62278643A JP27864387A JPH0543281B2 JP H0543281 B2 JPH0543281 B2 JP H0543281B2 JP 62278643 A JP62278643 A JP 62278643A JP 27864387 A JP27864387 A JP 27864387A JP H0543281 B2 JPH0543281 B2 JP H0543281B2
Authority
JP
Japan
Prior art keywords
laminate
internal electrode
electrode layer
center conductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62278643A
Other languages
Japanese (ja)
Other versions
JPH01120805A (en
Inventor
Munetoshi Futaho
Keisuke Kumano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP62278643A priority Critical patent/JPH01120805A/en
Publication of JPH01120805A publication Critical patent/JPH01120805A/en
Publication of JPH0543281B2 publication Critical patent/JPH0543281B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、各種の産業用、家庭用の電子、電気
機器及び通信機器から発生するノイズや、外部か
らこれらの機器内部に侵入するノイズを阻止する
ノイズフイルタとして用いるのに好適な複合型積
層貫通コンデンサの製造方法に関するものであ
る。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is intended to reduce noise generated from various industrial and household electronic, electrical and communication equipment, and noise that enters into these equipment from the outside. The present invention relates to a method for manufacturing a composite multilayer feedthrough capacitor suitable for use as a noise filter.

[従来の技術] 通信機器及びその他の電子機器等では、その小
形化、多機能化が進み、これに伴いIC、LSIなど
の半導体素止が多く利用されるようになつてきて
いる。しかるにこれらの機器は、機器外部から電
源線、信号線を通じて、或は空中伝播して侵入す
るノイズ等により誤動作したり、内部回路素子が
破壊される弱点をもつている。
[Background Art] Communication devices and other electronic devices are becoming smaller and more multifunctional, and as a result, semiconductor devices such as ICs and LSIs are increasingly being used. However, these devices have weaknesses such as malfunctions or destruction of internal circuit elements due to noise that enters from outside the device through power lines, signal lines, or propagates through the air.

また、パーソナルコンピユータやマイクロプロ
セツサを使用した制御機器では処理速度の高速化
に伴い、半導体素子の動作周波数がより高周波数
帯へと移行されつつあり、従来問題にならなかつ
た数百MHzにもおよぶ高周波ノイズが影響するよ
うになつてきている。
In addition, as the processing speed of personal computers and control equipment using microprocessors increases, the operating frequency of semiconductor devices is moving to higher frequency bands, and the operating frequency of semiconductor devices is moving to a higher frequency band, which has not been a problem in the past. high-frequency noise is becoming more and more influential.

従来、上記のような高周波ノイズを除去する場
合は、3端子形コンデンサやフエライトコアなど
の単体やそれらを組み合わせたフイルタを各信号
経路毎に実装していた。
Conventionally, in order to remove the above-mentioned high-frequency noise, a filter such as a three-terminal capacitor or a ferrite core or a combination thereof has been mounted for each signal path.

[発明が解決しようとする問題点] 上記のような従来の方式では、複数の信号経路
に各々フイルタを実装し、かつ各々のフイルタの
アース端子を回路基板のグランドパターンに接続
しなければならず、回路基板の配線設計が複雑と
なるほか、機器全体の小形化や薄形化が困難とな
り、コスト高になる問題があつた。
[Problems to be Solved by the Invention] In the conventional system as described above, a filter must be mounted on each of the plurality of signal paths, and the ground terminal of each filter must be connected to the ground pattern of the circuit board. In addition to complicating the wiring design of the circuit board, it also became difficult to make the entire device smaller and thinner, leading to higher costs.

また、3端子コンデンサなどのリード端子付き
ノイズ除去フイルタは、数百MHzの高周波帯域で
は、アース側リード線をいかに短く実装してもそ
の構造による残留インダクタンスが影響し、高周
波ノイズがバイパス効果を防げるため、充分なノ
イズ除去効果が得られない場合があつた。
In addition, for noise removal filters with lead terminals such as 3-terminal capacitors, in high frequency bands of several hundred MHz, no matter how short the ground lead wire is mounted, the residual inductance due to the structure will affect the high frequency noise, preventing the bypass effect. Therefore, there were cases where a sufficient noise removal effect could not be obtained.

なお、高周波ノイズを除去するのに極めて有効
な、残留インダクタンスが極めて小さい貫通コン
デンサを使用する場合、従来回路基板上に直接実
装し、その性能を有効に利用することは形状的制
約から困難であり、サブ基板や金属ケース等にあ
らかじめ取り付けた後、回路基板上に実装し、更
に半田ゴテで配線を半田付け接続する等の方式を
採用しており、取り付けが繁雑になり、機器全体
の大型化やコスト高を招いていた。
Furthermore, when using feed-through capacitors with extremely low residual inductance, which are extremely effective in removing high-frequency noise, it has traditionally been difficult to mount them directly on a circuit board and make effective use of their performance due to shape constraints. , a method such as attaching it to a sub-board or metal case in advance, mounting it on the circuit board, and then soldering the wiring using a soldering iron is adopted, which makes the installation complicated and increases the size of the entire device. This led to higher costs.

[問題点を解決するための手段] 本発明の複合型積層貫通コンデンサの製造方法
は、次のようにして行なわれる。
[Means for Solving the Problems] The method for manufacturing a composite multilayer feedthrough capacitor of the present invention is carried out as follows.

グリーンな誘導体層上に内部電極層を印刷し、
さらにこの内部電極層の上に誘電体層を積層して
内部電極層を印刷し、これを繰り返すことにより
誘電体層と内部電極層とが交互に積層された積層
体を製造する。
An internal electrode layer is printed on the green dielectric layer,
Furthermore, a dielectric layer is laminated on this internal electrode layer, the internal electrode layer is printed, and this process is repeated to produce a laminate in which dielectric layers and internal electrode layers are alternately laminated.

該積層体に厚さ方向に複数個の貫通孔を千鳥配
列にて穿設した後、該積層体の貫通孔の間の所要
部分を切断して積層体を所要の大きさに分割す
る。そして、切断された積層体を乾燥及び焼成す
ると共に、焼成された積層体に中心導体を挿入す
る。
After forming a plurality of through holes in the laminate in a staggered arrangement in the thickness direction, the laminate is divided into desired sizes by cutting the required portions between the through holes. Then, the cut laminate is dried and fired, and a center conductor is inserted into the fired laminate.

なお、上記切断工程、焼成工程及び中心導体挿
入工程のいずれかの工程の後に、積層体の少なく
とも側端面に外部電極層を形成する。また、前記
内部電極層は一層毎に前記中心導体と外部電極と
に交互に導通されるように前記積層体製造工程に
おいて印刷される。
Note that, after any one of the above-mentioned cutting step, firing step, and center conductor insertion step, an external electrode layer is formed on at least the side end surface of the laminate. Further, the internal electrode layers are printed in the laminate manufacturing process so that each layer is alternately electrically connected to the center conductor and the external electrode.

[作用] かかる本発明の積層型貫通コンデンサの製造方
法によれば、複数個のコンデンサの誘電体を共通
にして一体化できるから、全体として積層型貫通
コンデンサが小型化できる。従つて、本発明の複
合型積層貫通コンデンサの製造方法によれば、貫
通コンデンサを使用したノイズフイルタを、複数
個同時に回路基板上に高密度実装できる。
[Function] According to the method for manufacturing a multilayer feedthrough capacitor of the present invention, the dielectric of a plurality of capacitors can be made common and integrated, so that the multilayer feedthrough capacitor can be miniaturized as a whole. Therefore, according to the method for manufacturing a composite multilayer feedthrough capacitor of the present invention, a plurality of noise filters using feedthrough capacitors can be simultaneously mounted at high density on a circuit board.

[実施例] 以下図面を用いて本発明の実施例について詳細
に説明する。
[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の方法で製造される複合型積層
貫通コンデンサの一実施例を示す斜視図、第2図
は第1図−線に沿う断面図、第3図及び第4
図はそれぞれ第2図の−線及び−線に沿
う断面図である。
FIG. 1 is a perspective view showing an embodiment of a composite multilayer feedthrough capacitor manufactured by the method of the present invention, FIG. 2 is a sectional view taken along the line of FIG. 1, and FIGS.
The figures are sectional views taken along lines - and - in FIG. 2, respectively.

符号1は誘電体層と内部電極層とが交互に積層
された積層体であり、該積層体1には複数個(本
実施例では6個)の中心導体2が積層体1を厚み
方向に貫通して設けられている。積層体1の側端
面と両盤面には外部電極3が形成されている。
Reference numeral 1 denotes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and the laminate 1 has a plurality of (six in this example) center conductors 2 extending through the laminate 1 in the thickness direction. It is installed through. External electrodes 3 are formed on the side end faces of the laminate 1 and on both board faces.

第2〜4図に示す如く、積層体1は、誘電体層
4と内部電極層5とが交互に積層されたものであ
り、内部電極層5は1層毎に中心導体2と外部電
極3とに交互に導通している。以下、中心導体2
に導通する内部電極層を符号5aで示し、外部電
極3に導通する内部電極層を符号5bで示すこと
がある。
As shown in FIGS. 2 to 4, the laminate 1 has dielectric layers 4 and internal electrode layers 5 alternately laminated, and each internal electrode layer 5 has a center conductor 2 and an external electrode 3. They are alternately conductive. Below, center conductor 2
The internal electrode layer electrically connected to the external electrode 3 may be indicated by the symbol 5a, and the internal electrode layer electrically conductive to the external electrode 3 may be indicated by the symbol 5b.

内部電極層5aは、第3図に示す如く本実施例
では正方形状のものであり、中心導体2がその中
心を貫通して該中心導体2と導通する構成とされ
ている。この内部電極層5aは、従つて中心導体
2と同数個設けられている。
In this embodiment, the internal electrode layer 5a has a square shape as shown in FIG. 3, and the center conductor 2 passes through the center of the inner electrode layer 5a and is electrically connected to the center conductor 2. Therefore, the same number of internal electrode layers 5a as the center conductor 2 are provided.

内部電極層5bは、第4図に示す如く、中心導
体2の近傍部分を除き誘電体層4の全盤面を被う
ように設けられている。従つて、この内部電極層
5bは、中心導体2とは導通せず、その端縁部が
誘電体層4の端縁部にまで達し、ここにおいて外
部電極3と接合して導通されている。
As shown in FIG. 4, the internal electrode layer 5b is provided to cover the entire surface of the dielectric layer 4 except for the area near the center conductor 2. Therefore, this internal electrode layer 5b is not electrically connected to the center conductor 2, but its edge reaches to the edge of the dielectric layer 4, where it is joined to the external electrode 3 and electrically connected.

このように構成された複合型積層貫通コンデン
サにおいては、複数個のコンデンサの誘電体を共
通にして一体化した構造となつているから、全体
として小型である。従つて、この複合型積層貫通
コンデンサによれば、貫通コンデンサを使用した
ノイズフイルタを複数個同時に回路基板上に高密
度実装できる。
The composite multilayer feedthrough capacitor constructed in this manner has a structure in which a plurality of capacitors have a common dielectric material and are integrated, so the capacitor is compact as a whole. Therefore, according to this composite multilayer feedthrough capacitor, a plurality of noise filters using feedthrough capacitors can be simultaneously mounted at high density on a circuit board.

第5図は本発明の方法で製造される複合型積層
貫通コンデンサの別の実施例を示すの斜視図であ
る。本実施例においては、中心導体2が千鳥配列
にて配置されている。このように中心導体2を千
鳥配列することにより、中心導体2の配列ピツチ
pを第4図に示す複合型積層貫通コンデンサの1/
2にすることができ、より高密度に貫通コンデン
サを実装することができる。
FIG. 5 is a perspective view showing another embodiment of a composite multilayer feedthrough capacitor manufactured by the method of the present invention. In this embodiment, the center conductors 2 are arranged in a staggered arrangement. By arranging the center conductors 2 in a staggered manner in this way, the arrangement pitch p of the center conductors 2 can be reduced to 1/1 of the composite multilayer feedthrough capacitor shown in FIG.
2, and feedthrough capacitors can be mounted with higher density.

このような複合型貫通コンデンサは、本発明に
従つて、第6図ないし第8図に示す方法により製
造することができる。
Such a composite feedthrough capacitor can be manufactured according to the present invention by the method shown in FIGS. 6-8.

即ち、まずグリーンな状態にある誘導体層4上
に内部電極層5a又は5b(本実施例では5b)
を印刷する。そして、この内部電極層5bの上に
更にグリーンな状態にある誘導体層4を積層し、
第7図に示す如くこの新たに積層された誘導体層
4上に内部電極層5aを印刷する。これを繰り返
すことにより、誘電体層4と内部電極層5とが交
互に積層された積層体を製造する。
That is, first, an internal electrode layer 5a or 5b (5b in this embodiment) is placed on the dielectric layer 4 in a green state.
print. Then, a dielectric layer 4 in a green state is further laminated on this internal electrode layer 5b,
As shown in FIG. 7, an internal electrode layer 5a is printed on this newly laminated dielectric layer 4. By repeating this process, a laminate in which dielectric layers 4 and internal electrode layers 5 are alternately stacked is manufactured.

なお、第6図に示す如く、内部電極層5bを印
刷するに際しては、中心導体2を穿設する予定部
位に、中心導体の断面よりもやや大きな非印刷部
8が形成され、該電体層4が露出されるようにす
る。また、第7図に示す如く、内部電極層5a
は、その中心が前記非印刷部8の中心と一致する
ようにし、各内部電極層5a同志の間では所要の
間〓9を形成しておく。
As shown in FIG. 6, when printing the internal electrode layer 5b, a non-printed part 8, which is slightly larger than the cross section of the center conductor, is formed in the area where the center conductor 2 is planned to be drilled. 4 will be exposed. Further, as shown in FIG. 7, the internal electrode layer 5a
The center thereof is made to coincide with the center of the non-printed portion 8, and a distance 9 is formed between each internal electrode layer 5a for a required period.

このように積層体1を製造した後、第8図の如
く、該積層体1に厚さ方向に複数個の貫通孔6を
穿設する。この貫通孔6は前記非印刷部8の中心
を貫通するように穿設され、従つて第8図に示す
如く各貫通孔6は千鳥配列となるように設けられ
る。
After manufacturing the laminate 1 in this manner, a plurality of through holes 6 are bored in the laminate 1 in the thickness direction, as shown in FIG. The through holes 6 are formed so as to pass through the center of the non-printing portion 8, and therefore, the through holes 6 are provided in a staggered arrangement as shown in FIG.

しかる後、積層体1を、その貫通孔6の間の所
要部分に沿つて切断し、積層体1を所要の大きさ
に分割する。例えば切断線Aに沿つて切断する場
合には、前記した第1図ないし第4図に示す中心
導体を一列に配置した積層型貫通コンデンサが形
成される。また切断線Bの如く貫通孔6の2列毎
に切断を行なう場合には、前記第5図に示した中
心導体が千鳥配列された複合型積層貫通コンデン
サが製造される。
Thereafter, the laminate 1 is cut along the required portions between the through holes 6 to divide the laminate 1 into desired sizes. For example, when cutting along cutting line A, a multilayer feedthrough capacitor is formed in which the center conductors shown in FIGS. 1 to 4 are arranged in a row. Further, when cutting is performed every two rows of through holes 6 as indicated by cutting line B, a composite multilayer feedthrough capacitor in which the center conductors are arranged in a staggered manner as shown in FIG. 5 is manufactured.

切断された積層体は、乾燥及び焼成が施された
後、貫通孔6の内周面に導電層が塗布、印刷、メ
ツキ等により形成され、内部電極5a同志が接続
される。そして、この貫通孔6に中心導体2が導
入される。この後、積層体1の少なくとも側端面
に外部電極を印刷、塗布、メツキ等により形成す
ることにより本発明の積層型貫通コンデンサが完
成する。なお、外部電極を形成するに際し、積層
体の両盤面にも該外部電極を構成することによ
り、第1図ないし第5図に示す複合型積層貫通コ
ンデンサが製造される。
After the cut laminate is dried and fired, a conductive layer is formed on the inner peripheral surface of the through hole 6 by coating, printing, plating, etc., and the internal electrodes 5a are connected to each other. Then, the center conductor 2 is introduced into the through hole 6. Thereafter, external electrodes are formed on at least the side end surfaces of the laminate 1 by printing, coating, plating, etc., thereby completing the multilayer feedthrough capacitor of the present invention. When forming the external electrodes, the composite multilayer feedthrough capacitors shown in FIGS. 1 to 5 are manufactured by configuring the external electrodes on both surfaces of the laminate.

上記実施例においては、外部電極層が中心導体
2を挿入した後に形成されているが、積層体を切
断した後もしくは切断工程、焼成工程後に該外部
電極を形成しても良い。
In the above embodiment, the external electrode layer is formed after inserting the center conductor 2, but the external electrode layer may be formed after cutting the laminate, or after a cutting process or a firing process.

第1図及び第5図の如く積層体の盤面にも外部
電極を形成する場合には、中心導体を挿入するよ
りも以前に外部電極を形成するのが好適である。
When external electrodes are also formed on the board surface of the laminate as shown in FIGS. 1 and 5, it is preferable to form the external electrodes before inserting the center conductor.

本発明において、上記実施例の如く積層体の両
盤面にも外部電極を形成した場合には、複合ノイ
ズフイルタのアース型共通電極となる導電性のプ
レートを該外部電極に機能させることが可能であ
る。
In the present invention, when external electrodes are formed on both surfaces of the laminate as in the above embodiment, it is possible to make the external electrodes function as a conductive plate that becomes the ground type common electrode of the composite noise filter. be.

[効果] 以上の通り、本発明の複合型積層貫通コンデン
サの製造方法によれば、極めて小型で、複数個同
時に回路基板上に高密度実装することができる複
合型積層貫通コンデンサが容易かつ効率的に製造
される。
[Effects] As described above, according to the method for manufacturing a composite multilayer feedthrough capacitor of the present invention, a composite multilayer feedthrough capacitor that is extremely small and can be mounted simultaneously on a circuit board with high density can be easily and efficiently produced. Manufactured in

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の方法で製造される複合型積層
貫通コンデンサの一実施例を示す斜視図、第2図
は第1図−線に沿う断面図、第3図及び第4
図はそれぞれ第2図の−線及び−線に沿
う断面図である。第5図は本発明の方法で製造さ
れる複合型積層貫通コンデンサの別の実施例を示
す斜視図である。第6図及び第7図は本発明の複
合型積層貫通コンデンサの製造工程を示す斜視
図、第8図は同平面図である。 1……積層体、2……中心導体、3……外部電
極、4……誘電体層、5(5a,5b)……内部
電極層、6……貫通孔、8……非印刷部、9……
間〓。
FIG. 1 is a perspective view showing an embodiment of a composite multilayer feedthrough capacitor manufactured by the method of the present invention, FIG. 2 is a sectional view taken along the line of FIG. 1, and FIGS.
The figures are sectional views taken along lines - and - in FIG. 2, respectively. FIG. 5 is a perspective view showing another embodiment of a composite multilayer feedthrough capacitor manufactured by the method of the present invention. 6 and 7 are perspective views showing the manufacturing process of the composite multilayer feedthrough capacitor of the present invention, and FIG. 8 is a plan view thereof. DESCRIPTION OF SYMBOLS 1... Laminate, 2... Center conductor, 3... External electrode, 4... Dielectric layer, 5 (5a, 5b)... Internal electrode layer, 6... Through hole, 8... Non-printed part, 9...
Between.

Claims (1)

【特許請求の範囲】 1 グリーンな誘導体層上に内部電極層を印刷
し、さらにこの内部電極層の上に誘電体層を積層
してその上に内部電極層を印刷し、これを繰り返
すことにより誘電体層と内部電極層とが交互に積
層された積層体を製造する工程、 該積層体に厚さ方向に複数個の貫通孔を千鳥配
列にて穿設する工程、 該積層体の貫通孔の間の所要部分を切断して積
層体を所要の大きさに分割する切断工程、 切断された積層体を乾燥及び焼成する焼成工
程、 焼成された積層体に中心導体を挿入する中心導
体挿入工程、 上記切断工程、焼成工程及び中心導体挿入工程
のいずれかの工程の後に、積層体の少なくとも側
端面に外部電極層を形成する工程、 を有し、前記内部電極層は1層毎に前記中心導体
と外部電極とに交互に導通されるように前記積層
体製造工程において印刷されることを特徴とする
複合型積層貫通コンデンサの製造方法。
[Claims] 1. By printing an internal electrode layer on a green dielectric layer, further laminating a dielectric layer on this internal electrode layer, printing an internal electrode layer on top of this, and repeating this process. A step of manufacturing a laminate in which dielectric layers and internal electrode layers are alternately laminated, a step of drilling a plurality of through holes in the laminate in a staggered arrangement in the thickness direction, a through hole in the laminate. A cutting process in which the laminate is divided into required sizes by cutting the required portion between the laminates, a firing process in which the cut laminate is dried and fired, and a center conductor insertion process in which the center conductor is inserted into the fired laminate. , after any one of the cutting step, firing step, and center conductor insertion step, forming an external electrode layer on at least the side end surface of the laminate; A method for manufacturing a composite multilayer feedthrough capacitor, characterized in that the multilayer capacitor is printed in the step of manufacturing the multilayer body so that the conductor and the external electrode are alternately electrically connected.
JP62278643A 1987-11-04 1987-11-04 Composite laminated through-type capacitor and manufacture thereof Granted JPH01120805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62278643A JPH01120805A (en) 1987-11-04 1987-11-04 Composite laminated through-type capacitor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62278643A JPH01120805A (en) 1987-11-04 1987-11-04 Composite laminated through-type capacitor and manufacture thereof

Publications (2)

Publication Number Publication Date
JPH01120805A JPH01120805A (en) 1989-05-12
JPH0543281B2 true JPH0543281B2 (en) 1993-07-01

Family

ID=17600136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62278643A Granted JPH01120805A (en) 1987-11-04 1987-11-04 Composite laminated through-type capacitor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH01120805A (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2639139B2 (en) * 1989-11-27 1997-08-06 三菱マテリアル株式会社 Multilayer feedthrough capacitor array
US20030161086A1 (en) 2000-07-18 2003-08-28 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6603646B2 (en) 1997-04-08 2003-08-05 X2Y Attenuators, Llc Multi-functional energy conditioner
US7336467B2 (en) 2000-10-17 2008-02-26 X2Y Attenuators, Llc Energy pathway arrangement
US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US7274549B2 (en) 2000-12-15 2007-09-25 X2Y Attenuators, Llc Energy pathway arrangements for energy conditioning
US7301748B2 (en) 1997-04-08 2007-11-27 Anthony Anthony A Universal energy conditioning interposer with circuit architecture
CN1293831A (en) * 1998-01-19 2001-05-02 X2Y衰减器有限公司 Independent passive component structure with paired multi-layer dielectrics to generate differential and common mode filtering in one integrated assembly for surge protection
US7427816B2 (en) 1998-04-07 2008-09-23 X2Y Attenuators, Llc Component carrier
EP1312148A4 (en) 2000-08-15 2009-06-03 X2Y Attenuators Llc ELECTRODES SYSTEM FOR CIRCUIT ENERGY CONDITIONING
WO2005002018A2 (en) 2003-05-29 2005-01-06 X2Y Attenuators, Llc Connector related structures including an energy
WO2006099297A2 (en) 2005-03-14 2006-09-21 X2Y Attenuators, Llc Conditioner with coplanar conductors

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3538464A (en) * 1963-08-20 1970-11-03 Erie Technological Prod Inc Multiple pin connector having ferrite core stacked capacitor filter
JPS4882351A (en) * 1972-02-03 1973-11-02
JPS55124225A (en) * 1979-03-19 1980-09-25 Tdk Electronics Co Ltd Method of manufacturing dielectric porcelain laminated band
JPS595966U (en) * 1982-06-30 1984-01-14 石田 捷喜 Kyaday Batsugu
JPS5930520U (en) * 1982-08-21 1984-02-25 三菱電機株式会社 power generation equipment

Also Published As

Publication number Publication date
JPH01120805A (en) 1989-05-12

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