JPH0544229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse signal generating device suitable for a focusing device of a video camera, a special effects device, and the like.

If you want to automatically adjust the focus of your video camera,
A control signal for focus adjustment is obtained by extracting a portion of the video signal from the video camera and detecting the amount of high frequency components in the extracted video signal.

Furthermore, in special effects equipment, a technique is known in which a video screen is inserted by extracting a part of the video signal and replacing the extracted video signal with part of another video signal. .

In such technology, any extraction of a portion of the video signal corresponds to extraction of a portion of the video screen, and the portion of the video screen that is extracted must also be adjustable. Therefore, the gate pulse signal for extracting a portion of the video signal must have the same period as the periodic signal, and must be able to arbitrarily adjust the phase and pulse width.

In addition to the video equipment mentioned above,
Furthermore, there are devices other than video devices that require a pulse signal whose cycle matches that of a certain pulse signal and whose phase and pulse width are adjustable. In order to obtain such a pulse signal, conventionally, a pulse signal generating circuit is used which includes a time constant circuit for setting the leading edge of the pulse signal and a time constant circuit for setting the trailing edge of the pulse signal.

FIG. 1 is a block diagram showing an example of such a conventional pulse generation circuit, in which 1 is an input terminal, 2
is a monostable multivibrator circuit (hereinafter referred to as mono-multi), 3 is an inverter, 4 is a mono-multi,
5 is an output terminal, 6 is a power supply, 7 is a resistor, 8 is a capacitor, 9 is a resistor, and 10 is a capacitor.

FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and each signal is given the corresponding reference numeral in FIG. 1.

Next, the operation of this prior art will be explained.

In Figures 1 and 2, the period starts from input terminal 1.
The input pulse signal a of T _H is supplied to the monomulti 2, and the monomulti 2 is triggered by the rising edge of the input pulse signal a.

The monomulti 2 is connected to a power source 6 via a resistor 7, and a time constant circuit is formed by the resistor 7 and a capacitor 8 connected between one end of the resistor 7 and the ground terminal, making the resistor 7 variable. This allows the time constant to be adjusted.

However, the monomulti 2 has an input pulse signal a
The pulse width T _d is determined by the time constant of the time constant circuit of resistor 7 and capacitor 8.
A pulse signal b is generated.

Pulse signal b is inverted by inverter 3 to become pulse signal c, which triggers monomulti 4 at its rising edge.

The monomulti 4 is connected to a power supply 6 via a resistor 9, and a time constant circuit is formed by the resistor 9 and a capacitor 10 connected between one end of the resistor 9 and the ground terminal, making the resistor 9 variable. This allows the time constant to be adjusted.

However, the monomulti 4 rises in accordance with the rise of the pulse signal c, and the resistor 9 and capacitor 10
A pulse signal d having a pulse width _Tw determined by the time constant of the time constant circuit is generated.

The rising edge of this pulse signal d is the input signal a.
It is a pulse signal with _a pulse width _Tw delayed by _Td from the rising edge _of The input pulse signal a of the pulse signal d obtained at the output terminal 5 is determined by the time constant of the time constant circuit.
The phase T _d and pulse width T _w can be arbitrarily set by changing the resistors 7 and 9.

By the way, when such a pulse signal generation circuit is incorporated into a single-chip integrated circuit (hereinafter referred to as an IC), a time constant circuit whose time constant can be adjusted must be provided in each of the monomultis 2 and 4. Since the adjustable circuit cannot be incorporated into the IC, the IC must use two pins for such a pulse signal generation circuit.

In general, when converting into an IC, one pin is allocated to one circuit at most, and as many circuits as possible are incorporated to make the IC multi-functional.
Although we are trying to integrate the above conventional pulse generation circuit into an IC, we need two pins, so since the number of IC pins is fixed, we have to integrate only one circuit. must be reduced. Furthermore, when incorporating a predetermined number of circuits to provide a predetermined function, the conventional pulse generation circuit described above requires two pins, making it necessary to configure an IC using a package with an unnecessarily large number of pins. This may lead to increased costs.

In short, the above-mentioned conventional technology is capable of increasing the functionality of ICs,
It has the disadvantage of hindering integration and increasing costs.

The present invention eliminates the drawbacks of the prior art described above, and provides a pulse signal generation circuit that makes it possible to vary the phase and pulse width of a pulse signal using a single adjustment means, and is therefore suitable for IC implementation.

In order to achieve this object, the present invention changes the discharge start timing of a single charging/discharging circuit whose charging time constant is adjustable according to the time constant, and changing the charging voltage from the charging/discharging circuit. The present invention is characterized in that the pulse signal is formed based on the pulse signal.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the pulse generating circuit according to the present invention, in which 13 is an input terminal;
14 is an RS flip-flop circuit (hereinafter referred to as FF), 15 is a switching circuit, 16 and 17 are voltage comparison circuits, 18 is an output terminal, 19 is a power supply, 20
is a resistor, and 21 is a capacitor.

FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, and each signal is given the corresponding reference numeral in FIG. 3.

Next, the operation of this embodiment will be explained.

In FIGS. 3 and 4, an input pulse signal a having a period T _H from the input terminal 13 is supplied to the set terminal S of the FF 14, and the FF 14 is set at the rising edge of the input pulse signal a. When the FF 14 is set, the switching circuit 15 is turned off by the output signal of the FF 14.

Therefore, a charging current flows into the capacitor 21 from the power supply 19 through the resistor 20, and a charging voltage b is generated across the capacitor 21. Therefore,
A charging/discharging circuit is formed by the resistor 20 and the capacitor 21, the charging time constant of which is determined by the resistor 20 and the capacitor 21, and the charging time constant can be adjusted by configuring the resistor 20 or the capacitor 21 to be variable. It's getting old.

The charging voltage b of the charging/discharging circuit is supplied to the voltage comparison circuit 16 and compared with the reference voltage V _TH1 , and is also supplied to the voltage comparison circuit 17 and compared with the reference voltage V _TH2.
(However, V _TH2 < V _TH1 ).

The voltage comparison circuit 16 has a charge voltage b as a reference voltage.
V _TH1 or more, the output voltage changes from high level to low level, for example, and this output voltage is FF1
It is supplied to the reset terminal R of No. 4 and resets the FF 14 at the time of level change. As a result, the switching circuit 15 is turned on, and the charging/discharging circuit consisting of the resistor 20 and the capacitor 21 discharges via the switching circuit 15.

Next, when the FF 14 is set by the input pulse signal a, the switching circuit 15 is turned off and the charging/discharging circuit starts charging.

In this way, the sawtooth voltage across the capacitor 21 rises according to the time constant of the resistor 20 and the capacitor 21, and falls when the switching circuit 15 is turned on, that is, when the level of the output voltage of the voltage comparison circuit 16 changes. A charging voltage b is obtained.

Therefore, the charging voltage b is compared with the reference voltage V _TH2 in the voltage comparison circuit 17, and the charging voltage b is compared with the reference voltage V _TH2.
Pulse signal c that becomes high level when
is generated.

By the way, the phase difference T _d of the pulse signal c with respect to the input pulse signal a is such that the charging voltage b is the reference voltage V _TH2
is equal to the time it takes to reach , and also the pulse width
T _w is charging voltage b from reference voltage V _TH2 to reference voltage
It is equal to the time required to reach V _TH1 , and these times are determined by the time constants of the resistor 20 and the capacitor 21, so the resistor 20 or the capacitor 2
1, the pulse signal c obtained from the output terminal 18 can have variable phase T _d and pulse width T _w with respect to the input pulse signal a.

However, in this embodiment, the only component to be adjusted is the charging/discharging circuit consisting of the resistor 20 and the capacitor 21. Therefore, in this embodiment, by implementing an IC, it is sufficient to connect the charging/discharging circuit using the connection point 22 as a pin, and only one pin is assigned.

FIG. 5 is a circuit diagram showing a specific example of FIG. 3, and parts corresponding to those in FIG. 3 are given the same reference numerals.

In the figure, FF14 includes transistors Q ₁ ,
Q ₂ and IIL (abbreviation for Injection Integrated Logic)
The bases _{of the} transistors _{Q1 and Q2} constitute the reset terminal R and the set terminal S of the FF 14, respectively. In addition,
IIL can be constructed on the same chip as a standard bipolar IC, and the circuit configuration shown in FIG. 3 can be easily realized.

When the input pulse signal a (FIG. 4) is supplied from the input terminal 13 to the set terminal S of the FF 14, the output level of the inverter _G3 becomes low level. For this purpose, the transistor of the switching circuit 15
_Q3 is turned on and capacitor 21 starts charging.

The voltage comparison circuit 16 includes resistors R ₁ , R ₂ , R ₃ , R ₄ ,
It consists of R ₅ , R ₆ , R ₇ , transistor Q ₄ and differentially connected transistors Q ₅ and Q ₆ . Resistance _R5 ,
R ₆ and R ₇ set reference voltages V _TH1 and V _TH2 (Fig. 4) at points P ₁ and P ₂ , respectively. Reference voltage V _TH1 at point P ₁
is V _TH1 = V _CC · R ₆ + R ₇ / R ₅ + R ₆ + R ₇ , and the reference voltage V _TH2 at point P ₂ is V _TH2 = V _CC · R ₆ / R ₅ + R ₆ + R ₇ . However, V _CC is the power supply voltage.

Therefore, the charging voltage b4 of the capacitor 21 (the fourth
) is supplied to the base of transistor _Q5 , and when the charging voltage b exceeds the reference voltage V _TH1 , the transistor
_Q5 is turned on and transistor _Q6 is turned off. For this reason, the collector of transistor Q ₆ rises to the power supply voltage V _CC and transistor Q ₄ is turned off, and the potential of the collector of transistor Q ₄ becomes zero volts. This zero volt voltage is supplied as a reset signal to the reset terminal R of FF14, that is, to the base of transistor _Q1 ,
Set the output level of inverter _G2 to high level.
Therefore, the transistor _Q3 of the switching circuit 15 is turned on, and the capacitor 21 is rapidly discharged via the transistor _Q3 .

However, for every cycle T _H of input pulse signal a (Fig. 4), one cycle of sawtooth charging voltage b (fourth
) is generated and supplied to the voltage comparator circuit 17.

The voltage comparator circuit 17 consists of resistors R ₈ and R ₉ and differentially connected transistors Q ₇ and Q ₈ ,
Voltage comparator circuit 16 is connected to the base of transistor _Q8 .
A reference voltage V _TH2 occurring at point P ₂ in the middle is supplied, and the collector of transistor Q ₈ is connected to the output terminal, 8.

Therefore, the sawtooth charging voltage b (Fig. 4) from the capacitor 21 is supplied to the base of the transistor _Q7 , and when the charging voltage b exceeds the reference voltage V _TH2 , the transistor _Q7 is turned on and the transistor
_Q8 is in the off state.

Therefore, the potential at the collector of transistor _Q8 rises to a high level. During the period when the charging voltage b supplied to the transistor _Q7 is equal to or higher than the reference voltage _VTH2 , the potential of the collector of the transistor is at a high level.
Therefore, a pulse signal c (FIG. 4) having a pulse width T _w equal to the above period is obtained at the output terminal 18.

By changing the resistor 20 or the capacitor 21, the slope of the rise of the charging voltage b can be changed, and in the voltage comparison circuit 16, the charging voltage b and the reference voltage V _TH1 for the input pulse signal a can be changed. Since it is possible to change the point of coincidence, and therefore the falling point of the charging voltage b, the phase T _d and pulse width T _w of the pulse signal c obtained from the output terminal 18 with respect to the input pulse signal a can be changed.
can be changed by changing the resistor 20 or capacitor 21.

In this way, the charging/discharging circuit consisting of the resistor 20 and capacitor 24 to be adjusted is connected via the connection point 22, and the number of pins required for IC implementation is only one.

As explained above, according to the present invention, a charging/discharging circuit with an adjustable charging time constant is used, the charging start point of the charging/discharging circuit is controlled by an input pulse signal, and the charging start point is set to Since the pulse signal is formed based on the charging voltage from the charging/discharging circuit, the phase and pulse width of the pulse signal with respect to the input pulse signal are changed according to the charging voltage. Can be changed by adjusting the discharge circuit,
Moreover, one charge/discharge circuit is sufficient as an adjustment circuit for setting the phase and pulse width, and only one pin is allocated for IC implementation, which eliminates the drawbacks of the prior art described above. A pulse signal generation circuit with excellent functionality can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional pulse signal generation circuit, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is an example of a pulse signal generation circuit according to the present invention. FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, and FIG. 5 is a circuit diagram showing a specific example of FIG. 3. 13...Input terminal, 14...RS flip-flop circuit, 15...Switching circuit, 16...Voltage comparison circuit, 17...Voltage comparison circuit, 18...Output terminal.

Claims (1)

[Scope of Claims] 1. A pulse signal generation circuit for obtaining a pulse signal having the same period as an input pulse signal and variable in phase and pulse width, comprising: a charging/discharging circuit; and a set terminal receiving the periodic input pulse signal. a flip-flop circuit that is input and set; a switching circuit that is controlled by the output of the flip-flop circuit and controls charging and discharging of the charging and discharging circuit; and a charging and discharging voltage of the charging and discharging circuit and a predetermined reference voltage.
a first voltage comparison circuit that compares VTH1 with the charging/discharging voltage of the charging/discharging circuit and a predetermined reference voltage;
a second voltage comparison circuit for comparing VTH2 (<VTH1), the output voltage of the first voltage comparison circuit is input to the reset terminal of the flip-flop circuit, and from the second voltage comparison circuit, A desired pulse signal is obtained, and the timing of the leading edge of the desired pulse signal is determined based on the comparison timing between the charging and discharging voltage and the reference voltage VTH2, and the timing of the leading edge of the desired pulse signal is determined by comparing the charging and discharging voltage with the reference voltage VTH1. A pulse signal generating circuit characterized in that the timing of the trailing edge of the desired pulse signal and the reset timing of the flip-flop circuit are determined based on the comparison timing.