JPH0544759B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory element circuit and a microcomputer using the same, and in particular to an EPROM
The present invention relates to a memory element circuit suitable as a (Erasable and Programmable ROM) circuit and a microcomputer using the same.

[Background of the invention]

The conventionally used EPROM circuit and detection circuit have a configuration as shown in FIG.

In FIG. 1, 1 is a memory matrix, 2
1 is a memory element, 3 is a column selection circuit, 10 is a detection circuit, and 100 is a write circuit.

The nonvolatile memory element 2 constituting the memory matrix 1 stores "1" or "0" information depending on whether charge is injected into the floating gate by writing. To delete this information,
This is done using ultraviolet light, etc.

First, when writing information to the memory element 2, 0V is applied as a WE (write enable) signal to the gate of the transistor Tr20 provided between the detection circuit 10 and the column selection circuit 3, and the column selection signal is A high voltage (for example, 21 V) is applied to the line Yi and the word line Xj, and a voltage several volts lower than the above-mentioned high voltage is applied to the common data line B via the write circuit 100. As a result, current flows through the channel of the desired memory element 2 selected by the signal line Yi and word line Xj, and charges flow into the floating gate.

Memory matrix 1 has (n+1) rows (m+
1) It is composed of memory elements 2 in columns, and the gates of the memory elements 2 are connected to word lines that commonly connect the rows.
Xj (j = any value from 0 to n) is connected to the drain of memory element 2, and the data line that connects the columns in common
Di (i=any value from 0 to m) are connected to each other, and the source of the memory element 2 is grounded. Further, the data line Di (i=0 to m) is connected to the common data line B via column selection transistors T _y0 to _{T yn} .
is connected to point A of the detection circuit 10 via the transistor Tr20.

The potential at point A is input to point A, and the threshold value is
Inverter 4 with V _LT1 and this inverter 4
nMOS transistor Tr controlled by the output of
1 is connected.

When reading the memory information of each memory element 2, it is determined whether the threshold value Vth _M of the memory element 2 is high or low. When Vth _M is low, it is around 1V, and when it is high, VCC
It is more than the voltage value. Therefore, in the case _of a low threshold value _{Vth M0} , when the voltage of the word line Even when the voltage of word line Xj reaches the VCC voltage level, it does not become conductive. Detection of threshold value Vth _M of memory element 2 is as follows:
It is determined by the output OUT of the detection circuit 10, and the SA signal is applied to the gate of the load transistor Tr10.
Detection is started when the transistor Tr10 is turned on. Now, the selected memory element 2 is at the position M(j, i), and its state is the low threshold.
In the case of Vth _M0 , the voltage at point E, which is determined by the resistance division of the on-states of transistors Tr10, Tr1, Tr20, Tyi and memory element 2 connected in the same column in the current path, is determined by the inverter 6 having a threshold value V _LT3 . By detecting this, a high level voltage is applied to the output OUT. Further, when the state of the selected memory element 2 is the high threshold value Vth _M1 , the selected memory element 2 is not conductive, and the above-mentioned transistor Tr1
Since the path passing through 0, Tr1, Tr20, Tyi and memory element 2 is cut off, the potentials of data line Di, common data line B, point A, and point E begin to rise toward the VCC voltage. At this time, when the potential at point A reaches the threshold V _LT1 of the inverter 4, the voltage applied to the gate of the nMOS transistor Tr1 is inverted and becomes low level, so that the voltage applied to the gate of the nMOS transistor Tr1 is
is cut off. This allows the data line Di,
The potentials of the common data lines B and A are respectively fixed at the potential of the threshold V _LT1 , but since the potential of the E point continues to be charged from the VCC power supply through the transistor Tr10, it reaches the threshold V _LT3 of the inverter 6.
An inverted low level potential is applied to the output OUT.

Note that since the load capacity at point E is small, the potential at point E rises rapidly. In this way, memory information is detected by setting the threshold value V _LT3 of the detection inverter 6 to an intermediate value between the VCC voltage and the threshold value V _LT1 .

Although the conventional EPROM circuit shown in FIG. 1 does not require a timing clock, it has the following drawbacks.

(i) The potentials at points A and E indicate whether the memory element 2 read last time has a high threshold value Vth _M1 or a low threshold value.
Vth _M0 , the memory access time changes depending on its initial state. That is, the memory access time differs depending on the difference in the pair of the previous read value and the current read value (0, 0) (0, 1) (1, 0) (1, 1). For example, the previous “1” information (charge is injected into the floating gate of memory element 2)
When reading out "0" information (a combination of 1 and 0), the precharged charge remains in the stray capacitance of the data line Di, so this charge is first transferred to the memory element 2. M.O.S.
It is necessary to extract it through the . After that, the memory information is read, so access and
Time becomes longer. In contrast, last time “1”
When reading "1" information next after reading "1" information (a combination of 1 and 1), a current path is not formed, so there is no need to remove the charge precharged in the stray capacitance, and In a short time, the potential at point A becomes the threshold V _LT1 and the potential at point E becomes the threshold V _LT3
access time is reduced.
In the case of other combinations (0, 0) (0, 1), no precharging is performed, so the access time is approximately between the former and the latter. In this way, there is a drawback that there is a difference in operating speed each time a read is performed.

(ii) When reading memory information with a low threshold value Vth _M0 , a through current flows, so power consumption is large. The threshold value of the currently selected memory element 2
When Vth _M is high, the memory access time is determined by the current supply capability of the load transistor Tr10. In other words, the time required to charge the data line Di and the common data line B, which have a large capacity, to the threshold value V _LT1 of the inverter 4 is the memory access time. On the other hand, when the threshold value Vth _M of the memory element 2 is low, the memory access time is such that the charges on the data line Di and the common data line B are discharged through the memory element 2 while a constant current flows from the load transistor Tr10. It depends on the time you do it. Therefore, it is good for high threshold Vth _M1 , but for low threshold
In the case of Vth _M0 , a through current flows and power consumption increases.

[Purpose of the invention]

The purpose of the present invention is to solve these conventional problems,
An object of the present invention is to provide a memory element circuit that can always operate at high speed and with low power consumption without causing any difference in operating speed, and a microcomputer using the same.

[Summary of the invention]

In order to achieve the above object, the memory element circuit of the present invention includes a static detection circuit, receives the potential of the common data line as input, and is controlled by a second inverter having a threshold higher than the threshold of the first inverter. The present invention is characterized in that it includes a transistor for connecting the transistor and the detection means of the detection circuit to a power source. Furthermore, it has a precharge transistor for connecting the common data line and the detection means of the detection circuit to a power supply, and the common data line and the data line are set to a voltage value determined by charge distribution between the common data line and the data line. It is characterized by initial settings.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of an EPROM circuit showing one embodiment of the present invention.

FIG. 2 shows an example in which an ultraviolet erasable EPROM is used as the memory element 2.

The memory matrix 1 is composed of memory elements 2 arranged in (n+1) rows and (m+1) columns, as in FIG. A word line Xj is connected to the gate of the memory element 2, a data line Di is connected to the drain electrode of the memory element 2, and the source electrode is grounded. The first difference in FIG. 2 compared to the first conventional circuit is that the conventional detection circuit 10:
This is because a circuit has been added to quickly set the precharge voltage to an intermediate value. That is, the detection point E is connected to the power supply VCC via the precharge transistor Tr2, and the point A is
It is connected to the power supply VCC via a transistor Tr3 controlled by an inverter 5 having a threshold value V _LT2 for inputting the A point voltage and a precharge transistor Tr4. In this case, the relationship between the logical thresholds V _LT1 and V _LT2 of inverters 4 and 5 is expressed as V _LT1 <
Set it to be V _LT2 .

The second difference from the conventional circuit shown in FIG. 1 is that the charging circuit starts charging almost simultaneously with column selection operation, that is, the operation of column selection transistors T _y0 to _T Charging is completed before the voltage is applied to X ₀ to X _o . As a result, the direct current path between the two power sources of the memory circuit is completely cut off, and the memory circuit is operated using only the charging current to the parasitic capacitance of the circuit, so that operation with low power consumption is possible.

The third difference from the conventional circuit shown in FIG. 1 is that the data line Di connected to the memory element 2 is connected to the common data line B via the data line selection transistor T _yi (T _y0 to _{T yn} ). At the same time, the data line Di is grounded via other transistors T _yi (T _y0 to _{T yn} ). The above transistor T _yi
A Yi (Y ₀ to _{Y n} ) signal, which is an inverted signal of the word line selection signal Yi (Y ₀ to Y _n ) input to the gate of the transistor T _yi , is input to the gate of the transistor T yi.
As a result, the previously charged charge can be definitely discharged the next time to set the initial condition.

As in FIG. 1, the common data line B is connected to point A of the static detection circuit 10 via a voltage limiting transistor Tr20, and when the voltage at point A is input, an inverter with a threshold value V _LT1 is connected. Point A and point E are connected via transistor Tr1 controlled by transistor Tr1.

In addition, in the embodiment shown in FIG.
The EPROM detection circuit 10 is used as it is, and this circuit is equipped with an inverter 5, three transistors Tr2,
By simply adding Tr4 and Tr5, it can be used as a dynamic EPROM. That is, in this embodiment, the clock φ ₁ that drives the microcomputer is used as an EPROM built in the microcomputer.
It is basically configured as a static circuit that can operate in synchronization with _φ2 and can also operate as a single memory. This makes expensive dedicated
It is extremely convenient because it eliminates the need for an EPROM writer and can be used both as an EPROM dedicated to a microcomputer and as a stand-alone EPROM.

FIG. 3 is a read operation time chart of the circuit of FIG. 2.

As is clear from FIG. 3, when the circuit shown in FIG. 2 is built into a microcomputer, it operates in synchronization with the non-overlapping two-phase clocks φ ₁ and φ ₂ that drive the microcomputer, and By using the precharge method, it operates with SA signals disabled.

In Figure 3, ADR is at a predetermined position M(j,i)
PC is a memory address signal that generates Xj and Yi signals for selecting memory element 2, and PC is a precharge signal.

First, the precharge signal PC is set to a low level in synchronization with the clock _φ1 (when used as a single memory, there are no clocks _φ1 and _φ2 , so the precharge signal PC is not synchronized). At the same time, the word lines X ₀ to X _o are set to low level during the falling to rising period (φ ₂ ) of the clock φ ₂ . The period of clock _φ2 is wider than the precharge signal PC and covers PC. On the other hand, one of the column selection transistors T _y0 to _{T yn} is selected following the input of the address (ADR). In other words, the transistor controlled by the selection signal Yi
T _yi turns on (turns on at time h). Now, assuming that the Y ₀ signal is selected and becomes high level, the transistor T _y0 is on and the transistor
T _y1 ~ _{T yn} are off, and transistor T _y0 is off,
T _y1 to _{T yn} are turned on. Only the data line D ₀ is connected to the common data line B, and the other data lines D ₁ ~
D _n is grounded via transistors T _y1 to _{T yn} . Precharge signal PC is PMOS transistor
By applying it to the gates of Tr4 and Tr2,
From the VCC power supply voltage, point A is precharged via transistors Tr4, Tr3 and Tr2, Tr1, common data line B is precharged via transistor Tr20, and data line _D0 is further precharged via transistor T _y0 . (At the time of Figure 3a). As a result, the precharge voltages at point A, common data line B, and data line _D0 rise to the logic threshold voltage _VLT2 of inverter 5 (for example, 1.5V). When the V _LT2 voltage is reached while rising from OV to the VCC voltage, the output of inverter 5 is inverted and the low level voltage is applied to the nMOS transistor.
Since the voltage is applied to the gate of Tr3, the transistor Tr3 is turned off (at the time of FIG. 3b). On the other hand, at detection point E, the voltage is increasing from OV to VCC voltage.
The output of inverter 4 is inverted by the V _LT1 voltage, and the nMOS
Since the transistor Tr1 is turned off, the voltage at the detection point E where the load capacitance is small rapidly rises to the VCC voltage (at the time c in FIG. 3). In this way, A
point, common data line B, data line D ₀ to V _LT2 voltage,
Further, point E is precharged to the VCC voltage.

In synchronization with the falling edge of clock _φ1 (not synchronized when used alone), precharge signal PC
When this is completed (time point d in FIG. 3), word line Xj is selected in synchronization with clock φ ₂ (time point e in FIG. 3), and detection is started at detection point E. When Vth _M of memory element 2 is low, memory element 2
Since a current flows through, the voltages at point A, common data line B, and data line _D0, which are held at the _VLT2 voltage by precharging, begin to drop (at the time of FIG. 3 f). On the way down towards OV,
When the voltage reaches V _LT1 , inverter 4 is inverted and transistor Tr1 is turned on, so the voltage at detection point E, which was held at VCC voltage, suddenly drops to V _LT1.
The voltage drops to a nearby voltage (time point g in Figure 3). E
When the voltage at the point is determined to be the voltage V _LT1 , it is lower than the threshold value V _LT3 of the inverter 6, so an inverted high-level voltage is applied to the detection output OUT. Thereafter, the voltage at point E falls following point A, common data line B, and data line _D0 until it is precharged again.

On the other hand, the selected memory element 2 has a high threshold value Vth _M1
(Vth _M1 > VCC), since memory element 2 is not conductive, point A, common data line B, and data line
The voltages at D ₀ and detection point E continue to be held at the precharge voltage. The threshold value V _LT3 of detection inverter 6 is
Since it is set between the VCC voltage and the threshold voltage V _LT1 , after setting the precharge signal PC to high level,
If the time required for the voltages at point A, common data line B, and data line _D0 to reach the threshold value _VLT1 has elapsed, the output OUT of the inverter 6 can be used as a detection result for the threshold value of the memory element 2.

In this way, when built into a microcomputer, it can be operated in synchronization with the clocks _φ1 and _φ2 , and the SA (static sense)
Amplifier active) signal input is prohibited (3rd
(See the SA solid line in the figure), input the PC (precharge) signal.

On the other hand, when the EPROM shown in Figure 2 is used as a single memory, the SA signal is activated without synchronizing with the clock signals φ ₁ and φ ₂ (see the SA dashed line in Figure 3) since there are no clock signals φ 1 and φ 2. , prohibit PC signal. Selection lines Xj and Xi are address input
Static detection is performed by making the signal SA change in accordance with ADR and activating the signal SA that controls the gate of the load transistor Tr10. When the selected memory element 2 has a low threshold value Vth _M0 , the voltage at the detection point E is the voltage of the transistor Tr1,
The voltage is determined by Tr20, Tyi, and the series resistance division ratio between the memory element 2 and the load transistor Tr10. Also, the selected memory element 2 has a high threshold value.
In the case of Vth _M1 , since the memory element 2 is not conductive, the voltage at the detection point E becomes the VCC voltage.

In this way, in the EPROM circuit of the embodiment shown in FIG. 2, all the signals on the word line Xj are set to 0,
Only the signal of the data selection line Yi is determined in synchronization with the address ADR, and the PMOS transistor Tr2,
Since Tr4 and Tr10 cut off the DC current path,
No direct current flows from the VCC power supply to the ground of the memory element 2. Therefore, it can be operated with low power consumption. In addition, the precharge signal
By adding PC, the voltage at the detection point E increases to a predetermined value in a short time, and the charge previously charged to the data line Di is discharged via the transistor Tyi, so the value read last time is used. Therefore, the next access time does not change and is always constant.

Furthermore, it is extremely convenient because it can be built into a microcomputer and operated in synchronization with a clock, or it can be used as a standalone memory.

FIG. 4 shows a second embodiment of the invention.
5 is a configuration diagram of an EPROM circuit, and FIG. 5 is a read operation time chart of FIG. 4.

In FIG. 4, memory matrix 1 is
The word line Di of the column selection circuit 3 is the same as shown in the figure, and the word line Di of the column selection circuit 3 is connected to the data line selection transistor Tyi (T _y0 ~
T _yn ) to the common data line B. The first difference from the EPROM circuit shown in FIG. 2 is that the data line selection transistor Tyi and the data line
Di is grounded via a discharge transistor Tdi (T _d0 to T _dn ) controlled by a discharge signal DC, and a capacitor is connected to the common data line B.
C _B (parasitic capacitance between common data line B and point A may be used)
is connected. The second point is that the transistor Tr controlled by the inverter 4
1 is connected, and the inverter 5 shown in FIG. 2 is removed.

In other respects, the common data line B is connected to point A of the static detection circuit 10 via the voltage limiting transistor Tr20, as in FIG. In addition, point A is connected to VCC through a precharge transistor Tr3 controlled by a precharge signal PC.
It is connected to a power supply and to a detection point E via a transistor Tr1 which receives the voltage at point A and is controlled by an inverter 4 having a threshold value _VLT1 . Also, point E is the precharge transistor
Connected to the VCC power supply voltage via Tr2.

The EPROM circuit shown in FIG. 4 can also be built into a microcomputer and operate in synchronization with the clocks φ ₁ and φ ₂ that drive the computer.
It can operate statically as a single unit.

Also, as is clear from Xj and Yi in FIG. 5, contrary to the circuit operation in FIG. 2, when precharging, the signal on the column selection line Yi is set to 0, and the signal on the word line Xj is set to 0. Synchronize and confirm.

First, in synchronization with clock _φ1 , point A and common data line B are precharged by precharge signal PC, and data lines _D0 to _Dn are simultaneously discharged. At that time, during the period of φ ₂ from the falling edge of the clock φ ₂ to the next rising edge, the column selection lines Y ₀ to _{Y n}
all to low level. The period of φ ₂ has a wider time width than the PC signal and the DC (discharge) signal, and covers these signals. On the other hand, as described above, only one word line Xj is selected following the address ADR.

In this state, the common word line B, point A and detection point E are connected to the precharge transistor Tr3,
Precharged to VCC voltage by Tr2. Furthermore, data lines D ₀ to D _n are connected to transistors T _d0 to
All are discharged by T _dn . As a result, the previously charged charges are wiped out, so the initial conditions are fixed, and the access time always maintains a constant value. When the precharge and discharge are completed (at the time of FIG. 5d), the column selection line Yi is selected in synchronization with the clock _φ2 (at the time of FIG. 5e), and detection is started.

At this time, the voltage at the common data line B and point A, which has increased to the VCC voltage due to precharging, is determined by the total capacitance C _B of the common data line B and point A, and the capacitance division of the data line capacitance C _Di as shown below. The voltage suddenly drops to the voltage (point of time f in FIG. 5).

Vs=C _B /C _B +C _di・VCC ...(1) Here, the threshold value V _LT1 of inverter 4 is set as V _LT1 <Vs
When the selected memory element 2 is set to a low threshold value Vth _M0 (Vth _M0 < VCC), the memory element 2 becomes conductive. Therefore, assuming that the data line D ₀ is currently selected, The voltages of the data line D ₀ , the common data line B, and the point A further decrease toward OV (see FIGS. 5A and 5B). At this time, when the threshold voltage V _LT1 of the inverter 4 is reached (time point r in Fig. 5), the inverter 4 is inverted, and the transistor Tr1
is turned on, the voltage at the detection point E rapidly drops to the vicinity of the V _LT1 voltage (time point q in FIG. 5), and thereafter changes to follow the voltage at the point A until it is precharged.

On the other hand, the selected memory element 2 has a high threshold value Vth _M1
In the case of (Vth _M1 > VCC), since the memory element 2 is not conductive, the data line Di, the common data line B,
Point A is held at a voltage Vs determined by capacitance division (level indicated by s in FIG. 5). As is clear from FIG. 5, this voltage Vs is the threshold value of the inverter 4.
Since it is higher than V _LT1 , the output of the inverter 4 is not inverted and the transistor Tr1 remains off, so the voltage at the detection point E continues to be held at the VCC voltage. Threshold value V _LT3 of detection inverter 6 is set to VCC~
By setting between V _LT1 , the threshold state of the selected memory element 2, that is, the memory information can be detected.

The above is for the case where it is built into a microcomputer and uses the pre-charge method, so SA
Signaling is prohibited (see solid line in Figure 5 SA).

Next, in order to perform a static operation compatible with a single EPROM, the precharge signal PC and the discharge signal DC are inhibited, and the word line Xj and column selection line Yi are changed in accordance with the address input ADR. Also, the SA signal is enabled and applied to the gate of the load transistor Tr10 (see the broken line in SA in FIG. 5).

In this way, in the EPROM circuit of the embodiment shown in FIG. 4, all the signals on the data selection line Yi are set to 0, only the signal on the word line Xj is determined in synchronization with the address ADR, and the PMOS transistors Tr3 and
Since Tr2 and Tr10 cut off the DC current path,
No direct current flows, allowing operation with low power consumption. In addition, the precondition is to charge the capacitor C _B , and after increasing the voltage at the detection point E by precharging, it rapidly decreases to the voltage determined by the charge share when the signal from the data selection line Yi is applied. Therefore, it is possible to shorten the access time compared to the conventional method.

Further, since all the previous charge is discharged by the discharge signal DC, the next access time does not change depending on the memory information read last time, and is always a constant time. In addition, by setting the voltage value at each point at the start of detection to an intermediate level close to the detection threshold,
It is possible to detect at high speed.

〔Effect of the invention〕

As explained above, according to the present invention, the DC path between the two power supplies of the memory circuit is completely cut off, and the circuit is operated using only the charging current to the parasitic capacitance.
Lower power consumption can be achieved. Furthermore, since the previously charged charge is discharged and used as the initial condition, the next access time does not change depending on the previously read memory information, and high-speed reading is always possible.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional EPROM circuit, Fig. 2 is a block diagram of an EPROM circuit showing a first embodiment of the present invention, Fig. 3 is an operation time chart of Fig. 2, and Fig. 4 is a block diagram of the present invention. FIG. 5 is a block diagram of an EPROM circuit showing a second embodiment of the present invention, and FIG. 5 is an operation time chart of FIG. 1: memory matrix, 2: memory element,
X ₀ to _{X n} : Word (selection) line, Y ₀ to _{Y n} : Data selection line, B: Common data line, E: Detection point, PC:
Pre-charge signal, DC: Discharge signal,
Tr20: Voltage limiting transistor.

Claims (1)

[Claims] 1. A group of column selection transistors controlled by a column selection signal and connected to one end to a common data line and the other end to a data line, and the data line and word line (row selection line). A matrix of storage elements arranged at intersections, a transistor connected to the common data line and controlled by a first inverter having a predetermined threshold value, and a selected storage element connected to the drain side of the transistor. a detection circuit having means for detecting information; a transistor controlled by a second inverter that receives the potential of the common data line as an input and has a threshold higher than a threshold of the first inverter; , and a precharge transistor for connecting the transistor and the detection means of the detection circuit to a power source. 2. The precharging transistor is turned on almost simultaneously with the column selection operation, starts precharging the detection means and the data line, and completes the precharging before the row selection operation. The memory element circuit according to item 1. 3. When the precharge transistor is built into a microcomputer, it operates in synchronization with the internal clock of the microcomputer, and when it is a single memory, it operates as a static sense amplifier active signal instead. 2. The memory element circuit according to claim 1, wherein the detection means is operated by. 4. A memory arranged at the intersection of a group of column selection transistors controlled by a column selection signal and connected to a common data line at one end and a data line at the other end, and the data line and word line (row selection line). a matrix of elements, a transistor connected to the common data line and controlled by a first inverter having a predetermined threshold, and means connected to the drain side of the transistor for detecting stored information of a selected storage element. A storage element circuit having a detection circuit comprising a precharge transistor for connecting the common data line and the detection means of the detection circuit to a power supply, and connecting the common data line and the data line to the common data line. A memory element circuit characterized in that the voltage value is initially set to a voltage value determined by the charge distribution of the data line and the data line. 5. The precharging transistor is turned on almost simultaneously with the row selection operation to start precharging the detection means and the data line, and completes the precharging before the column selection operation. The memory element circuit described in Section 1. 6. The memory element circuit according to claim 4, wherein a transistor is connected to the data line, one end of which is grounded, and which is turned on at the same timing as the start of precharging to discharge the electric charge of the data line. . 7. After the row selection and column selection operations, the precharged charges are discharged only by the current flowing into the parasitic capacitance of the common data line and the selected data line. The memory element circuit according to item 5. 8. A memory arranged at the intersection of a group of column selection transistors controlled by a column selection signal and connected to a common data line at one end and a data line at the other end, and the data line and word line (row selection line). a matrix of elements, a transistor connected to the common data line and controlled by a first inverter having a predetermined threshold, and means connected to the drain side of the transistor for detecting stored information of a selected storage element. In a storage element circuit having a detection circuit and a microcomputer using the same, a first detection circuit detects a first voltage level of the common data line and a second voltage level of the common data line. A memory element circuit and a microcomputer using the same, characterized in that it has a second detection circuit for detection. 9. A memory arranged at the intersection of a group of column selection transistors controlled by a column selection signal and connected to one end to a common data line and the other end to a data line, and the data line and word line (row selection line). a matrix of elements, a transistor connected to the common data line and controlled by a first inverter having a predetermined threshold, and means connected to the drain side of the transistor for detecting stored information of a selected storage element. A first detection circuit that detects a first voltage level of the common data line; The first detection circuit has a second detection circuit for detecting a voltage level, a clock pulse generation means for driving the microcomputer, and an external terminal for inputting a signal to the first detection circuit. A memory element circuit and a microcomputer using the same, characterized in that the second detection circuit operates in response to a signal from the terminal, and the second detection circuit operates in response to a signal from the clock pulse generating means. 10. The method according to claim 8 or 9, wherein the second detection circuit precharges the voltage level of the common data line to a predetermined potential in response to a signal from a clock pulse generating means. A memory element circuit and a microcomputer using the same.