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JPH0545072B2 - - Google Patents
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JPH0545072B2 - - Google Patents

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Publication number
JPH0545072B2
JPH0545072B2 JP60225662A JP22566285A JPH0545072B2 JP H0545072 B2 JPH0545072 B2 JP H0545072B2 JP 60225662 A JP60225662 A JP 60225662A JP 22566285 A JP22566285 A JP 22566285A JP H0545072 B2 JPH0545072 B2 JP H0545072B2
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
substrate
single crystal
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60225662A
Other languages
Japanese (ja)
Other versions
JPS6285473A (en
Inventor
Akikazu Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60225662A priority Critical patent/JPS6285473A/en
Publication of JPS6285473A publication Critical patent/JPS6285473A/en
Publication of JPH0545072B2 publication Critical patent/JPH0545072B2/ja
Granted legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/30Hydrogen technology
    • Y02E60/50Fuel cells

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  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ガラス、金属、セラミツクス、プラ
スチツクス等による基板の上に単結晶膜を生成し
た太陽電池の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a solar cell in which a single crystal film is formed on a substrate made of glass, metal, ceramics, plastics, or the like.

[従来の技術] 一般的に多結晶よりも単結晶を用いた太陽電池
の方が高性能である事は言うまでもない。
[Prior Art] It goes without saying that solar cells using single crystals generally have higher performance than those using polycrystals.

従来、単結晶膜を用いた太陽電池を製作するに
あたつては、インゴツトより切り出したバルク単
結晶のウエハを基板とし、その上に単結晶膜を成
長させていた。
Conventionally, when manufacturing a solar cell using a single crystal film, a bulk single crystal wafer cut from an ingot was used as a substrate, and a single crystal film was grown on it.

しかしながら、上述の方法には、基板とする単
結晶ウエハが高価である上に、基板としては1mm
程度のかなりの厚みを要し、しかも、結晶裁断の
際の切りしろとして高価な材料を無駄にする等の
経済的、資源的欠点があつた。
However, in the above method, the single crystal wafer used as the substrate is expensive, and the substrate is only 1 mm thick.
Moreover, there were economic and resource disadvantages, such as the need for considerable thickness, and the waste of expensive materials as cutting allowances during crystal cutting.

[発明が解決しようとする問題点] そこで、本発明の目的は、上述した従来の欠点
を除去し、高価な単結晶基板を用いることなく、
すなわち、単結晶基板ではない基板、具体的には
例えば、ガラス基板、金属板、セラミツクスある
いは温度条件が許せばプラスチツク基板等、任意
材料の基板を用いて所望の化合物の単結晶膜を成
長させて構成した高性能、低コスト、省資源の太
陽電池の製造方法を提供することにある。
[Problems to be Solved by the Invention] Therefore, an object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to solve the problem without using an expensive single crystal substrate.
That is, a single crystal film of a desired compound is grown using a substrate other than a single crystal substrate, specifically, a substrate made of any material such as a glass substrate, a metal plate, a ceramic substrate, or a plastic substrate if temperature conditions permit. The object of the present invention is to provide a method for manufacturing a high-performance, low-cost, and resource-saving solar cell.

[問題点を解決するための手段] 本発明にかかる太陽電池の製造方法は、単結晶
基板ではない基板上に、太陽電池の接合を含む活
性層を作るための化合物半導体層を堆積させる工
程と、化合物半導体層上に化合物半導体を構成す
る成分の単体金属層を堆積させる工程と、単体金
属層で覆われた化合物半導体層をその融点を含む
範囲の温度に加熱してから常温にまで冷却して単
体金属層と基板との間に化合物半導体の単結晶層
を形成する工程とを具えたことを特徴とする。
[Means for Solving the Problems] A method for manufacturing a solar cell according to the present invention includes a step of depositing a compound semiconductor layer for forming an active layer including a junction of a solar cell on a substrate that is not a single crystal substrate. , a step of depositing an elemental metal layer of a component constituting the compound semiconductor on the compound semiconductor layer, and heating the compound semiconductor layer covered with the elemental metal layer to a temperature in a range including its melting point, and then cooling it to room temperature. The method is characterized by comprising a step of forming a single crystal layer of a compound semiconductor between the single metal layer and the substrate.

すなわち、単結晶基板ではない任意所望材料に
よる基板上に、所望の太陽電池用化合物半導体膜
(通常は多結晶膜)を堆積させ、その上に堆積化
合物成分のうち低融点でかつ低蒸気圧側の金属の
単体成分を更に堆積させて化合物を蔽い、しかる
後に、その化合物融点近くの温度まで基板温度を
上昇させて再結晶化させた後、常温まで温度を降
下させることにより、再結晶と液相成長を混成し
た方法により、当該基板上に単結晶膜を形成す
る。
That is, a desired compound semiconductor film for solar cells (usually a polycrystalline film) is deposited on a substrate made of any desired material other than a single-crystal substrate, and a compound semiconductor film with a low melting point and low vapor pressure among the deposited compound components is deposited on top of the substrate. The metal element is further deposited to cover the compound, and then the substrate temperature is raised to a temperature close to the melting point of the compound to cause recrystallization, and then the temperature is lowered to room temperature to perform recrystallization and liquid crystallization. A single crystal film is formed on the substrate by a method combining phase growth.

化合物半導体の堆積層の上を蔽つている単体金
属成分層は太陽電池の片側電極として構成した
り、あるいはかかる単体金属成分層を除去して、
更にその生成された単結晶膜上に化合物半導体を
エピタキシー成長させることにより高品質単結晶
膜を成長させて種々の太陽電池すなわち、ヘテロ
接合、p−n接合、シヨツトキー接合等をもつ太
陽電池を構成してもよい。
The single metal component layer covering the deposited layer of compound semiconductor can be configured as one side electrode of a solar cell, or by removing such a single metal component layer,
Furthermore, by epitaxially growing a compound semiconductor on the produced single crystal film, a high quality single crystal film is grown to construct various solar cells, that is, solar cells having heterojunctions, pn junctions, Schottky junctions, etc. You may.

[作用] 本発明によれば、単結晶基板ではない任意所望
の基板、すなわち従来極めて困難とされていた、
ガラス、金属、セラミツクス、プラスチツクス等
の任意所望の材料の基板上に単結晶半導体膜を生
成し、しかも比較的大面積の単結晶膜を得ること
により、多結晶膜太陽電池よりも遥かに高効率の
太陽電池を低コストかつ省資源に貢献しながら製
造することが可能となり、太陽電池の発展普及に
大きく寄与する。
[Function] According to the present invention, any desired substrate other than a single crystal substrate, that is, it has been considered extremely difficult to
By producing a single-crystalline semiconductor film on a substrate of any desired material such as glass, metal, ceramics, plastics, etc., and obtaining a relatively large-area single-crystalline film, the cost is much higher than that of polycrystalline film solar cells. This makes it possible to manufacture highly efficient solar cells at low cost and while contributing to resource conservation, greatly contributing to the development and spread of solar cells.

[実施例] 以下に、図面を参照して本発明を詳細に説明す
る。
[Example] The present invention will be described in detail below with reference to the drawings.

第1図AおよびBは本発明により製造したヘテ
ロ接合太陽電池の実施例を示し、ここで、1は透
明ガラス基板、7は基板1上に配置したIn2O3
SnO2等のネサ膜、7′はネサ膜7に取付けた電
極、3はネサ膜7上に堆積させたInP、GaAs等
の化合物半導体層、5はこの化合物半導体層3を
覆うIn、Ga等の単体金属被覆層を示す。5′は層
5の上より取出した電極を示す。起電力は電極
5′と7′との間から取出す。化合物半導体層3が
InPの場合には電極5はInを用い、化合物半導体
層3がGaAsの場合には電極5はGaを用いる。化
合物半導体層3としてInPを用いた場合、この層
3の厚さは約1〜5μm程度とし、電極5として
のInの厚さは約10μm程度とする。この場合、例
えば、ネサ膜7がn型半導体ならば、InPまたは
GaAsがp型半導体になるように半導体層3ある
いは単体金属被覆層5中にp型のドーパント(不
純物)を混入する。
1A and 1B show an example of a heterojunction solar cell manufactured according to the present invention, where 1 is a transparent glass substrate, 7 is an In 2 O 3 disposed on the substrate 1,
7 ' is an electrode attached to the NESA film 7, 3 is a compound semiconductor layer such as InP or GaAs deposited on the NESA film 7, and 5 is In, Ga, etc. that covers this compound semiconductor layer 3. A single metal coating layer is shown. 5' indicates an electrode taken out from above layer 5. The electromotive force is extracted from between electrodes 5' and 7'. The compound semiconductor layer 3
In the case of InP, the electrode 5 is made of In, and when the compound semiconductor layer 3 is made of GaAs, the electrode 5 is made of Ga. When InP is used as the compound semiconductor layer 3, the thickness of this layer 3 is about 1 to 5 μm, and the thickness of In as the electrode 5 is about 10 μm. In this case, for example, if the NESA film 7 is an n-type semiconductor, InP or
A p-type dopant (impurity) is mixed into the semiconductor layer 3 or the single metal coating layer 5 so that GaAs becomes a p-type semiconductor.

第1図Bのように積層した後、この積層を短時
間にわたりInPの融点近くに昇温して加熱した
後、直ちに室温に戻すことにより、化合物半導体
層3のInPは再結晶化し同時に電極5のIn中に昇
温時に含まれたPがInと共に再結晶してできた
InP単結晶面上に接触するようになり、いわゆる
InPの液相成長が起こり、電極7のネサ膜と電極
5のInに挟まれたInP単結晶膜が生成される。
After laminating the layers as shown in FIG. The P contained in the In during heating was recrystallized together with the In.
It comes into contact with the InP single crystal plane, so-called
Liquid phase growth of InP occurs, and an InP single crystal film sandwiched between the Nesa film of the electrode 7 and the In of the electrode 5 is generated.

上述の化合物半導体層3および単体金属層5の
蒸着による形成並びに単結晶化処理の一連工程に
おける基板1の温度変化と経過時間との関係の一
例を第3図に示す。まず、基板1の温度を270℃
に保ちながら、いずれも純度6nineのインジウム
Inと赤燐Pとをそれぞれ収容した別個の蒸着源ル
ツボからネサ膜7上に分子線蒸着すなわち超高真
空蒸着を行う。その蒸着前の真空度は5.5×
10-9Torr、蒸着時の真空度は燐Pの蒸気圧によ
り1.5×10-7Torr程度となつた。なお、インジウ
ムInは700〜800℃、燐Pは約300℃でそれぞれ蒸
発した。このようにして厚さ3μmのInP化合物膜
3の合成被着を行つた後、引続き、p用ルツボの
温度を下げて燐Pの蒸発を停止し、In用ルツボか
らのインジウムInのみの蒸着を続行して厚さ約
18μmのIn被膜5を化合物膜3上に積層する。か
かる積層3,5の形成は、第3図に示したタイム
チヤートにおける区間b−cにおいて基板1の温
度を270℃に保つたまま行う。引続いて、基板1
の温度を、一旦、区間c−fにて順次に低下させ
た後に、区間f−hにおいて、基板1の温度を約
1000℃まで急速に上昇させた後、自然放熱冷却に
より常温に降下させる。化合物InPの融点は1060
℃であるから、かかる1000℃までの温度急上昇の
過程において化合物InPが再結晶し、その結晶粒
が肥大化するとともに、いずれの結晶粒も基板1
の面に平行な(111)面が優位配向となる。その
再結晶に際して、予め蒸着したInP化合物の不純
物が極めて少なければ、結晶粒界を形成する不純
物も極めて少なくなつて結晶粒界はほとんど無く
なるか、極めてわずかに存在するか、のいずれか
となる。
FIG. 3 shows an example of the relationship between the temperature change of the substrate 1 and the elapsed time in a series of steps of forming the compound semiconductor layer 3 and the single metal layer 5 by vapor deposition and single crystallization treatment described above. First, set the temperature of substrate 1 to 270℃.
All use 6nine purity indium while maintaining
Molecular beam deposition, that is, ultra-high vacuum deposition, is performed on the Nesa film 7 from separate deposition source crucibles containing In and red phosphorus P, respectively. The degree of vacuum before vapor deposition is 5.5×
10 -9 Torr, and the degree of vacuum during vapor deposition was approximately 1.5×10 -7 Torr due to the vapor pressure of phosphorus P. In addition, indium In was evaporated at 700 to 800°C, and phosphorus P was evaporated at about 300°C. After synthetically depositing the InP compound film 3 with a thickness of 3 μm in this manner, the temperature of the P crucible is lowered to stop the evaporation of phosphorus P, and only indium In is deposited from the In crucible. Continue to thickness approx.
An 18 μm In film 5 is laminated on the compound film 3. The formation of the laminated layers 3 and 5 is performed while the temperature of the substrate 1 is maintained at 270 DEG C. in the section b-c in the time chart shown in FIG. Subsequently, board 1
Once the temperature of the substrate 1 is lowered sequentially in sections c-f, the temperature of the substrate 1 is lowered to approximately
After rapidly raising the temperature to 1000℃, the temperature is lowered to room temperature through natural cooling. The melting point of the compound InP is 1060
℃, the compound InP recrystallizes in the process of rapid temperature rise to 1000℃, its crystal grains enlarge, and all crystal grains
The (111) plane parallel to the plane is the dominant orientation. During recrystallization, if the impurities in the pre-deposited InP compound are extremely low, the impurities that form grain boundaries will also be extremely low, and grain boundaries will either be almost absent or only slightly present.

しかして、InP化合物中に存在する蒸気圧の高
い燐Pは解離して脱出しようとするが、表面をIn
被膜によつて蔽われているために脱出し得ず、一
部の燐PがインジウムIn中に溶け込む。ついで、
上述したように基板温度が再結晶温度約1000℃に
達した後に、直ちに自然放熱により室温まで低下
させると、その自然冷却過程において前述の再結
晶過程で生成した単結晶乃至単結晶に近い(111)
面優先配向の状態にある下地のInP化合物膜3の
上に、上述のようにして燐Pが溶け込んでいるイ
ンジウムInの融液が接触して液相エピタキシヤル
成長が行われるかあるいは再結晶と液相成長が同
時に起るものと考えられる。ここで注意すべき
は、もし再結晶温度1000℃に長時間保持しておれ
ば、InP化合物層3とIn被膜5とが互いに拡散融
合してしまい、所望の成膜が得られなくなるおそ
れがあるので融点近傍の温度保持は極力短時間、
例えば1〜3分程度にとどめる。
However, the phosphorus P, which has a high vapor pressure and exists in the InP compound, tries to dissociate and escape, but the surface
Since it is covered by the film, it cannot escape, and some of the phosphorus P dissolves into the indium In. Then,
As mentioned above, if the substrate temperature reaches the recrystallization temperature of approximately 1000°C and is immediately lowered to room temperature by natural heat dissipation, the natural cooling process produces a single crystal or close to a single crystal (111 )
The melt of indium In in which phosphorus P is dissolved as described above comes into contact with the underlying InP compound film 3 which is in a plane-preferential orientation state, and liquid phase epitaxial growth or recrystallization is performed. It is thought that liquid phase growth occurs simultaneously. It should be noted here that if the recrystallization temperature is kept at 1000°C for a long time, the InP compound layer 3 and the In coating 5 will diffuse and fuse with each other, and there is a risk that the desired film formation will not be obtained. Therefore, keep the temperature near the melting point for as short a time as possible.
For example, keep it to about 1 to 3 minutes.

要するに、本発明における単結晶膜成長の過程
においては、再結晶により単結晶または単結晶に
近い状態にあつて、しかも、基板面に平行な
(111)面優先配向を有するInP化合物膜が種単結
晶膜となつて、その上にInP化合物の液相エピタ
キシヤル成長が行われることにより、単結晶化の
改善促進がなされるものと考えられる。
In short, in the process of single-crystal film growth in the present invention, an InP compound film that is in a single-crystal or near-single-crystal state by recrystallization and has a preferential orientation of the (111) plane parallel to the substrate surface is grown as a seed monolayer. It is thought that improvement of single crystallization is promoted by forming a crystalline film and performing liquid phase epitaxial growth of the InP compound thereon.

さらに電力取出用電極5′および7′をそれぞれ
層5および7に取付けることにより、ヘテロ接合
太陽電池が構成される。太陽光はガラス基板1の
側から照射する。ネサ膜7がInPよりも広い禁制
帯幅を持つていればその窓効果によりさらに高い
効率が得られることは言うまでもない。
Further, by attaching power extraction electrodes 5' and 7' to layers 5 and 7, respectively, a heterojunction solar cell is constructed. Sunlight is irradiated from the glass substrate 1 side. Needless to say, if the Nesa film 7 has a wider forbidden band width than InP, even higher efficiency can be obtained due to its window effect.

本発明pn接合太陽電池の一例を第2図Aおよ
びBに示す。ここで、1は透明ガラス基板、2は
基板1上に配置され、化合物半導体層3に接触す
るオーム性電極から成る櫛形または格子状電極、
3はInPやGaAs等の化合物半導体層、5はIn、
Ga等の単体金属による被膜層を示す。起電力は
電極2に取り付けた電極2′と層5に取り付けた
電極5′との間より取り出す。化合物半導体層3
がInPの場合には層5としてIn、層3がGaAsの
場合には層5としてGaを用いる。層3と層5と
の間にはpまたはn形半導体単結晶膜4を配置す
る。なお、層3がn形半導体層の場合、単結晶膜
4としてp形半導体層が形成されるように単体金
属被覆層5の生成時に、この層5中にp形ドーパ
ント、例えばZn、Mg、Be等を膜4に近い側の層
5内に混入しておく。今、層3としてInPを用い
た場合、例えば化合物半導体層3の厚さは約1〜
5μm程度とし、その上に上述したpn接合形成の
ためのドーパントを混入した層をIn層またはInP
層にドーパント混入により構成する。しかる後、
この積層をInPの融点付近まで短時間加熱し、そ
の後自然放冷により常温に戻す。第1図で説明し
たときの原理と全く同様にn(p)形半導体単結晶膜
3とp(n)形半導体単結晶膜4がガラス基板1およ
び櫛形電極2とIn層5との間に形成される。以上
によりpn接合太陽電池が構成される。
An example of the pn junction solar cell of the present invention is shown in FIGS. 2A and 2B. Here, 1 is a transparent glass substrate, 2 is a comb-shaped or grid-shaped electrode made of an ohmic electrode arranged on the substrate 1 and in contact with the compound semiconductor layer 3;
3 is a compound semiconductor layer such as InP or GaAs, 5 is In,
Indicates a coating layer made of a simple metal such as Ga. The electromotive force is taken out between the electrode 2' attached to the electrode 2 and the electrode 5' attached to the layer 5. Compound semiconductor layer 3
When the layer 3 is InP, In is used as the layer 5, and when the layer 3 is GaAs, the layer 5 is Ga. A p- or n-type semiconductor single crystal film 4 is arranged between layers 3 and 5. Note that when the layer 3 is an n-type semiconductor layer, a p-type dopant such as Zn, Mg, Be or the like is mixed into the layer 5 on the side closer to the membrane 4. Now, when InP is used as the layer 3, for example, the thickness of the compound semiconductor layer 3 is about 1~
The thickness is about 5 μm, and on top of that, a layer mixed with the above-mentioned dopant for forming a pn junction is formed as an In layer or InP layer.
It is constructed by mixing a dopant into the layer. After that,
This stack is heated for a short time to around the melting point of InP, and then allowed to cool naturally to return to room temperature. In exactly the same way as the principle explained in FIG. It is formed. The above constitutes a pn junction solar cell.

太陽光はガラス基板1の側から照射される。 Sunlight is irradiated from the glass substrate 1 side.

更に、例えばこの方法でInPまたはGaAsの単
結晶層3を形成した後にInP単結晶層あるいは
GaAs単結晶層3上に被膜されたそれぞれInある
いはGa層をその融点以上(例えばInでは約200
℃)で拭い取るとか、回転遠心力により脱離除去
するか、あるいはエツチングで除去した後、その
生成単結晶層3の面上に所望単結晶のエピタキシ
ヤル成長を行いながらpn接合、ヘテロ接合、あ
るいはシヨツトキー接合等を構成して単結晶膜太
陽電池を作製することができる。
Furthermore, for example, after forming the InP or GaAs single crystal layer 3 using this method, an InP single crystal layer or
The In or Ga layer coated on the GaAs single crystal layer 3 is heated at a temperature higher than its melting point (for example, about 200
℃), or removed by rotational centrifugal force, or removed by etching, while epitaxially growing a desired single crystal on the surface of the resulting single crystal layer 3, forming a p-n junction, a heterojunction, etc. Alternatively, a single crystal film solar cell can be fabricated by forming a Schottky junction or the like.

なお、上述の積層の生成および構成は、蒸着方
法、スパツタ方法、CVD方法等により行い、再
結晶化および液相成長は真空中あるいはAr、N2
等の不活性ガス中で行う。
The formation and configuration of the above-mentioned stacked layers is performed by a vapor deposition method, a sputtering method, a CVD method, etc., and the recrystallization and liquid phase growth are performed in a vacuum or using Ar, N 2
It is carried out in an inert gas such as

更に、太陽光受光側に反射防止膜を設けて太陽
電池効率向上を図ることができることはいうまで
もない。
Furthermore, it goes without saying that an antireflection film can be provided on the sunlight receiving side to improve solar cell efficiency.

[発明の効果] 以上から明らかなように、本発明によれば、従
来極めて困難とされていた、ガラス、金属、セラ
ミツクス、プラスチツクス等の任意所望の材料の
基板上に単結晶半導体膜を生成し、 しかも比較的大面積の単結晶膜を得ることによ
り、多結晶膜太陽電池よりも遥かに高効率の太陽
電池を低コストかつ省資源に貢献しながら製造す
ることが可能となり、太陽電池の発展普及に大き
く寄与する。
[Effects of the Invention] As is clear from the above, according to the present invention, it is possible to produce a single crystal semiconductor film on a substrate made of any desired material such as glass, metal, ceramics, plastics, etc., which has been considered extremely difficult in the past. Moreover, by obtaining a single crystal film with a relatively large area, it becomes possible to manufacture solar cells with much higher efficiency than polycrystalline film solar cells at low cost and while contributing to resource conservation. It will greatly contribute to the development and popularization.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図AおよびBは本発明方法により製造した
ヘテロ接合太陽電池の一実施例を示す、それぞ
れ、上面図および断面図、第2図AおよびBは本
発明方法により製造したpn接合太陽電池の構成
一例を示す、それぞれ、上面図および断面図、第
3図は本発明単結晶半導体膜生成過程実施例にお
ける基板温度変化の一例を示すタイムチヤートで
ある。 1……基板、2……櫛形または格子状電極、3
……化合物半導体層および単結晶化合物n(p)型半
導体層、4……化合物半導体層および単結晶化合
物n(n)型半導体層、5……単体金属被覆層、7…
…ネサ膜、2′,5′,7′……電極。
Figures 1A and B show an example of a heterojunction solar cell manufactured by the method of the present invention, respectively, a top view and a cross-sectional view, and Figures 2A and B show a pn junction solar cell manufactured by the method of the present invention. FIG. 3 is a top view and a cross-sectional view showing an example of the structure, respectively, and a time chart showing an example of substrate temperature change in an embodiment of the single crystal semiconductor film production process of the present invention. 1... Substrate, 2... Comb-shaped or grid-shaped electrode, 3
...Compound semiconductor layer and single crystal compound n(p) type semiconductor layer, 4...Compound semiconductor layer and single crystal compound n(n) type semiconductor layer, 5...Single metal coating layer, 7...
...Nesa membrane, 2', 5', 7'... electrode.

Claims (1)

【特許請求の範囲】 1 単結晶基板ではない基板上に、太陽電池の接
合を含む活性層を作るための化合物半導体層を堆
積させる工程と、該化合物半導体層上に当該化合
物半導体を構成する成分の単体金属層を堆積させ
る工程と、該単体金属層で覆われた前記化合物半
導体層をその融点を含む範囲の温度に加熱してか
ら常温にまで冷却して前記単体金属層と基板との
間に前記化合物半導体の単結晶層を形成する工程
とを具えたことを特徴とする太陽電池の製造方
法。 2 単結晶基板ではない基板上に、太陽電池の接
合を含む活性層を作るための化合物半導体層を堆
積させる工程と、該化合物半導体層上に当該化合
物半導体を構成する成分の単体金属層を堆積させ
る工程と、該単体金属層で覆われた前記化合物半
導体層をその融点を含む範囲の温度に加熱してか
ら常温にまで冷却して前記単体金属層と基板との
間に前記化合物半導体の単結晶層を形成する工程
と、前記単体金属層が除去された単結晶化合物半
導体層の露出面上に当該単結晶のエピタキシヤル
成長を行いながら接合を作る工程とを具えたこと
を特徴とする太陽電池の製造方法。
[Claims] 1. A step of depositing a compound semiconductor layer for forming an active layer including a junction of a solar cell on a substrate that is not a single crystal substrate, and a step of depositing a compound semiconductor layer on the compound semiconductor layer, and a component constituting the compound semiconductor on the compound semiconductor layer. heating the compound semiconductor layer covered with the single metal layer to a temperature in a range including its melting point and then cooling it to room temperature to create a gap between the single metal layer and the substrate. A method for manufacturing a solar cell, comprising: forming a single crystal layer of the compound semiconductor. 2. A step of depositing a compound semiconductor layer for forming an active layer including a solar cell junction on a substrate that is not a single crystal substrate, and depositing an elemental metal layer of a component constituting the compound semiconductor on the compound semiconductor layer. a step of heating the compound semiconductor layer covered with the single metal layer to a temperature in a range including its melting point and then cooling it to room temperature to form a single layer of the compound semiconductor between the single metal layer and the substrate. A solar method comprising the steps of forming a crystal layer and forming a junction while epitaxially growing the single crystal on the exposed surface of the single crystal compound semiconductor layer from which the single metal layer has been removed. How to manufacture batteries.
JP60225662A 1985-10-09 1985-10-09 Solar cell and manufacture thereof Granted JPS6285473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60225662A JPS6285473A (en) 1985-10-09 1985-10-09 Solar cell and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60225662A JPS6285473A (en) 1985-10-09 1985-10-09 Solar cell and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS6285473A JPS6285473A (en) 1987-04-18
JPH0545072B2 true JPH0545072B2 (en) 1993-07-08

Family

ID=16832808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60225662A Granted JPS6285473A (en) 1985-10-09 1985-10-09 Solar cell and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6285473A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289890A (en) * 2001-03-27 2002-10-04 Nagoya Kogyo Univ Solar cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5075382A (en) * 1973-11-05 1975-06-20
JPS5117033A (en) * 1974-07-31 1976-02-10 Masuyuki Naruse Nenshokino nenshoantei oyobi kakibutono reikyakuhoho
IT1048834B (en) * 1974-11-08 1980-12-20 Western Electric Co PHOTOVOLTAIC CELL PERFECTED

Also Published As

Publication number Publication date
JPS6285473A (en) 1987-04-18

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