JPH0545075B2 - - Google Patents
Info
- Publication number
- JPH0545075B2 JPH0545075B2 JP61077005A JP7700586A JPH0545075B2 JP H0545075 B2 JPH0545075 B2 JP H0545075B2 JP 61077005 A JP61077005 A JP 61077005A JP 7700586 A JP7700586 A JP 7700586A JP H0545075 B2 JPH0545075 B2 JP H0545075B2
- Authority
- JP
- Japan
- Prior art keywords
- superconducting
- signal line
- signal
- circuit
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はジヨセフソン接合装置に関し、特にジ
ヨセフソン論理回路やジヨセフソン記憶回路とし
て用いられるジヨセフソン接合装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Josephson junction device, and more particularly to a Josephson junction device used as a Josephson logic circuit or a Josephson memory circuit.
従来、ジヨセフソン論理回路やジヨセフソン記
憶回路として用いられるジヨセフソン接合装置
は、１枚の接地板上の同一平面上に配置されてい
た。
Conventionally, Josephson junction devices used as Josephson logic circuits and Josephson memory circuits have been arranged on the same plane on one ground plane.
その具体例を記載した文献には、(イ)1980年３月
発行のアイビーエム・ジヤーナル・オブ・リサー
チ・アンド・デイベロツプメント（IBM
Journal of Research and Development）第24
巻、第２号、第155頁、(ロ)1983年５月発行のアイ
イーイーイー・エレクトロン・デバイス・レター
ズ（IEEE Electron Device Letters）第EDL−
４巻、第５号、第150頁、(ハ)1979年10月発行のア
イイーイーイー・ジヤーナル・オブ・ソリツド・
ステイト・サーキツト（IEEE Journal of Solid
−State Circuits）第SC−14巻、第５号、第794
頁等がある。 Literature describing specific examples includes (a) IBM Journal of Research and Development (IBM) published in March 1980;
Journal of Research and Development) No. 24
Volume, No. 2, Page 155, (b) IEEE Electron Device Letters, No. EDL, published May 1983.
Volume 4, No. 5, Page 150, (c) IEE Journal of Solids, published October 1979.
State Circuits (IEEE Journal of Solid
-State Circuits) Volume SC-14, No. 5, No. 794
There are pages etc.
これらの記憶回路は、一平面上に配置されいる
ため、各記憶セルを選択・駆動する信号線は、行
方向もしくは列方向の各記憶セルを駆動した後、
それぞれ折返されて各信号線の駆動回路の他端に
接続されいた。即ち各信号線は記憶セルのゲート
回路を駆動した後記憶ループの外側もしくはその
上側や下側を通つて駆動回路へ戻されていた。一
方、従来ジヨセフソン接合装置を積み重ねて３次
元的に配置することは、特開昭53−50986号公報
によつて示されていた。しかしながらジヨセフソ
ン回路装置の具体的配置に関しては、全く示され
ていない。 These memory circuits are arranged on one plane, so the signal lines that select and drive each memory cell are connected to each other after driving each memory cell in the row or column direction.
Each signal line was folded back and connected to the other end of the drive circuit of each signal line. That is, after each signal line drives the gate circuit of the memory cell, it is returned to the drive circuit through the outside of the memory loop, or above or below it. On the other hand, Japanese Patent Application Laid-Open No. 53-50986 discloses that conventional Josephson bonding devices can be stacked and arranged three-dimensionally. However, no information is given regarding the specific arrangement of the Josefson circuit device.
上述した従来のジヨセフソン接合装置は、各信
号線の戻り線を設けるための余分の面積を必要と
し装置全体の寸法が大きくなつていた。
The above-mentioned conventional Josephson bonding device requires an extra area to provide return lines for each signal line, resulting in an increase in the overall size of the device.
又、装置の全体寸法を増大させないことを目的
として、回路パターンの上側もしくは下側に戻り
線を設ける場合には、回路の構造を複雑にし、製
造程数を増大させた。従つて、従来の装置は、戻
り線パターンが設けられたことによるパターン段
差の問題や、工程数の増大による製造歩留りの低
下をまねくという問題があつた。 Furthermore, when a return line is provided above or below the circuit pattern in order to avoid increasing the overall size of the device, the structure of the circuit becomes complicated and the number of manufacturing steps increases. Therefore, the conventional apparatus has problems such as a pattern step difference due to the provision of the return line pattern and a decrease in manufacturing yield due to an increase in the number of steps.
一方、回路の動作に関しては、従来のジヨセフ
ソン接合装置は戻り線を信号が伝搬する戻り線信
号伝送時間を必要とするため回路装置全体の動作
の高速化が制約されていた。さらに、戻り線を設
けるための回路面積の増大も動作速度を遅らせる
ため、一層回路の高速動作が因難になつていた。 On the other hand, regarding the operation of the circuit, the conventional Josephson bonding device requires return line signal transmission time for the signal to propagate through the return line, which limits the speed of operation of the entire circuit device. Furthermore, the increase in circuit area required to provide the return line also slows down the operating speed, making it even more difficult to operate the circuit at high speed.
本発明の目的は、集積度及び動作速度の改善さ
れた３次元的に配置されたジヨセフソン接合装置
を提供することにある。本発明の他の目的は、構
造が簡単で製造歩留り及び信頼性の向上した３次
元元的に配置されたジヨセフソン接合装置を提供
することにある。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensionally arranged Josephson bonding device with improved integration and operating speed. Another object of the present invention is to provide a three-dimensionally arranged Josephson bonding device which is simple in structure and has improved manufacturing yield and reliability.
本発明のジヨセフソン接合装置は、第１の超伝
導性接地板の一主表面上に絶縁層を介して配置さ
れた第１の複数の負荷回路を駆動する第１の超伝
導性信号線と、第２の超伝導性接地板の一主表面
上に他の絶縁層を介して配置された第２の複数の
負荷回路を駆動する第２の超伝導性信号線と、前
記第１、第２の超伝導性信号線に駆動信号を供給
するジヨセフソン接合を含む駆動回路とが、前記
第１または第２の超伝導性接地板のいずれか一方
に設けられた貫通孔内を通る結合線で結ばれて閉
ループを構成し、前記第１の超伝導性信号線また
は前記第２の超伝導性信号線のいずれか一方を信
号の往路とし他方を信号の復路としたというもの
である。
The Josephson junction device of the present invention includes: a first superconducting signal line for driving a first plurality of load circuits disposed on one main surface of a first superconducting ground plate with an insulating layer interposed therebetween; a second superconducting signal line for driving a second plurality of load circuits disposed on one main surface of the second superconducting ground plate with another insulating layer interposed therebetween; A drive circuit including a Josephson junction that supplies a drive signal to the superconducting signal line of the first or second superconducting ground plate is connected to the drive circuit by a coupling line passing through a through hole provided in either the first or second superconducting ground plate. A closed loop is formed by using one of the first superconducting signal line and the second superconducting signal line as an outgoing signal path and the other as a returning signal path.
ジヨセフソン接合を含む駆動回路により発生さ
れる駆動信号は、まず例えば第１の超伝導性信号
線に接続されている複数の負荷回路を順次駆動す
る。その後、駆動信号は第１又は第２の超伝導性
接地板を貫いて設けられた結合線を経て第２の超
伝導性信号線へ伝送され、同様にして第２の超伝
導性信号線に接続されている複数の負荷回路を駆
動したのち再度第１又は第２の超伝導接地板を貫
いて駆動回路の他端に戻される。ここで第２の超
伝導性信号線はその終端が駆動回路の近傍に来る
ように配置される。即ちこの場合、第１の超伝導
性信号線が信号の往路となり、第２の超伝導性信
号線が信号の復路となる。
A drive signal generated by a drive circuit including a Josephson junction first sequentially drives a plurality of load circuits connected to, for example, a first superconducting signal line. Thereafter, the drive signal is transmitted to the second superconducting signal line via a coupling line provided through the first or second superconducting ground plane, and similarly to the second superconducting signal line. After driving a plurality of connected load circuits, it passes through the first or second superconducting ground plate again and returns to the other end of the drive circuit. Here, the second superconducting signal line is arranged so that its terminal end is near the drive circuit. That is, in this case, the first superconducting signal line becomes the outgoing path of the signal, and the second superconducting signal line becomes the incoming path of the signal.
以上説明した様に、本発明の装置においては、
各伝送線路の信号線は戻り線を特に設ける必要は
ない。何となれば、各信号電流の戻り電流は、影
像電流として第１および第２の超伝導性接地板上
を流れるからである。なお、第１および第２の超
伝導性接地板は、各超伝導性信号線の始端と終端
の近傍で接続して置けばよい。 As explained above, in the device of the present invention,
There is no particular need to provide a return line for the signal line of each transmission line. This is because the return current of each signal current flows on the first and second superconducting ground planes as an image current. Note that the first and second superconducting ground planes may be connected to each other near the starting and ending ends of each superconducting signal line.
従つて、信号の伝送時間が戻り線のある従来の
およそ半分となり、動作速度を速くすることがで
きる。又、戻り線の配置が不要になつたため、回
路面積が小さくなり、回路の高集積化が行える。
更に、戻り線が別途配線層に設けられている従来
例に比べると、その配線層が不要であるので構造
簡単になり製造工程が削減され歩留りが高くな
る。 Therefore, the signal transmission time is approximately half that of the conventional method with a return line, and the operation speed can be increased. Furthermore, since it is no longer necessary to arrange a return line, the circuit area is reduced and the circuit can be highly integrated.
Furthermore, compared to the conventional example in which the return line is provided in a separate wiring layer, since the wiring layer is not required, the structure is simplified, the number of manufacturing steps is reduced, and the yield is increased.
次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の概略を説明するた
めの斜視模式図である。 FIG. 1 is a schematic perspective view for explaining the outline of an embodiment of the present invention.
この実施例は第１の超伝導性接地板１の一主表
面上に絶縁層を介して配置された第１の複数の負
荷回路５−１ａ〜５−１ｄを駆動する第１の超伝
導性信号線４−１と、第２の超伝導性接地板２の
一主表面上に他の絶縁層を介して配置された第２
の複数の負荷回路７−１ａ〜７−１ｄを駆動する
第２の超伝導性信号線６−２と、第１、第２の超
伝導性信号線６−１，６−２に駆動信号を供給す
るジヨセフソン接合を含む駆動回路３−１とが、
第２の超伝導性接地板に設けられた貫通孔内を通
る接合線９−１，８−１で結ばれて閉ループを構
成し、第１の超伝導性信号線４−１および第２の
超伝導性信号線６−１のうち前者を信号の往路と
し後者を信号の復路としたというものである。 This embodiment is a first superconducting ground plate 1 that drives a plurality of first load circuits 5-1a to 5-1d arranged on one main surface of a first superconducting ground plate 1 with an insulating layer interposed therebetween. The signal line 4-1 and a second superconducting ground plate 2 disposed on one main surface of the second superconducting ground plate 2 with another insulating layer interposed therebetween.
A drive signal is applied to the second superconducting signal line 6-2 that drives the plurality of load circuits 7-1a to 7-1d, and the first and second superconducting signal lines 6-1 and 6-2. A drive circuit 3-1 including a Josephson junction to be supplied,
They are connected by bonding lines 9-1 and 8-1 passing through the through holes provided in the second superconducting ground plate to form a closed loop, and the first superconducting signal line 4-1 and the second Of the superconducting signal lines 6-1, the former is used as an outgoing signal path, and the latter is used as a returning signal path.
なお、図には駆動回路３−2を含む同様の回路
がもう一つ示されているが、その数は任意であ
る。たとえば1Kビツトメモリを32×32のマトリ
ツクスで構成する時には、少くとも32組、場合に
より64組の駆動回路と超伝導性信号線を設ければ
よい。この場合、各超伝導性信号線が駆動する負
荷回路は記憶セルとなる。 Note that although the figure shows one more circuit similar to the drive circuit 3-2 , the number of such circuits is arbitrary. For example, when configuring a 1K bit memory with a 32 x 32 matrix, it is sufficient to provide at least 32 sets, and possibly 64 sets of drive circuits and superconducting signal lines. In this case, the load circuit driven by each superconducting signal line becomes a memory cell.
第２図は本発明のジヨセフソン・チツプの主要
部の断面図である。図に於て、厚さ方向（高さ向
そ同義）の寸法は図を見易くするために拡大して
示してある。第１の超伝導性信号線４−1、負荷
回路５−1a〜５−1d及び駆動回路４−1とからなる
第１の回路群は基板１０上にスパツタ等によつて
成膜された厚さ300nｍ程度のニオブ等の超伝導
体からなる第１の超伝導性接地板１上に厚さ100
〜200nｍの絶縁層４１を介して配置される。第
１の回路群上に厚さ数μｍ〜10μｍ程度のSiO、
SiO2等の絶縁体からなる絶縁層４２をスパツタ
もしくは蒸着等により形成した後厚さ300nｍ程
度のニオブ等の超伝導体からなる第２の超伝導性
接地板２をスパツタ等によつて形成する。第２の
超伝導性信号線６−1、負荷回路７−1a〜７−1dか
らなる第２の回路群は第２の超伝導性接地板２上
に厚さ100〜200nｍの絶縁層４３を介して配置さ
れる。第１の回路群において信号の影像電流は第
１の超伝導性接地板１の表面を流れ、第２の回路
群において信号の影像電流は、第２の超伝導性接
地板２の表面を流れる様に、第１の回路群と第２
の超伝導性接地板２との間隔が設定されている。
第１の回路群中の厚さ300nｍ程度のニオブ等の
超伝導体からなる対向電極１１、ジヨセフソン接
合１２、厚さ200nｍ程度のニオブ等の超伝導体
からなる基部電極１３からなる駆動回路３−1で
発生された駆動信号は、配線２１→２２→２３→
２４へとコンタクト３１〜３３を介して伝送され
る。第１の超伝導性信号線の終端は数マイクロメ
ータ角の超伝導体柱等からなる結合線８−1によ
り第２の超伝導性信号線の始端に接続される。従
つて、駆動信号は第１の回路群から第２の回路群
へ伝送され、再び信号の復路を形成する配線２５
→２６→２７→２８へとコンタクト３４〜３６を
介して伝送される。第２の超伝導性信号線の終端
は、結合線９−1により第１の回路群の配線２９
へ接続され、配線２９はコンタクト３７を介して
駆動回路３−1の他端である対向電極１１へ接続
されている。第２の回路群を形成する場合、配
線、コンタクト、絶縁層等は第１の回路群に準じ
る。以上のように、信号は第１の回路群と第２の
回路群を貫ぬいて閉ループをなして流れることが
でき、信号線の戻り線は特に必要がない。なお、
高速信号の伝送を波形歪を縮小にして行うため
に、信号電流の影像電流が流れる第１おおよび第
２の超伝導性接地板１，２が結合線８−1，８−2
の近傍で連続するように、両接地板を接続した場
合を図示した。 FIG. 2 is a sectional view of the main parts of the Josephson chip of the present invention. In the drawings, the dimensions in the thickness direction (same meaning as the height direction) are enlarged to make the drawings easier to see. The first circuit group consisting of the first superconducting signal line 4-1 , the load circuits 5-1a to 5-1d , and the drive circuit 4-1 is formed using a thin film formed by sputtering or the like on the substrate 10. A layer with a thickness of 100 nm is placed on the first superconducting ground plate 1 made of a superconductor such as niobium with a thickness of about 300 nm.
It is arranged through an insulating layer 41 of ~200 nm. SiO with a thickness of several μm to 10 μm is placed on the first circuit group.
After forming an insulating layer 42 made of an insulator such as SiO 2 by sputtering or vapor deposition, a second superconducting ground plate 2 made of a superconductor such as niobium with a thickness of about 300 nm is formed by sputtering or the like. . The second circuit group consisting of the second superconducting signal line 6-1 and load circuits 7-1a to 7-1d has an insulating layer 43 with a thickness of 100 to 200 nm on the second superconducting ground plate 2. placed through. In the first circuit group, the signal image current flows on the surface of the first superconducting ground plate 1, and in the second circuit group, the signal image current flows on the surface of the second superconducting ground plate 2. Similarly, the first circuit group and the second circuit group
The distance between the superconducting ground plate 2 and the superconducting ground plate 2 is set.
A drive circuit 3- in the first circuit group includes a counter electrode 11 made of a superconductor such as niobium with a thickness of about 300 nm, a Josephson junction 12, and a base electrode 13 made of a superconductor such as niobium with a thickness of about 200 nm. The drive signal generated in 1 is transmitted through wiring 21 → 22 → 23 →
24 via contacts 31-33. The terminal end of the first superconducting signal line is connected to the starting end of the second superconducting signal line by a coupling line 8-1 consisting of a superconductor pillar or the like several micrometers square. Therefore, the drive signal is transmitted from the first circuit group to the second circuit group, and again via the wiring 25 that forms the return path of the signal.
→26→27→28 via contacts 34-36. The end of the second superconducting signal line is connected to the wiring 29 of the first circuit group by a coupling line 9-1 .
The wiring 29 is connected via a contact 37 to the counter electrode 11, which is the other end of the drive circuit 3-1 . When forming the second circuit group, wiring, contacts, insulating layers, etc. are similar to those of the first circuit group. As described above, the signal can flow through the first circuit group and the second circuit group in a closed loop, and there is no particular need for a return line for the signal line. In addition,
In order to transmit high-speed signals with reduced waveform distortion, the first and second superconducting grounding plates 1 and 2 through which the image current of the signal current flows are connected to coupling wires 8-1 and 8-2.
The figure shows the case where both ground plates are connected so that they are continuous near the ground plane.
なお、第１の回路群の最上部のパターンと第２
の超伝導性板２との間隔は、第１の回路群を流れ
る信号が第２の超伝導性接地板２上に作る影像電
流が回路動作に影響しないように設定される。第
１の回路群と第２の接地板の間隔は、従来知られ
ている回路群のパターン厚１〜2μｍの回路に対
して、10μｍ前後必要である。さらに結合線８−
１，９−1を通すために第２の超伝導性接地板２に
設けられる貫通孔は配線中の信号の伝搬に影響を
及ぼさないように設定される。次に、配線２１〜
２９の幅寸法は伝送線路の特性インピーダンスを
考慮して設定される。この特性インピーダンスは
駆動回路の出力仕様に依存する。具体的には配線
の幅が数マイクロメータ程度となるように各回路
定数が設定される。 Note that the top pattern of the first circuit group and the second
The distance between the superconducting ground plate 2 and the superconducting ground plate 2 is set such that the image current created by the signal flowing through the first circuit group on the second superconducting ground plate 2 does not affect the circuit operation. The distance between the first circuit group and the second ground plane is required to be approximately 10 μm for a conventionally known circuit group having a pattern thickness of 1 to 2 μm. Furthermore, the connecting line 8-
The through holes provided in the second superconducting grounding plate 2 for passing the wires 1 and 9-1 are set so as not to affect the propagation of signals in the wiring. Next, wiring 21~
The width dimension of 29 is set in consideration of the characteristic impedance of the transmission line. This characteristic impedance depends on the output specifications of the drive circuit. Specifically, each circuit constant is set so that the width of the wiring is approximately several micrometers.
第２図において、配線２１〜２９の構造と配置
は、模式的に示してある。実際の回路における超
伝導性伝送線路の構造は、ジヨセフソン接合等を
含んだ複雑な構造となる。又駆動回路から出た駆
動信号が第１の超伝導性信号線から第２の超伝導
性信号線を経て駆動回路へ戻つてくる場合につい
て説明したが、第２から第１へと信号が流れるよ
うにしてもよいのは明白なことである。以上の実
施例において、回路群は２層に重ねて配置されて
いたが、回路群を３層以上に重ねるようにしても
よいことも改めて説明するまでもない。なお、本
発明を記憶回路に適用した場合、信号線と直交す
る方向の信号線には戻り線が必要となるが、その
場合には信号線２２〜２４、コンタクト３１〜３
３と直交する方向の信号線の終端を抵抗等を介し
て接地する回路方式で駆動すればよい。回路群を
４層に重ねて本発明を実施すると、行と列両方向
の信号線の戻り線が不要となることも明らかであ
る。 In FIG. 2, the structure and arrangement of the wirings 21 to 29 are schematically shown. The structure of a superconducting transmission line in an actual circuit is a complicated structure that includes Josephson junctions and the like. Also, we have explained the case where the drive signal output from the drive circuit returns to the drive circuit from the first superconducting signal line via the second superconducting signal line, but the signal flows from the second to the first. It is obvious that you can do this. In the above embodiments, the circuit groups are arranged in two layers, but it goes without saying that the circuit groups may be arranged in three or more layers. Note that when the present invention is applied to a memory circuit, a return line is required for the signal line in the direction perpendicular to the signal line, but in that case, the signal lines 22 to 24 and the contacts 31 to 3
The signal line may be driven by a circuit system in which the terminal end of the signal line in the direction perpendicular to 3 is grounded via a resistor or the like. It is also clear that if the present invention is implemented by stacking circuit groups in four layers, return lines for signal lines in both the row and column directions become unnecessary.
以上説明したように本発明は、超伝導性伝送線
路で３次元的な閉ループを構造することにより、
信号線に戻り線が不要となり、ジヨセフソン接合
装置の集積度及び動作速度が向上する効果があ
る。更に、構造が簡単となるので製造歩留り及び
信頼性が向上する効果もある。
As explained above, the present invention constructs a three-dimensional closed loop using superconducting transmission lines.
There is no need for a return line in the signal line, which has the effect of improving the degree of integration and operating speed of the Josephson junction device. Furthermore, since the structure is simplified, manufacturing yield and reliability are improved.
第１図は本発明の一実施例の概略を説明するた
めの斜視模式図、第２図は本発明の一実施例のジ
ヨセフソン・チツプの主要部の断面図である。
１……第１の超伝導性接地板、２……第２の超
伝導性接地板、３−1，３−2……駆動回路、４−
１，４−2……第１の超伝導性信号線、５−1a〜５
−1d，５−2a〜５−2d……負荷回路、６−1，６−
２……第２の超伝導性信号線、８−１，８−2，９
−1，９−2……結合線、１０……基板、１３……
対向電極、１２……ジヨフセソン接合、１３……
基部電極、２１〜２９……配線、３１〜３７……
コントクト、４１〜４３……絶縁層。
FIG. 1 is a schematic perspective view for explaining the outline of an embodiment of the present invention, and FIG. 2 is a sectional view of the main part of a Josephson chip according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First superconducting ground plate, 2... Second superconducting ground plate, 3-1 , 3-2 ... Drive circuit, 4-
1,4-2 ...first superconducting signal line, 5-1a to 5
- 1d , 5- 2a ~ 5- 2d ...Load circuit, 6- 1 , 6-
2 ...Second superconducting signal line, 8-1, 8-2 , 9
- 1 , 9- 2 ... bonding line, 10 ... board, 13 ...
Counter electrode, 12... Jiofuseson junction, 13...
Base electrode, 21-29... Wiring, 31-37...
Contact, 41-43...Insulating layer.
Claims (1)
を介して配置された第１の複数の負荷回路を駆動
する第１の超伝導性信号線と、第２の超伝導性接
地板の一主表面上に他の絶縁層を介して配置され
た第２の複数の負荷回路を駆動する第２の超伝導
性信号線と、前記第１、第２の超伝導性信号線に
駆動信号を供給するジヨセフソン接合を含む駆動
回路とが、前記第１または第２の超伝導性接地板
のいずれか一方に設けられた貫通孔内を通る結合
線で結ばれて閉ループを構成し、前記第１の超伝
導性信号線または前記第２の超伝導性信号線のい
づれか一方を信号の往路とし他方を信号の復路と
したことを特徴とするジヨセフソン接合装置。1 A first superconducting signal line for driving a first plurality of load circuits disposed on one main surface of a first superconducting ground plate with an insulating layer interposed therebetween; A second superconducting signal line for driving a second plurality of load circuits disposed on one main surface of the ground plane via another insulating layer, and a second superconducting signal line for driving the first and second superconducting signal lines A drive circuit including a Josephson junction for supplying a drive signal is connected with a coupling line passing through a through hole provided in either the first or second superconducting ground plate to form a closed loop; A Josephson junction device characterized in that either the first superconducting signal line or the second superconducting signal line is used as an outgoing signal path, and the other is used as a returning signal path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61077005A JPS62232981A (en) | 1986-04-02 | 1986-04-02 | Josephson junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61077005A JPS62232981A (en) | 1986-04-02 | 1986-04-02 | Josephson junction device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62232981A JPS62232981A (en) | 1987-10-13 |
| JPH0545075B2 true JPH0545075B2 (en) | 1993-07-08 |
Family
ID=13621647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61077005A Granted JPS62232981A (en) | 1986-04-02 | 1986-04-02 | Josephson junction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62232981A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5845194B2 (en) * | 1980-07-11 | 1983-10-07 | 日本電信電話株式会社 | Superconducting integrated circuit and its manufacturing method |
| JPS58147181A (en) * | 1982-02-26 | 1983-09-01 | Fujitsu Ltd | Josephson integrated circuit device |
-
1986
- 1986-04-02 JP JP61077005A patent/JPS62232981A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62232981A (en) | 1987-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5817543A (en) | Method of constructing an integrated circuit memory | |
| US4254445A (en) | Discretionary fly wire chip interconnection | |
| JPS60134440A (en) | Semiconductor integrated circuit device | |
| JP3417808B2 (en) | Wiring structure of LSI package | |
| JP3604884B2 (en) | Semiconductor memory device and method of arranging internal structure thereof | |
| JPH0545075B2 (en) | ||
| JPH0565069B2 (en) | ||
| JPH0556864B2 (en) | ||
| JPS63293941A (en) | Semiconductor integrated circuit device | |
| US4935637A (en) | Linear element array with wire bonding arrangement | |
| JP2755239B2 (en) | Package for semiconductor device | |
| JPS61224341A (en) | Semiconductor integrated circuit device | |
| JP2940045B2 (en) | Semiconductor integrated circuit | |
| JP3186715B2 (en) | Semiconductor integrated circuit device | |
| CN220173719U (en) | A superconducting quantum chip | |
| JPH0728133B2 (en) | Circuit board | |
| JPH04338683A (en) | Superconducting integrated circuit element and mounting method therefor | |
| JPH0348455A (en) | Semiconductor device | |
| JPS62263653A (en) | Manufacture of semiconductor integrated circuit device | |
| JP3262426B2 (en) | Layout method for semiconductor integrated circuit device | |
| JPH03169073A (en) | Semiconductor integrated circuit device | |
| JPS61230340A (en) | Semiconductor integrated circuit device | |
| JPH0719778B2 (en) | Semiconductor integrated circuit device | |
| JPH0556874B2 (en) | ||
| JPS601844A (en) | Semiconductor integrated circuit device |