JPH0545092B2 - - Google Patents
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- Publication number
- JPH0545092B2 JPH0545092B2 JP1133486A JP1133486A JPH0545092B2 JP H0545092 B2 JPH0545092 B2 JP H0545092B2 JP 1133486 A JP1133486 A JP 1133486A JP 1133486 A JP1133486 A JP 1133486A JP H0545092 B2 JPH0545092 B2 JP H0545092B2
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- transistor
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- field effect
- gate
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- 230000005669 field effect Effects 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプラズマ表示装置の如き大容量負荷の
駆動に適する高電圧デイジタル制御信号出力回路
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage digital control signal output circuit suitable for driving a large capacity load such as a plasma display device.
プラズマ表示装置のような大容量負荷を駆動す
るには高電圧のデイジタル制御信号が必要である
が、この制御信号は、通常、PNPバイポーラ・
トランジスタとＮチヤネル形電界効果トランジス
タとを一つの基板上に複合形成した所謂バイ・モ
ス（Bi−MOS）構造の半導体回路により発生さ
れる。これはＰ，N2つのチヤネル形電界効果ト
ランジスタを双方に高耐圧特性をもたせて一つの
基板上に形成することが困難なことに起因し、高
耐圧のＣ−MOS半導体装置が容易に得られない
ことによる。従つて、Ｐチヤネル形に比し、動作
速度、電流容量共に有利なＮチヤネル形のものが
２個準備され、その一つにはPNPバイポーラ・
トランジスタからなる入力段が挿入されプツシユ
プル回路に構成されるのが通常である。
High-voltage digital control signals are required to drive large capacitance loads such as plasma display devices, and these control signals are typically PNP bipolar
It is generated by a semiconductor circuit having a so-called Bi-MOS (Bi-MOS) structure in which a transistor and an N-channel field effect transistor are compositely formed on one substrate. This is because it is difficult to form two P and N channel field effect transistors on a single substrate with both having high breakdown voltage characteristics, and it is not easy to obtain a high breakdown voltage C-MOS semiconductor device. It depends. Therefore, two N-channel types, which are advantageous in operating speed and current capacity compared to the P-channel type, have been prepared, one of which is the PNP bipolar type.
Usually, an input stage consisting of a transistor is inserted to form a push-pull circuit.
第２図に従来の高圧デイジタル制御信号出力回
路を示す。 FIG. 2 shows a conventional high voltage digital control signal output circuit.
この場合、PNPバイポーラ・トランジスタQ1
はエミツタ接地であり、そのベース電位を信号入
力時電源から通ずる電流による抵抗Ｒ１の両端電
圧によつて制御されて導通し、Ｎチヤネル形電界
効果トランジスタQ4のゲートおよびゲート、ソ
ース間に接続されたツエナー・ダイオードD1の
カソードに電源電位VDDをそれぞれ印加してこれ
を導通せしめるよう機能する。 In this case, PNP bipolar transistor Q 1
has a grounded emitter, and its base potential is controlled by the voltage across the resistor R1 due to the current flowing from the power supply when a signal is input. The function is to apply the power supply potential V DD to the cathodes of the Zener diodes D 1 and to make them conductive.
このプツシユプル回路は、信号入力の極性に応
答してＮチヤネル形電界効果トランジスタQ2，
Q4の何れか一つを導通させ、大きな容量負荷に
対する充電または放電作用を行ない得るので、Ｃ
−MOS回路に代わる高電圧のデイジタル制御信
号発生回路として用いられている。 This push-pull circuit responds to the polarity of a signal input by connecting N-channel field effect transistors Q 2 ,
By making any one of Q 4 conductive, it is possible to charge or discharge a large capacitive load, so C
-Used as a high-voltage digital control signal generation circuit in place of MOS circuits.
しかしながら、この従来回路は、PNPバイポ
ーラ・トランジスタのベース電位制御に抵抗回路
を用いるので、抵抗損失による電力消費が大き
く、また、プラズマ表示装置の如き大容量負荷が
必要とする高い駆動電圧を出力することが容易で
ないという問題点を有する。
However, since this conventional circuit uses a resistor circuit to control the base potential of the PNP bipolar transistor, it consumes a large amount of power due to resistance loss, and also outputs the high driving voltage required by a large capacitance load such as a plasma display device. The problem is that it is not easy to do so.
本発明の目的は、上記の情況に鑑み、きわめて
僅少の消費電力で大容量負荷を駆動するに充分な
高電圧デイジタル制御信号を出力し得る高電圧デ
イジタル制御信号出力回路を提供することであ
る。 SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a high voltage digital control signal output circuit capable of outputting a high voltage digital control signal sufficient to drive a large capacity load with extremely low power consumption.
本発明の高電圧デイジタル制御信号出力回路
は、電源の高圧側および低圧側にエミツタおよび
ソースをそれぞれ接続し且つコレクタおよびドレ
インを互いに接続して前記電源の両端子間に直列
挿入されるPNPバイポーラ・トランジスタと第
１のＮチヤネル形電界効果トランジスタの直列回
路と、第１の信号入力および第２の信号入力とを
入力とするAND回路と、このAND回路の出力に
ゲートを接続し電源の低圧側にソースを接続し
PNPトランジスタのベースにドレインを接続し
た第２のＮチヤネル形電界効果トランジスタと、
前記第１の入力信号を入力に接続し前記第１のＮ
チヤネル形電界効果トランジスタのゲートに出力
を接続したインバータ回路と、電源の高圧側にド
レインを接続し、出力端子にソースを接続し
PNPトランジスタのコレクタにゲートを接続し
た第３のＮチヤネル形電界効果トランジスタと、
第３のＮチヤネル形電界効果トランジスタのゲー
トにカソードを接続し、ソースにアノードを接続
したツエナーダイオードと、出力端子と電源の低
圧側との間に接続された容量負荷とを含む。
The high-voltage digital control signal output circuit of the present invention has a PNP bipolar circuit inserted in series between both terminals of the power supply, with the emitter and source connected to the high-voltage side and low-voltage side of the power supply, respectively, and the collector and drain connected to each other. A series circuit of a transistor and a first N-channel field effect transistor, an AND circuit whose inputs are a first signal input and a second signal input, and a gate connected to the output of this AND circuit, which connects a gate to the low voltage side of the power supply. connect the source to
a second N-channel field effect transistor whose drain is connected to the base of the PNP transistor;
connecting the first input signal to an input of the first N
An inverter circuit has an output connected to the gate of a channel field effect transistor, a drain connected to the high voltage side of the power supply, and a source connected to the output terminal.
a third N-channel field effect transistor whose gate is connected to the collector of the PNP transistor;
It includes a Zener diode having a cathode connected to the gate and an anode connected to the source of the third N-channel field effect transistor, and a capacitive load connected between the output terminal and the low voltage side of the power supply.
即ち、本発明によれば、プツシユプル回路の
PNPバイポーラトランジスタのベース電位を制
御する回路のＮチヤネル形電界効果トランジスタ
のゲート電位を制御する信号入力として、第１の
信号入力と第２の信号入力とのAND出力を用い
ることにより、任意の適切なタイミング、パルス
幅のON時間の設定が可能となり、PNPトランジ
スタのベース電位を制御する回路における損失電
力を大幅に低減することを可能とするものであ
る。 That is, according to the present invention, the push-pull circuit
By using the AND output of the first signal input and the second signal input as the signal input for controlling the gate potential of the N-channel field effect transistor of the circuit that controls the base potential of the PNP bipolar transistor, any appropriate This makes it possible to set the ON time of the timing and pulse width, making it possible to significantly reduce the power loss in the circuit that controls the base potential of the PNP transistor.
第１図は、本発明の一実施例を示す接続回路図
である。本実施例では、電源VDDおよびVSS間に
直列接続されたPNPバイポーラトランジスタQ1
およびＮチヤネル形電界効果トランジスタQ2と、
第１の信号入力端子VIN1と第２の信号入力端子
VIN2とを入力とするAND回路Ｎ１と、ゲートを
Ｎ１の出力に、ソースを電源VSSに、ドレインを
PNPトランジスタQ1のベースに接続するＮチヤ
ネル形電界効果トランジスタQ3と、信号入力
VIN1とトランジスタQ2のゲートとの間に接続さ
れたインバータ回路Ｎ２と、トランジスタQ1の
コレクタにゲートを接続し、トランジスタQ1，
Q2の直列回路の回路節点Ｐ１にカソードを接続
するツエナ・ダイオードＤ１のアノードにソース
を接続するＮチヤネル形トランジスタQ4と、ト
ランジスタQ4のソースに接続される出力端子
VOUTと電源VSS端子との間に接続された容量負荷
C1とを含む。
FIG. 1 is a connection circuit diagram showing one embodiment of the present invention. In this example, a PNP bipolar transistor Q 1 is connected in series between the power supplies V DD and V SS .
and an N-channel field effect transistor Q2 ,
First signal input terminal V IN1 and second signal input terminal
AND circuit N1 whose input is V IN2 , the gate is the output of N1, the source is the power supply V SS , and the drain is
N-channel field effect transistor Q 3 connected to the base of PNP transistor Q 1 and signal input
An inverter circuit N2 is connected between V IN1 and the gate of the transistor Q2 , and the gate is connected to the collector of the transistor Q1 , and the transistors Q1 ,
An N-channel transistor Q4 whose cathode is connected to the circuit node P1 of the series circuit of Q2 , whose source is connected to the anode of the Zener diode D1, and an output terminal connected to the source of the transistor Q4 .
Capacitive load connected between V OUT and power supply V SS pin
Including C 1 .
第３図は本発明の実施例における入出力波形の
一例であり、同図ａ，ｂはそれぞれVIN1，VIN2の
入力波形を示し、同図ｃ，ｄ及びｅはそれぞれ
AND路Ｎ１、インバータ回路Ｎ２、出力端子
VOUTの出力波形を示す。 FIG. 3 is an example of input/output waveforms in the embodiment of the present invention, where a and b in the figure show the input waveforms of V IN1 and V IN2 , respectively, and c, d, and e in the figure show the input waveforms of V IN1 and V IN2, respectively.
AND path N1, inverter circuit N2, output terminal
Shows the output waveform of V OUT .
信号入力端子VIN1およびVIN2にはそれぞれ第３
図ａ，ｂに示す如き矩形波信号が入力される。
VIN1の入力信号が“０”から“１”に立上り、ほ
ぼ同時にVIN2の入力信号も“０”から“１”に立
上ることにより、AND回路Ｎ１の出力も第３図
ｃに示すように“０”から“１”に立上り、トラ
ンジスタQ3がONし、PNPバイポーラトランジ
スタQ1のベースが深くバイアスされONする。ト
ランジスタQ1のコレクタ電流はトランジスタQ4
のゲート容量を充電し、ツエナーダイオードＤ１
のカソードに電源VDDの電圧を印加するよう動作
する。トランジスタQ4がゲートに加わるツエナ
ーダイオードＤ１のツエナ電圧でONすると容量
負荷C1はトランジスタQ4のON電流により、大き
な電流で充電され、その蓄積電荷量を増大させて
高電圧を発生させ、出力端子VOUTから第３図ｅ
に示すように“１”レベルの外部制御信号を出力
する。 Signal input terminals V IN1 and V IN2 each have a third
Rectangular wave signals as shown in Figures a and b are input.
Since the input signal of V IN1 rises from "0" to "1" and the input signal of V IN2 also rises from "0" to "1" at the same time, the output of AND circuit N1 also changes as shown in Figure 3c. The signal rises from "0" to "1", transistor Q3 turns on, and the base of PNP bipolar transistor Q1 is deeply biased and turns on. The collector current of transistor Q 1 is the collector current of transistor Q 4
charges the gate capacitance of Zener diode D1
It operates to apply the voltage of the power supply V DD to the cathode of the When the transistor Q4 is turned on by the Zener voltage of the Zener diode D1 applied to the gate, the capacitive load C1 is charged with a large current by the ON current of the transistor Q4 , increasing the amount of accumulated charge and generating a high voltage, which outputs From terminal V OUT to Figure 3 e
As shown in the figure, a "1" level external control signal is output.
ついで、VIN2の入力信号が“１”から“０”に
立下がると、AND回路Ｎ１の出力が“１”から
“０”になり、トランジスタQ3はOFF、トランジ
スタQ1もOFFとなるが、トランジスタQ4のゲー
ト容量の蓄積電荷が消滅するまでの期間、トラン
ジスタQ4はONであり、トランジスタQ4がOFF
となつた後も負荷が容量なので急激な電位の低下
は起こらず、短時間ならば、十分出力“１”状態
を保持する。 Next, when the input signal of V IN2 falls from "1" to "0", the output of AND circuit N1 changes from "1" to "0", transistor Q3 turns OFF, and transistor Q1 also turns OFF. , until the accumulated charge in the gate capacitance of transistor Q 4 disappears, transistor Q 4 is ON and transistor Q 4 is OFF.
Since the load is a capacitor, even after this occurs, a sudden drop in potential does not occur, and the output "1" state is sufficiently maintained for a short period of time.
従つて、トランジスタQ4のプツシユ電流によ
り容量負荷C1を充電するのに必要にして十分な
パルス幅の入力信号を定め、信号入力端子に印加
することによつて、PNPトランジスタQ1のON
期間が短くなり、その間に抵抗回路で生ずる損失
電力を大幅に低減することが可能である。 Therefore, by determining an input signal with a pulse width necessary and sufficient to charge the capacitive load C1 with the push current of the transistor Q4 , and applying it to the signal input terminal, the PNP transistor Q1 is turned on.
The period is shortened, and it is possible to significantly reduce the power loss occurring in the resistor circuit during that period.
信号入力端子VIN1の入力信号が“１”から
“０”に立下がるとインバータＮ２の出力が第３
図ｄに示すように“０”から“１”に立上りトラ
ンジスタQ2がONし、容量負荷C1の蓄積電荷をツ
エナダイオードＤ１を介して電源VSS（地気）へと
放電せしめる。即ち、出力端子VOUTから“０”
の外部制御信号が出力される。この間、AND回
路Ｎ１の出力はVIN２の入力信号の状態にかかわ
らず“０”を保持しトランジスタQ3，Q1，Q4と
もにOFF状態にある。 When the input signal of signal input terminal V IN1 falls from “1” to “0”, the output of inverter N2
As shown in FIG. d, the transition from "0" to "1" causes the transistor Q2 to turn on, discharging the accumulated charge in the capacitive load C1 to the power supply VSS (earth) via the Zener diode D1. In other words, “0” from the output terminal V OUT
An external control signal is output. During this time, the output of the AND circuit N1 remains at "0" regardless of the state of the input signal of V IN 2, and the transistors Q 3 , Q 1 , and Q 4 are all in the OFF state.
本実施例回路の模疑実験結果によれば、トラン
ジスタQ4のON時間は従来の信号入力端子VIN1の
みを用いた場合のON時間に比べ１／４程度で十
分、容量負荷C1を充電可能である。 According to the simulation results of this example circuit, the ON time of the transistor Q 4 is approximately 1/4 of the ON time when only the conventional signal input terminal V IN1 is used, which is enough to charge the capacitive load C 1. It is possible.
尚、本実施例で信号入力端子VIN2に信号入力端
子VIN1の２倍の周波数のパルスが入力されている
のは、信号入力端子VIN2に印加される入力信号を
変更せずに信号入力端子VIN1のみに印加される入
力信号の位相を反転させることにより出力信号
VOUTに得られる出力信号の位相を反転すること
が可能とするためである。 In addition, in this embodiment, the reason why a pulse with twice the frequency of the signal input terminal V IN1 is input to the signal input terminal V IN2 is that the signal is input without changing the input signal applied to the signal input terminal V IN2 . Output signal by inverting the phase of the input signal applied only to terminal V IN1
This is to enable the phase of the output signal obtained at V OUT to be inverted.
以上の様に、本発明による回路を用いることに
より、適切なタイミングとパルス幅の入力信号を
用いて、高電圧デイジタル制御信号回路における
損失電力の大幅な低減を行なうことが可能であ
る。 As described above, by using the circuit according to the present invention, it is possible to significantly reduce the power loss in a high voltage digital control signal circuit by using an input signal with appropriate timing and pulse width.
また、本発明による回路を使用する場合、信号
入力端子VIN1，VIN2に本実施例のように別々の波
形を入力することが出来ない場合においても信号
入力端子VIN2を“１”状態に固定して用いること
により従来の回路と同じ動作が可能であるため、
従来の回路に比べ、汎用性は失なわれず使用する
条件、必要度に応じて適切な波形を入力すること
により各種の利用法が可能である。 Furthermore, when using the circuit according to the present invention, even when it is not possible to input separate waveforms to the signal input terminals V IN1 and V IN2 as in this embodiment, the signal input terminal V IN2 is kept in the "1" state. Since it can operate in the same way as conventional circuits by being fixed,
Compared to conventional circuits, this circuit does not lose its versatility and can be used in a variety of ways by inputting appropriate waveforms according to usage conditions and needs.
以上詳細に説明したように、本発明によれば、
きわめて僅少の消費電力で充分な駆動能力をもつ
デイジタル制御信号を出力し得る回路を集積回路
内に容易に形成し得るので、プラズマ表示装置の
如き大容量の負荷駆動回路として顕著な効果を奏
し得る。
As explained in detail above, according to the present invention,
Since a circuit capable of outputting a digital control signal with sufficient driving capability with very little power consumption can be easily formed in an integrated circuit, it can be used as a large-capacity load driving circuit such as a plasma display device. .
第１図は本発明の一実施例を示す接続回路図、
第２図は従来の高電圧デイジタル制御信号出力回
路の接続回路図、第３図ａ〜ｅは本発明の実施例
における入出力波形の一例を示す波形図である。
Q1……PNPバイポーラ・トランジスタ、Q2〜
Q4……Ｎチヤネル形電界効果トランジスタ、C1
……容量負荷、Ｄ１……ツエナダイオード、Ｒ１
……抵抗、VIN1……信号入力端子、VIN2……信号
入力端子、VOUT……出力端子、VDD，VSS……電
源、Ｎ１……AND回路、Ｎ２……インバータ回
路。
FIG. 1 is a connection circuit diagram showing an embodiment of the present invention;
FIG. 2 is a connection circuit diagram of a conventional high voltage digital control signal output circuit, and FIGS. 3 a to 3 e are waveform diagrams showing examples of input and output waveforms in an embodiment of the present invention. Q 1 ...PNP bipolar transistor, Q 2 ~
Q 4 ...N-channel field effect transistor, C 1
... Capacitive load, D1 ... Zener diode, R1
...Resistor, V IN1 ... Signal input terminal, V IN2 ... Signal input terminal, V OUT ... Output terminal, V DD , V SS ... Power supply, N1 ... AND circuit, N2 ... Inverter circuit.
Claims (1)
ソースをそれぞれ接続し且つコレクタおよびドレ
インを互いに接続して前記電源の両端子間に直列
挿入されるPNPバイポーラ・トランジスタと第
１のＮチヤネル形電界効果トランジスタの直列回
路と、第１の信号入力および第２の信号入力とを
入力とするAND回路と、該AND回路の出力にゲ
ートを接続し電源の低圧側にソースを接続し前記
PNPトランジスタのベースにドレインを接続し
た第２のＮチヤネル形電界効果トランジスタと、
前記第１の信号入力を入力に接続し前記第１のＮ
チヤネル形電界効果トランジスタのゲートに出力
を接続したインバータ回路と、前記電源の高圧側
にドレインを接続し、出力端子にソースを接続し
前記PNPトランジスタのコレクタにゲートを接
続した第３のＮチヤネル形電界効果トランジスタ
と、前記第３のＮチヤネル形電界効果トランジス
タのゲートにカソードを接続しソースにアノード
を接続したツエナーダイオードと、前記出力端子
と前記電源の低圧側との間に接続された容量負荷
とを含むことを特徴とする高電圧デイジタル制御
信号出力回路。1. A PNP bipolar transistor and a first N-channel field effect transistor inserted in series between both terminals of the power source, with the emitter and source connected to the high voltage side and low voltage side of the power source, respectively, and the collector and drain connected to each other. an AND circuit whose inputs are a series circuit, a first signal input, and a second signal input; a gate is connected to the output of the AND circuit, and a source is connected to the low voltage side of the power supply.
a second N-channel field effect transistor whose drain is connected to the base of the PNP transistor;
connecting the first signal input to an input of the first N
an inverter circuit in which the output is connected to the gate of the channel field effect transistor; and a third N-channel type in which the drain is connected to the high voltage side of the power supply, the source is connected to the output terminal, and the gate is connected to the collector of the PNP transistor. a field effect transistor, a Zener diode having a cathode connected to the gate and an anode connected to the source of the third N-channel field effect transistor, and a capacitive load connected between the output terminal and the low voltage side of the power supply. A high voltage digital control signal output circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1133486A JPS62169518A (en) | 1986-01-21 | 1986-01-21 | Output circuit for high voltage digital control signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1133486A JPS62169518A (en) | 1986-01-21 | 1986-01-21 | Output circuit for high voltage digital control signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169518A JPS62169518A (en) | 1987-07-25 |
| JPH0545092B2 true JPH0545092B2 (en) | 1993-07-08 |
Family
ID=11775133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1133486A Granted JPS62169518A (en) | 1986-01-21 | 1986-01-21 | Output circuit for high voltage digital control signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169518A (en) |
-
1986
- 1986-01-21 JP JP1133486A patent/JPS62169518A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62169518A (en) | 1987-07-25 |
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