JPH0546099B2 - - Google Patents
Info
- Publication number
- JPH0546099B2 JPH0546099B2 JP59092442A JP9244284A JPH0546099B2 JP H0546099 B2 JPH0546099 B2 JP H0546099B2 JP 59092442 A JP59092442 A JP 59092442A JP 9244284 A JP9244284 A JP 9244284A JP H0546099 B2 JPH0546099 B2 JP H0546099B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- manufacturing
- bonded
- gas atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
- H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
- H10W15/01—Manufacture or treatment
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、内部に誘電体層や他と異なる不純物
ドープ層等の変性層が形成された半導体基板を製
造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor substrate in which a modified layer such as a dielectric layer or a layer doped with a different impurity is formed.
半導体装置においては、pn接合の形成や絶縁
等の目的で、酸化や不純物拡散等の技術により半
導体基板結晶を変性させることが行われる。ま
た、金属、誘電体、半導体等を各種の膜形成技術
により堆積、成長させることも行われる。しかし
これらの技術は、全て、半導体基板の表面から内
部への拡散、上部への積み上げの技術であり、半
導体基板内部に独立した変性層を埋め込み形成す
ることは極めて困難である。とりわけ、半導体基
板内部に誘電体を埋込むことはむずかしい。
In semiconductor devices, semiconductor substrate crystals are modified by techniques such as oxidation and impurity diffusion for the purpose of forming pn junctions, insulating, and the like. Additionally, metals, dielectrics, semiconductors, etc. are deposited and grown using various film formation techniques. However, all of these techniques involve diffusion from the surface of the semiconductor substrate into the interior and stacking on top, and it is extremely difficult to embed an independent modified layer inside the semiconductor substrate. In particular, it is difficult to embed a dielectric material inside a semiconductor substrate.
例えば、シリコン半導体基板に酸素をイオン注
入して熱処理することにより、内部に酸化物層を
形成する技術が知られている。しかしこの方法で
は、半導体基板内部に深く酸化膜を形成しようと
すると、半導体基板が著しく損傷を受ける。また
イオン注入量や深さの制御の自由度が小さく、所
定の深さ位置に所定の厚みの酸化膜を制御性良く
埋込むことは不可能に近い。 For example, a technique is known in which an oxide layer is formed inside a silicon semiconductor substrate by implanting oxygen ions into the substrate and subjecting it to heat treatment. However, with this method, if an attempt is made to form an oxide film deep inside the semiconductor substrate, the semiconductor substrate will be significantly damaged. Furthermore, the degree of freedom in controlling the amount and depth of ion implantation is small, and it is almost impossible to bury an oxide film of a predetermined thickness at a predetermined depth with good controllability.
また半導体基板内部に高濃度不純物層を埋込む
技術としては、バイポーラICにおいて良く知ら
れているように、半導体基板表面に拡散層を形成
した後、その上にエピタキシヤル成長法により半
導体層を形成する方法がある。しかしこの方法
も、厚いエピタキシヤル層を得ようとすると、長
時間を要し、その間に埋込み層の不純物が大きく
再拡散する、といつた問題がある。 In addition, as a technique for embedding a high concentration impurity layer inside a semiconductor substrate, as is well known for bipolar ICs, a diffusion layer is formed on the surface of the semiconductor substrate, and then a semiconductor layer is formed on it using an epitaxial growth method. There is a way to do it. However, this method also has the problem that it takes a long time to obtain a thick epitaxial layer, during which time impurities in the buried layer are largely re-diffused.
以上のような理由で、半導体素子構造は自ずか
ら制限され、素子特性上の要請を素子の設計に反
映されるために多くの工夫が必要であつた。この
ため半導体基板内部に簡単な工程で、制御性良く
変性層を形成する技術が望まれていた。 For the reasons mentioned above, semiconductor element structures are naturally limited, and many efforts have been made to reflect requirements for element characteristics in element design. For this reason, there has been a desire for a technique for forming a modified layer inside a semiconductor substrate through a simple process and with good controllability.
本発明は上記した点に鑑みてなされたもので、
内部に誘電体等の変性層を簡単且つ制御性良く埋
込み形成することを可能とした半導体基板の製造
方法を提供することを目的とする。
The present invention has been made in view of the above points, and
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that allows a modified layer such as a dielectric material to be embedded therein simply and with good controllability.
本発明者らは、鏡面研磨された2枚の半導体基
板を、充分清浄な雰囲気下でゴミなどの異物を介
在させることなく研磨面どうしを密着させること
により、強固な接合体基板が得られ、更にこれを
200℃以上の温度で熱処理すれば接合強度がより
大になることを見出した。この接合のメカニズム
の詳細は未だ不明であるが、鏡面研磨面に形成さ
れる自然酸化膜が重要な役割を果たしているらし
いことが推測されるに至つている。本発明は、こ
の新しい技術を利用する。
The present inventors have discovered that a strong bonded substrate can be obtained by bringing the polished surfaces of two mirror-polished semiconductor substrates into close contact with each other in a sufficiently clean atmosphere without intervening foreign substances such as dust. Furthermore this
It has been found that heat treatment at a temperature of 200°C or higher increases the bonding strength. Although the details of this bonding mechanism are still unclear, it has been speculated that the natural oxide film formed on the mirror-polished surface seems to play an important role. The present invention takes advantage of this new technology.
すなわち本発明は、内部に変成層が形成された
半導体基板を製造する方法であつて、鏡面研磨さ
れた第1の半導体基板の表面に基板端面に開口す
る溝を形成する工程と、この基板と鏡面研磨され
た第2の半導体基板の研磨面どうしを清浄な雰囲
気下で対向させて密着させ接合体基板を形成する
工程と、前記接合体基板に外力を加えることなく
加熱して接合体基板の接合強度を高める工程と、
この接合体基板をガス雰囲気に晒して前記溝に沿
つて接合体基板内部に変成層を形成する工程とを
備えたことを特徴とする半導体基板の製造方法で
ある。 That is, the present invention is a method for manufacturing a semiconductor substrate in which a metamorphic layer is formed, which includes the steps of forming a groove opening to the end surface of the substrate in the surface of a mirror-polished first semiconductor substrate; A step of forming a bonded substrate by bringing the polished surfaces of mirror-polished second semiconductor substrates into close contact with each other in a clean atmosphere, and heating the bonded substrate without applying any external force to the bonded substrate. A process of increasing bonding strength,
This method of manufacturing a semiconductor substrate includes the step of exposing the bonded substrate to a gas atmosphere to form a metamorphic layer inside the bonded substrate along the groove.
例えば特開昭56−13773号公報に半導体基板の
接合に関する技術が開示されているが、この技術
は接合時に機械的押圧と加熱を要し、塑性変形を
伴うものである。これに対し本発明は、接着自体
は自力的に行われるものであり、外圧は不要であ
る。また接合強度向上のための熱処理時も加圧は
不要であり、塑性変形は生じず、この点で全く異
なる接合技術である。例えば、前記ガス雰囲気と
して酸素を含むガス雰囲気を用いれば、変性層と
して酸化膜を形成することができる。また不純物
を含むガス雰囲気を用いれば、変性層として不純
物ドープ層を形成することができる。 For example, JP-A-56-13773 discloses a technique for bonding semiconductor substrates, but this technique requires mechanical pressing and heating during bonding and is accompanied by plastic deformation. In contrast, in the present invention, the adhesion itself is performed by itself, and no external pressure is required. Furthermore, no pressure is required during heat treatment to improve bonding strength, and no plastic deformation occurs, which is a completely different bonding technology. For example, if a gas atmosphere containing oxygen is used as the gas atmosphere, an oxide film can be formed as the modified layer. Furthermore, if a gas atmosphere containing impurities is used, an impurity-doped layer can be formed as the modified layer.
本発明によれば、2枚の半導体基板を接合させ
た接合体基板を形成するに際し、圧力を加える機
構等は不要であり、鏡面研磨された2枚の基板の
鏡面同志を清浄な雰囲気下で対向させて密着する
のみでよい。このため、接合体基板を容易に形成
することができ、量産性の向上をはかることがで
きる。しかも、変性層は接合体基板の接合部に位
置する溝の露出面のみに選択的に形成されるの
で、変性層を制御性良く形成することができる。
即ち、半導体基板の内部に埋込み形成する変性層
を、簡単に且つ制御性良く実現することができ
る。このようにして得られる半導体基板は、例え
ば変性層を素子分離層とする従来と同様のIC製
造用半導体基板として用いられることは勿論、変
性層により半導体基板の上下を分離した多層構造
IC用の半導体基板として、そのほか種々の用途
に用いられる。
According to the present invention, when forming a bonded substrate in which two semiconductor substrates are bonded together, there is no need for a mechanism to apply pressure, and the mirror surfaces of the two mirror-polished substrates are held together in a clean atmosphere. All you need to do is face them and place them in close contact. Therefore, a bonded substrate can be easily formed, and mass productivity can be improved. Moreover, since the modified layer is selectively formed only on the exposed surface of the groove located at the joint portion of the bonded substrate, the modified layer can be formed with good controllability.
That is, a modified layer buried inside a semiconductor substrate can be easily realized with good controllability. The semiconductor substrate obtained in this way can be used, for example, as a conventional semiconductor substrate for IC manufacturing in which the modified layer serves as an element isolation layer, as well as a multilayer structure in which the upper and lower parts of the semiconductor substrate are separated by the modified layer.
It is used as a semiconductor substrate for ICs and for a variety of other uses.
本発明において、第1の半導体基板の表面に溝
を設けることは、接合体基板を形成した後に変性
層を形成するために必須のものであるが、この溝
は2枚の半導体基板を接合する際に間に気泡が残
留するのを防止する意味もある。接合面に気泡が
残留すると強固な接合が得られないことを本発明
者らは実験的にも確認しており、このことは重要
である。 In the present invention, providing a groove on the surface of the first semiconductor substrate is essential for forming a modified layer after forming a bonded substrate, but this groove is used to bond two semiconductor substrates. It also has the purpose of preventing air bubbles from remaining in between. The present inventors have experimentally confirmed that a strong bond cannot be obtained if air bubbles remain on the bonding surface, and this is important.
〔発明の実施例〕
以下図面を参照して本発明の実施例を説明す
る。第1図a,bは第1のシリコン基板11の平
面図とそのA−A′断面図である。この基板21
の表面は表面粗さ500Å以下に鏡面研磨されてお
り、またその表面には基板端部に開口する溝12
が形成されている。第2図a,bは第2のシリコ
ン基板21であり、この表面も表面粗さ500Å以
下に鏡面研磨されている。またこの基板21の表
面には穴22が形成されている。これらの基板1
1,21を充分洗浄し乾燥させた後、浮遊塵20
個/m3以下の清浄な雰囲気下で第3図に示すよう
に研磨面どうしを密着させ、接合する。この接合
体基板は接合強度を高めるため200℃以上、好ま
しくは1000℃程度で熱処理するのがよいが、本実
施例ではこの熱処理は次の熱工程で兼用する。即
ち接合体基板を、酸素を含むガス雰囲気中で1200
℃で加熱することにより、第4図に示すように溝
12及び穴22の壁面に酸化膜31を形成する。[Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. FIGS. 1a and 1b are a plan view of the first silicon substrate 11 and a cross-sectional view thereof taken along line A-A'. This board 21
The surface is mirror-polished to a surface roughness of 500 Å or less, and there are grooves 12 that open at the edge of the substrate.
is formed. FIGS. 2a and 2b show a second silicon substrate 21, whose surface is also mirror-polished to a surface roughness of 500 Å or less. Further, holes 22 are formed on the surface of this substrate 21. These substrates 1
After thoroughly washing and drying 1 and 21, floating dust 20
As shown in FIG. 3 , the polished surfaces are brought into close contact with each other and bonded in a clean atmosphere with a particle density of less than 1.0 mm/m 3 . This bonded substrate is preferably heat-treated at 200° C. or higher, preferably at about 1000° C., in order to increase the bonding strength, but in this example, this heat treatment is also used in the next heat step. That is, the bonded substrate was heated for 1200 min in an oxygen-containing gas atmosphere.
By heating at .degree. C., an oxide film 31 is formed on the walls of the trenches 12 and holes 22, as shown in FIG.
こうして本実施例によれば、酸化膜31を内部
に埋込み形成したシリコン基板を簡単に形成する
ことができる。この基板は酸化膜31を素子分離
層として通常のIC基板として用いることができ
る。また酸化膜31が基板11,21を完全に電
気的に分離する状態とすれば、多層構造IC基板
としても用いられる。更にまたこの基板を大電力
用半導体素子基板として使う場合等、溝22に冷
却媒体を流して素子の冷却を行うことができる。 In this manner, according to this embodiment, a silicon substrate with the oxide film 31 embedded therein can be easily formed. This substrate can be used as a normal IC substrate with the oxide film 31 as an element isolation layer. Furthermore, if the oxide film 31 completely electrically isolates the substrates 11 and 21, it can also be used as a multilayer IC substrate. Furthermore, when this substrate is used as a high-power semiconductor device substrate, the device can be cooled by flowing a cooling medium through the grooves 22.
なお上記実施例において、第2の基板21の穴
22は必ずしも設けなくてもよい。また第2の基
板21に第1の基板11と同様のパターンで溝を
形成しておいてもよい。 Note that in the above embodiment, the hole 22 in the second substrate 21 does not necessarily need to be provided. Further, grooves may be formed in the second substrate 21 in a pattern similar to that of the first substrate 11.
上記実施例では、変性層として酸化膜を形成し
たが、例えば不純物を含むガス雰囲気を用いて溝
に沿つて不純物ドープ層を形成する場合も本発明
は有効である。更に変性層として酸化膜などを形
成することもできる。 In the above embodiments, an oxide film is formed as the modified layer, but the present invention is also effective, for example, when an impurity-doped layer is formed along the groove using a gas atmosphere containing impurities. Furthermore, an oxide film or the like may be formed as a modified layer.
第1図〜第4図は本発明の一実施例を説明する
ための図であり、第1図a,bは第1のシリコン
基板の平面図とそのA−A′断面図、第2図a,
bは第2のシリコン基板の平面図とそのB−
B′断面図、第3図はこれらの基板を接合した状
態を示す断面図、第4図はその接合体基板内部に
酸化膜を形成した状態を示す断面図である。
11……第1のシリコン基板、12……溝、2
1……第2のシリコン基板、22……穴、31…
…酸化膜(変性層)。
1 to 4 are diagrams for explaining one embodiment of the present invention, in which FIGS. 1a and 1b are a plan view of a first silicon substrate and its A-A' cross-sectional view, and FIG. a,
b is a plan view of the second silicon substrate and its B-
3 is a sectional view showing a state in which these substrates are bonded together, and FIG. 4 is a sectional view showing a state in which an oxide film is formed inside the bonded substrate. 11...first silicon substrate, 12...groove, 2
1... Second silicon substrate, 22... Hole, 31...
...Oxide film (denatured layer).
Claims (1)
する方法であつて、鏡面研磨された第1の半導体
基板の表面に基板端面に開口する溝を形成する工
程と、この基板と鏡面研磨された第2の半導体基
板の研磨面どうしを清浄な雰囲気下で対向させて
密着させ接合体基板を形成する工程と、前記接合
体基板に外力を加えることなく加熱して接合体基
板の接合強度を高める工程と、この接合体基板を
ガス雰囲気に晒して前記溝に沿つて接合体基板内
部に変成層を形成する工程とを備えたことを特徴
とする半導体基板の製造方法。 2 変成層形成時の熱処理と、前記接合体基板の
接合強度を高める工程における熱処理とを兼用す
ることを特徴とする特許請求の範囲第1項記載の
半導体基板の製造方法。 3 前記ガス雰囲気は酸素を含む反応性ガス雰囲
気であり、前記変成層として酸化膜を形成する特
許請求の範囲第1項記載の半導体基板の製造方
法。 4 前記ガス雰囲気は不純物を含む反応性ガス雰
囲気であり、前記変成層として不純物ドープ層を
形成する特許請求の範囲第1項記載の半導体基板
の製造方法。 5 前記接合体基板の接合強度を高める工程にお
ける熱処理が200℃乃至1200℃の温度条件である
ことを特徴とする特許請求の範囲第1項記載の半
導体基板の製造方法。[Scope of Claims] 1. A method for manufacturing a semiconductor substrate in which a metamorphic layer is formed, which comprises the steps of: forming a groove opening to an end surface of the substrate in a mirror-polished first semiconductor substrate; A step of forming a bonded substrate by bringing the polished surfaces of the substrate and a mirror-polished second semiconductor substrate into close contact with each other in a clean atmosphere, and heating the bonded substrate without applying any external force to form the bonded substrate. A method for manufacturing a semiconductor substrate, comprising: increasing the bonding strength of the substrate; and exposing the bonded substrate to a gas atmosphere to form a metamorphic layer inside the bonded substrate along the groove. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the heat treatment during the formation of the metamorphic layer and the heat treatment during the step of increasing the bonding strength of the bonded substrate are used. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the gas atmosphere is a reactive gas atmosphere containing oxygen, and an oxide film is formed as the metamorphic layer. 4. The method of manufacturing a semiconductor substrate according to claim 1, wherein the gas atmosphere is a reactive gas atmosphere containing impurities, and an impurity-doped layer is formed as the metamorphic layer. 5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the heat treatment in the step of increasing the bonding strength of the bonded substrate is performed at a temperature of 200°C to 1200°C.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092442A JPS60236254A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor substrate |
| EP85300953A EP0161740B1 (en) | 1984-05-09 | 1985-02-13 | Method of manufacturing semiconductor substrate |
| DE8585300953T DE3583183D1 (en) | 1984-05-09 | 1985-02-13 | METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE. |
| US06/701,516 US4638552A (en) | 1984-05-09 | 1985-02-14 | Method of manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092442A JPS60236254A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60236254A JPS60236254A (en) | 1985-11-25 |
| JPH0546099B2 true JPH0546099B2 (en) | 1993-07-13 |
Family
ID=14054526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59092442A Granted JPS60236254A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60236254A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2685244B2 (en) * | 1988-09-30 | 1997-12-03 | 株式会社日本自動車部品総合研究所 | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2926741C2 (en) * | 1979-07-03 | 1982-09-09 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Field effect transistor and process for its manufacture |
-
1984
- 1984-05-09 JP JP59092442A patent/JPS60236254A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60236254A (en) | 1985-11-25 |
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