JPH0546575B2 - - Google Patents
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- Publication number
- JPH0546575B2 JPH0546575B2 JP61001443A JP144386A JPH0546575B2 JP H0546575 B2 JPH0546575 B2 JP H0546575B2 JP 61001443 A JP61001443 A JP 61001443A JP 144386 A JP144386 A JP 144386A JP H0546575 B2 JPH0546575 B2 JP H0546575B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- voltage
- substrate
- axis
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000004020 conductor Substances 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 49
- 238000010030 laminating Methods 0.000 claims description 3
- 230000005674 electromagnetic induction Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は平面上の座標位置を決定する装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for determining coordinate positions on a plane.
この分野の先行技術として特公昭49−44540号
に自動座標位置決め装置として開示された発明
(以下従来技術という)がある。第5図は従来技
術の構成を示すブロツク図で、図において1は正
弦波電圧発生回路で、たとえば周波数3kHzの正
弦波を発生する。2はカーソルコイルで正弦波電
圧発生回路1からの電流により、たとえばカーソ
ルコイル2の中心軸を中心とする3kHzの交番磁
界を発生する。3は基準位相信号線で、正弦波発
生回路1で発生する3kHz正弦波電圧の基準位相
を示す電圧を伝送する。4,5はそれぞれ増幅
器、6は90°移相器、7はアナログ加算器、8は
位相測定回路、9はy軸信号処理・位相測定回路
で、回路9には4,5,6,7,8と同一構成の
回路を1組含んでいる。11は格子装置であつ
て、カーソルコイル2によつて発生される交番磁
界の電磁誘導によつて電圧が誘起される導体が格
子状に形成された平面を有する絶縁性基板を4枚
積層して形成される。これら絶縁性基板の厚さは
極めて薄いものであるが、第5図では説明の便宜
のために、格子装置11を構成する絶縁性基板の
厚さを拡大して表示してある。第5図以外の各図
においても絶縁性基板の厚さは拡大して表示す
る。
As a prior art in this field, there is an invention (hereinafter referred to as "prior art") disclosed as an automatic coordinate positioning device in Japanese Patent Publication No. 49-44540. FIG. 5 is a block diagram showing the configuration of the prior art. In the figure, 1 is a sine wave voltage generating circuit, which generates a sine wave with a frequency of, for example, 3 kHz. A cursor coil 2 generates, for example, an alternating magnetic field of 3 kHz centered on the central axis of the cursor coil 2 by the current from the sine wave voltage generating circuit 1. A reference phase signal line 3 transmits a voltage indicating the reference phase of the 3kHz sine wave voltage generated by the sine wave generating circuit 1. 4 and 5 are amplifiers, 6 is a 90° phase shifter, 7 is an analog adder, 8 is a phase measurement circuit, and 9 is a y-axis signal processing/phase measurement circuit. , 8 includes one set of circuits with the same configuration as . Reference numeral 11 denotes a lattice device, which is made up of four laminated insulating substrates each having a plane in which a conductor is formed in a lattice shape, in which a voltage is induced by the electromagnetic induction of the alternating magnetic field generated by the cursor coil 2. It is formed. Although the thickness of these insulating substrates is extremely thin, the thickness of the insulating substrate constituting the grating device 11 is shown enlarged in FIG. 5 for convenience of explanation. In each figure other than FIG. 5, the thickness of the insulating substrate is shown enlarged.
第6図は第5図の格子装置11中の2枚の絶縁
性基板上の導体の格子形状を示す平面図で、実線
で示す11aの蛇行形状(convolute)の導体格
子は第1の絶縁性基板に形成されており、点線で
示す11bの蛇行形状の導体格子は第2の絶縁性
基板に形成されている。2は第5図の2と同じく
円形のカーソルコイルである。第6図に示す導体
格子の長い方の方向をy軸としこれに直角な方向
をx軸とする。第6図に示す例では、導体格子1
1aはy軸方向に平行でx軸方向にD/2の間隔
を置いて配列された平行導体と、隣接した平行導
体の端を交互にその両端で接続して一つの導体格
子に属するすべての導体を直列に接続するための
エンドターンとから構成され、そのピツチはDで
ある。導体格子11bも導体格子11aと同様に
構成されているが、導体格子11aに対して+x
の方向にD/4だけずらして各導体が配列されて
いる。 FIG. 6 is a plan view showing the lattice shape of the conductor on the two insulating substrates in the lattice device 11 of FIG. A meandering conductor grid 11b indicated by dotted lines is formed on the second insulating substrate. 2 is a circular cursor coil like 2 in FIG. The longer direction of the conductor grid shown in FIG. 6 is the y-axis, and the direction perpendicular thereto is the x-axis. In the example shown in FIG.
1a is parallel conductors that are arranged parallel to the y-axis direction and spaced apart by D/2 in the x-axis direction, and the ends of adjacent parallel conductors are connected alternately at both ends to connect all the conductor grids that belong to one conductor grid. It consists of end turns for connecting conductors in series, and its pitch is D. The conductor grid 11b is also configured similarly to the conductor grid 11a, but with respect to the conductor grid 11a, +x
The conductors are arranged shifted by D/4 in the direction of .
カーソルコイル2に周波数fの交流電流を流す
とき導体格子11aに誘起する電圧を考えてみ
る。カーソルコイル2の中心点が導体格子11a
のy軸に平行な導体の直上にあるときは、コイル
2の右半分からその導体に誘起する電圧とコイル
2の左半分からその導体に誘起する電圧との大き
さが同じでその方向が互に反対方向になるため打
消し合つて零となる。導体格子11aの互に隣接
する2つの導体の中央にカーソルコイル2の中心
点が置かれたとき、コイル2の右半分から右側の
導体に誘起する電圧とコイル2の左半分から左側
の導体に誘起する電圧は互に逆方向の電圧となる
が、この両電圧が互に加算されるようにエンドタ
ーンを介して接続されているので、導体格子11
aの誘起電圧は最大となる。 Consider the voltage induced in the conductor grid 11a when an alternating current of frequency f is passed through the cursor coil 2. The center point of the cursor coil 2 is the conductor grid 11a
directly above a conductor parallel to the y-axis, the voltage induced in that conductor from the right half of coil 2 is the same as the voltage induced in that conductor from the left half of coil 2, and their directions are mutual. Since they are in opposite directions, they cancel each other out and become zero. When the center point of the cursor coil 2 is placed at the center of two adjacent conductors of the conductor grid 11a, the voltage induced from the right half of the coil 2 to the right conductor and the voltage induced from the left half of the coil 2 to the left conductor The induced voltages are in opposite directions, but since the two voltages are connected through the end turn so that they are added together, the conductor grid 11
The induced voltage at a becomes maximum.
したがつて、第6図に示すように、導体格子1
1aの一つの導体位置をx=0とすれば、導体格
子11aに誘起される合成電圧VAは
VA=VMsin2πx/Dsin2πft ……(1)
となる。同様にして、導体格子11bに誘起され
る合成電圧VBは
VB=VMsin2π(x−D/4)/Dsin2πft
=−VMsin2πx/Dsin2πft ……(2)
となる。但しVMは誘起電圧の振幅最大値を表す。 Therefore, as shown in FIG.
If the position of one conductor of 1a is x=0, the composite voltage V A induced in the conductor grid 11a is V A =V M sin2πx/Dsin2πft (1). Similarly, the composite voltage V B induced in the conductor grid 11b is V B =V M sin2π(x-D/4)/Dsin2πft = -V M sin2πx/Dsin2πft (2). However, V M represents the maximum amplitude of the induced voltage.
電圧VBを90°移相した電圧VBQは VBQ=VMsin2πx/Dcos2πft ……(3) となり VR=VA+VBQ=VMcos(2πft−2πx/D)……(4) となる。 The voltage V BQ obtained by shifting the phase of the voltage V B by 90° is V BQ = V M sin2πx/D cos2πft ...(3), and V R = V A + V BQ = V M cos (2πft−2πx/D)...(4) becomes.
すなわち、第5図における増幅器4,5の出力
は式(1)、(2)で表わされ、90°移相器6の出力は式
(3)で、アナログ加算器7の出力は式(4)で表わすこ
とができる。基準位相信号線3上の電圧をVRcps
2πftとすれば、位相測定回路8で位相差2πx/Dを
測定し、Dは既知であるからxを算出することが
できる。 That is, the outputs of amplifiers 4 and 5 in FIG. 5 are expressed by formulas (1) and (2), and the output of 90° phase shifter 6 is expressed by formula
In (3), the output of the analog adder 7 can be expressed by equation (4). The voltage on the reference phase signal line 3 is V Rcps
If 2πft, the phase difference 2πx/D is measured by the phase measuring circuit 8, and since D is known, x can be calculated.
y軸信号処理・位相測定回路9においても、同
様にして、カーソルコイル3の中心点のy方向の
座標位置を算出することができる。 Similarly, in the y-axis signal processing/phase measurement circuit 9, the coordinate position of the center point of the cursor coil 3 in the y direction can be calculated.
従来技術による装置は以上のように構成されて
いるので、いわゆるエツヂ効果を消去することが
困難であつた。
Since the conventional device is constructed as described above, it has been difficult to eliminate the so-called edge effect.
すなわち、カーソルコイル2の位置がエンドタ
ーンに近ずくと、エンドターンに誘起される電圧
が大きくなり、式(1)、(2)で表わされる電圧に誤差
電圧として加えられ、式(4)の位相差に誤差が発生
する。従来技術による装置ではエツヂ効果を消去
するための補償用の導体が設けられているが、こ
の補償用の導体を設けることは絶縁性基板上の導
体素子の形状を複雑にし、しかもエツヂ効果を充
分に消去できるものでないという点に問題点があ
つた。 In other words, as the position of the cursor coil 2 approaches the end turn, the voltage induced at the end turn increases and is added as an error voltage to the voltages expressed by equations (1) and (2), resulting in the difference in equation (4). An error occurs in the phase difference. Conventional devices are provided with a compensating conductor to eliminate the edge effect, but providing this compensating conductor complicates the shape of the conductor element on the insulating substrate, and it is difficult to fully eliminate the edge effect. The problem was that it could not be erased immediately.
この発明は以上のような問題点を解決するため
になされたもので、エツヂ効果消去のための補償
用の導体を必要とせず、エツヂ効果の発生するこ
とがない座標位置決定装置を得ることを目的とし
ている。 This invention was made to solve the above problems, and aims to provide a coordinate positioning device that does not require a compensation conductor to eliminate the edge effect and does not generate the edge effect. The purpose is
この発明ではエンドターンによつて平行導体の
端をその両端で交互に接続して一つの導体格子に
属するすべての導体が直列に接続されて蛇行形状
の導体格子を構成することを避け、各平行導体に
誘起する電圧をそれぞれ別々に取り出して演算増
幅器で加算することにし、エンドターンを省略し
た。また、加算のための電圧を集めて演算増幅器
の入力点に接続するための集電導体に誘起される
電圧が誤差として入力されることがないように、
同一の電圧が誘起される集電導体の誘起電圧が打
消し合うような接続とした。
In this invention, the ends of the parallel conductors are alternately connected at both ends by end turns to avoid connecting all the conductors belonging to one conductor grid in series to form a meandering conductor grid, and each parallel conductor We decided to extract the voltages induced in the conductors separately and add them together using an operational amplifier, thereby omitting the end turns. In addition, in order to prevent the voltage induced in the current collecting conductor that collects the voltage for addition and connects it to the input point of the operational amplifier from being input as an error,
The connection was made in such a way that the induced voltages of the current collecting conductors where the same voltage is induced cancel each other out.
エンドターンが存在しないので、エツヂ効果が
発生せず、集電導体に誘起される電圧は互いに消
去される。
Since there are no end turns, no edge effect occurs and the voltages induced in the current collecting conductors cancel each other out.
以下この発明の実施例を図面について説明す
る。第1図はこの発明の一実施例を示すブロツク
図であつて、第5図と同一符号は同一又は相当部
分を示し、41,51はそれぞれ演算増幅器、1
00はこの発明の格子装置である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same symbols as in FIG. 5 indicate the same or corresponding parts, 41 and 51 are operational amplifiers, 1
00 is the grating device of this invention.
格子装置100では従来の格子装置11におけ
る1枚の絶縁性基板を2枚の絶縁性基盤に分けて
構成し、従つて第5図の格子装置11が4枚の絶
縁性基板の積層によつて形成されるとすれば、こ
の発明の格子装置100は8枚の絶縁性基板の積
層によつて形成される。 In the lattice device 100, one insulating substrate in the conventional lattice device 11 is divided into two insulating substrates, so that the lattice device 11 in FIG. 5 is constructed by laminating four insulating substrates. If formed, the grating device 100 of the present invention is formed by laminating eight insulating substrates.
第2図は第1図の格子装置100における絶縁
性基板の積層を示す分解斜視図、第3図及び第4
図は第2図の各絶縁性基板を展開してその導体格
子を示す平面図である。第1図、第2図、第3
図、第4図を通じ10,20,30,40,5
0,60,70,80は各絶縁性基板、116,
216,316,416,516,616,71
6,816,117,217,317,417,
517,617,717,817はそれぞれ接続
端子、101,102,103,104,10
5,201,202,…301,302,…40
1,402,…501,502,…601,60
2,…701,702,…801,802,…は
それぞれ導体、106,107,206,20
7,306,307,406,407,506,
507,606,607,706,707,80
6,807はそれぞれ集電導体、108,10
9,110,111,112,208,…,30
8,…,408,…,508,…,608,…,
708,…,808,…はそれぞれの導体に直列
に挿入され、その導体に誘起した電圧を演算増幅
器で加算するための入力抵抗である。従つてこれ
らの抵抗はすべて等しい値の抵抗値を持つている
ことが必要である。 FIG. 2 is an exploded perspective view showing the lamination of insulating substrates in the grating device 100 of FIG. 1, and FIGS.
The figure is a plan view of each insulating substrate shown in FIG. 2 developed and showing its conductor lattice. Figure 1, Figure 2, Figure 3
Figure, 10, 20, 30, 40, 5 through Figure 4
0, 60, 70, 80 are each insulating substrate, 116,
216, 316, 416, 516, 616, 71
6,816,117,217,317,417,
517, 617, 717, 817 are connection terminals, 101, 102, 103, 104, 10, respectively.
5,201,202,...301,302,...40
1,402,...501,502,...601,60
2,...701,702,...801,802,... are conductors, respectively, 106,107,206,20
7,306,307,406,407,506,
507,606,607,706,707,80
6,807 are current collecting conductors, 108,10 respectively
9,110,111,112,208,...,30
8,...,408,...,508,...,608,...,
708, . . . , 808, . . . are input resistors inserted in series with the respective conductors and used to add the voltages induced in the conductors by the operational amplifier. Therefore, it is necessary that all these resistors have the same resistance value.
絶縁性基板の平面上に固定するx、y直角座標
軸は第3図、第4に図示するように定める。とこ
ろで第3図と第4図とではx軸とy軸とを交換す
れば互に同様になるので、以下第3図について説
明し、第1図のy軸信号処理・位相測定回路9に
入力される第4図の回路については説明を省略す
る。 The x and y orthogonal coordinate axes fixed on the plane of the insulating substrate are determined as shown in FIGS. 3 and 4. By the way, FIG. 3 and FIG. 4 are the same if the x-axis and y-axis are exchanged, so we will explain FIG. Description of the circuit shown in FIG. 4 will be omitted.
説明の便宜のため基板10,20,30,40
を第1、第2、第3、第4の基板と称し、これら
の基板はそれぞれ、y=yeの位置でx軸に平行な
集電導体(第1の導体という、たとえば導体10
6)と、y=ysの位置でx軸に平行な集電導体
(第2の導体という、たとえば導体107)と、
y軸に平行でx軸方向にピツチ間隔Dをもつて配
列され、両端が第1の導体106と第2の導体1
07に接続される複数本の平行導体(たとえば1
01〜105)からなる導体格子と、それぞれの
導体に挿入される抵抗(たとえば108〜11
2)とから構成されている。 For convenience of explanation, substrates 10, 20, 30, 40
are called first, second, third, and fourth substrates, and these substrates are respectively connected to a current collecting conductor (referred to as a first conductor, for example, a conductor 10
6), a current collecting conductor (referred to as a second conductor, for example, conductor 107) parallel to the x-axis at the position y= ys ,
They are parallel to the y-axis and arranged with a pitch interval D in the x-axis direction, with the first conductor 106 and the second conductor 1 at both ends.
Multiple parallel conductors (for example, 1
01 to 105) and a resistor inserted into each conductor (for example, 108 to 11
2).
また、第1の基板10上の導体格子の位置を基
準とすると、第2、第3、第4の基板20,3
0,40上の導体格子の位置は+x方向へそれぞ
れD/2、D/4、3D/4だけずらされている。 Furthermore, when the position of the conductor grid on the first substrate 10 is used as a reference, the positions of the second, third, and fourth substrates 20, 3
The positions of the conductor grids on 0 and 40 are shifted in the +x direction by D/2, D/4, and 3D/4, respectively.
第1図に示すように、第1の基板10の第1の
導体106と第2の基板20の第2の導体207
の接続点(接続端子116と217の短絡点)を
演算増幅器4の反転入力端子に接続し、第1の基
板10の第2の導体107と第2の基板20の第
1の導体206の接続点(接続端子117と21
6の短絡点)を演算増幅器4の非反転入力端子に
接続すると、導体101,102,103,10
4,105に誘起する電圧の総和から導体20
1,202,…に誘起する電圧の総和を減算した
電圧が演算増幅器41の出力となる。すなわち、
基板10と基板20を重ねた導体格子からは第6
図の導体格子11aに相当する電圧を得ることが
でき、基板10と基板20とを重ねた場合はエン
ドターンを必要としないので、エツジ効果は発生
しない。また、カーソルコイル2によつて導体1
06,206に誘起される電圧は互に等しく、こ
れが反対方向に加えられ、導体107,207に
誘起それる電圧は互に等しく、これが反対方向に
加えられるので、集電導体による誤差は発生しな
い。 As shown in FIG. 1, the first conductor 106 of the first substrate 10 and the second conductor 207 of the second substrate 20
The connection point (the short-circuit point between the connection terminals 116 and 217) is connected to the inverting input terminal of the operational amplifier 4, and the second conductor 107 of the first substrate 10 and the first conductor 206 of the second substrate 20 are connected. points (connection terminals 117 and 21
6) to the non-inverting input terminal of the operational amplifier 4, conductors 101, 102, 103, 10
From the sum of the voltages induced on the conductor 20
The voltage obtained by subtracting the sum of the voltages induced in 1, 202, . . . becomes the output of the operational amplifier 41. That is,
From the conductor grid in which the substrates 10 and 20 are stacked, the sixth
A voltage corresponding to the conductor grid 11a in the figure can be obtained, and when the substrates 10 and 20 are stacked, no end turns are required, so no edge effect occurs. Also, the conductor 1 is controlled by the cursor coil 2.
The voltages induced in conductors 107 and 207 are equal and applied in opposite directions, and the voltages induced in conductors 107 and 207 are equal and applied in opposite directions, so no error occurs due to the current collecting conductor. .
同様にして、基板30,40上の導体格子から
演算増幅器51によつて式(2)に示す電圧を得るこ
とができる。 Similarly, the voltage shown in equation (2) can be obtained from the conductor grids on the substrates 30 and 40 by the operational amplifier 51.
演算増幅器41,51以後の回路は第5図に同
一符号で示す回路と同様に動作するので、その説
明を省略する。更に基板50,60,70,80
上の導体格子から41,51,6,7,8と同様
な回路構成を有するy軸信号処理・位相測定回路
9により、カーソルコイル2のy方向の位置を決
定する動作は、基板10〜40上の導体格子から
カーソルコイル2のx方向の位置を決定する動作
と同様であるのでその説明を省略する。 Since the circuits after the operational amplifiers 41 and 51 operate in the same manner as the circuits indicated by the same reference numerals in FIG. 5, their explanation will be omitted. Furthermore, the substrates 50, 60, 70, 80
The operation of determining the position of the cursor coil 2 in the y direction by the y-axis signal processing/phase measuring circuit 9 having the same circuit configuration as the conductor grids 41, 51, 6, 7, and 8 from the upper conductor grid is performed by the substrates 10 to 40. This operation is similar to the operation of determining the x-direction position of the cursor coil 2 from the conductor grid above, so its explanation will be omitted.
ところで、多くの場合、この発明の装置は第2
図に示すように8枚の絶縁性基板を備えている
が、直線上の位置決定を目的として使用する場合
は、たとえばx軸方向の位置を決定するのに必要
な部分だけを備えていれば足り、従つて、第1に
おいて基板50,60,70,80とy軸信号処
理・位相測定回路9が省略された構成もこの発明
の装置として含まれるものである。 By the way, in many cases, the device of this invention
As shown in the figure, it is equipped with 8 insulating substrates, but when using it for the purpose of determining position on a straight line, for example, it is necessary to have only the parts necessary for determining the position in the x-axis direction. Therefore, a configuration in which the substrates 50, 60, 70, 80 and the y-axis signal processing/phase measurement circuit 9 are omitted in the first embodiment is also included as an apparatus of the present invention.
なお、第3図、第4図において抵抗108,1
09,…を導体101,102,…と別に示した
が、導体101,102…を互に等しい抵抗値を
有する導体で構成すれば特に抵抗を挿入しなくて
もよい。 In addition, in FIGS. 3 and 4, the resistors 108, 1
09, . . . are shown separately from the conductors 101, 102, . . . However, if the conductors 101, 102, .
以上のようにこの発明によれば、簡単な回路に
よつてエツヂ効果が完全に消去できる座標位置決
定装置を得ることができる。
As described above, according to the present invention, it is possible to obtain a coordinate position determining device in which edge effects can be completely eliminated using a simple circuit.
第1図はこの発明の一実施例を示すブロツク
図、第2図は第1図の格子装置における絶縁性基
板の積層を示す分解斜視図、第3図及び第4図は
第2図の各絶縁性基板を展開してその導体格子を
示す平面図、第5図は従来技術の構成を示すブロ
ツク図、第6図は第5図の格子装置中の2枚の絶
縁性基板上の導体格子の形状を示す平面図。
1……正弦波電圧発生回路、2……カーソルコ
イル、3……基準位相信号線、41,51……そ
れぞれ演算増幅器、6……90°移相器、7……加
算器、10,20,30,40……第1、第2、
第3、第4の絶縁性基板、106,206,30
6,406……それぞれ第1の導体、107,2
07,307,407……それぞれ第2の導体、
100……格子装置。各図中同一符号は同一又は
相当部分を示す。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is an exploded perspective view showing the stacking of insulating substrates in the grating device of FIG. 1, and FIGS. 3 and 4 are each of the components shown in FIG. FIG. 5 is a block diagram showing the configuration of the prior art; FIG. 6 is a plan view showing the conductor lattice on the two insulating substrates in the lattice device of FIG. 5. A plan view showing the shape of. 1... Sine wave voltage generation circuit, 2... Cursor coil, 3... Reference phase signal line, 41, 51... Operational amplifier, respectively, 6... 90° phase shifter, 7... Adder, 10, 20 , 30, 40...first, second,
Third and fourth insulating substrates, 106, 206, 30
6,406...first conductor, 107,2 respectively
07, 307, 407...each second conductor,
100...Grid device. The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
子状に形成された平面を有する絶縁性基板を複数
枚積層して形成した格子装置と、この格子装置の
平面上に載置されるカーソルコイルとを備え、こ
のカーソルコイルに交流電流を流し、上記格子装
置の導体に誘起される電圧を処理して上記カーソ
ルコイルの上記格子装置の平面上における座標位
置を決定する座標位置決定装置において、 上記格子装置の平面に固定した直角座標の軸を
x軸及びy軸とするとき、 上記格子装置の複数枚の絶縁性基板のうちx軸
方向の座標位置決定に関連する基板は第1、第
2、第3、第4の4枚の基板から構成され、これ
ら4枚の基板はそれぞれy=yeの位置でx軸に平
行な第1の導体と、y=ysの位置でx軸に平行な
第2の導体と、y軸に平行でx軸方向にピツチ間
隔Dをもつて配列され、両端が上記第1の導体と
第2の導体とにそれぞれ接続される複数本の平行
導体からなる導体格子と、この導体格子の各導体
に誘起される電圧を演算増幅器で加算するときの
入力抵抗としてそれぞれの導体に挿入される抵抗
とを備え、 上記第1の基板上の導体格子を基準とし、上記
第2、第3、第4の基板上の導体格子の位置を+
x方向にそれぞれD/2、D/4、3D/4ずつ
ずらして配列し、 上記第1の基板の第1の導体と上記第2の基板
の第2の導体とを接続する第1の接続点の電圧か
ら、上記第1の基板の第2の導体と上記第2の基
板の第1の導体とを接続する第2の接続点の電圧
を第1の演算増幅器により減算し、 上記第3の基板の第1の導体と上記第4の基板
の第2の導体とを接続する第3の接続点の電圧か
ら、上記第3の基板の第2の導体と上記第4の基
板の第1の導体とを接続する第4の接続点の電圧
を第2の演算増幅器により減算し、 上記第1及び第2の演算増幅器の出力を上記交
流電流の位相に関し相互間に90度移相した上で加
算した合成電圧の位相を計測して上記カーソルコ
イルの上記x軸上の位置を算出することを特徴と
する座標位置決定装置。[Claims] 1. A lattice device formed by laminating a plurality of insulating substrates each having a plane in which a conductor in which a voltage is induced by electromagnetic induction is formed in a lattice shape, and a cursor coil placed on the cursor coil, the coordinates for determining the coordinate position of the cursor coil on the plane of the lattice device by passing an alternating current through the cursor coil and processing the voltage induced in the conductor of the lattice device; In the positioning device, when the axes of rectangular coordinates fixed on the plane of the grating device are the x-axis and y-axis, a substrate related to coordinate position determination in the x-axis direction among the plurality of insulating substrates of the grating device; is composed of four substrates, first, second, third, and fourth, and each of these four substrates has a first conductor parallel to the x-axis at a position of y=y e , and a conductor parallel to the x-axis at a position of y=y s. and a second conductor parallel to the x-axis at the position of The first substrate includes a conductor grid made up of a plurality of parallel conductors, and a resistor inserted into each conductor as an input resistance when adding voltages induced in each conductor of the conductor grid by an operational amplifier. With the upper conductor grid as a reference, the positions of the conductor grids on the second, third, and fourth substrates are +
A first connection that connects the first conductor of the first substrate and the second conductor of the second substrate, which are arranged to be shifted by D/2, D/4, and 3D/4 in the x direction, respectively. From the voltage at the point, the voltage at a second connection point connecting the second conductor of the first substrate and the first conductor of the second substrate is subtracted by the first operational amplifier; From the voltage at the third connection point connecting the first conductor of the substrate and the second conductor of the fourth substrate, the voltage of the second conductor of the third substrate and the first conductor of the fourth substrate is calculated. A second operational amplifier subtracts the voltage at a fourth connection point that connects the conductor of A coordinate position determination device characterized in that the position of the cursor coil on the x-axis is calculated by measuring the phase of the combined voltage added in the coordinate position determination device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61001443A JPS62160525A (en) | 1986-01-09 | 1986-01-09 | Coordinates position determining device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61001443A JPS62160525A (en) | 1986-01-09 | 1986-01-09 | Coordinates position determining device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62160525A JPS62160525A (en) | 1987-07-16 |
| JPH0546575B2 true JPH0546575B2 (en) | 1993-07-14 |
Family
ID=11501580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61001443A Granted JPS62160525A (en) | 1986-01-09 | 1986-01-09 | Coordinates position determining device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62160525A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005513575A (en) * | 2001-12-29 | 2005-05-12 | タイグエン エンタープライズ カンパニーリミテッド | Touch-controlled display with a thin film antenna array built into the inductive layer in a grid pattern |
-
1986
- 1986-01-09 JP JP61001443A patent/JPS62160525A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62160525A (en) | 1987-07-16 |
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