JPH0546728B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a data processing device, particularly a data processing device that processes data obtained by sampling a temporally continuous analog signal such as an audio signal or a video signal, after passing it through a transmission system such as a recording/reproducing system. It relates to a processing device.

<Description of Prior Art> In data transmitted through a transmission system, data with low reliability may occur due to data errors or lack of data due to, for example, dropouts occurring during recording and reproduction. When such low reliability data is detected, it is common to replace the detected low reliability data with newly generated data. For example, when error data occurs in data obtained by sampling an audio signal, a method has been used in which the error data is replaced with interpolated data obtained using data before and after the error data. The methods include the pre-hold method, in which the data immediately before the error data is used as interpolation data, the average value interpolation method, in which the average value of the data immediately before and after the error data is used as the interpolation data, and the data in the vicinity of the error data. A cubic interpolation method using interpolated data obtained from (at least four) methods is known.

In terms of the degree of approximation of such interpolated data to the original signal data, the previous value hold method is the worst, followed by the average value interpolation method and the cubic interpolation method, which are better in that order, but the scale of the hardware also increases accordingly. I get used to it. Therefore, they are used depending on the type of information signal processed by the data processing circuit and the scale of the device.

FIG. 1 is a diagram showing an example of a schematic configuration of a conventional general data processing device that replaces error data using an average value interpolation method. In FIG. 1, 2 and 4 are latch circuits, respectively, which delay transmitted data by one sampling period. 6 is an average value calculation circuit, which inputs the input data of the latch circuit 2 and the latch circuit 4.
The output data is calculated and output. A data selector 8 selectively outputs the output data of the latch circuit 2 and the output data of the average value calculation circuit 6. 10 is a timing clock input terminal, 12
1 is a well-known input terminal for an error detection signal, and 14 is a latch circuit for delaying the error detection signal by one sampling period. As is well known, the error detection signal is obtained by checking the parity word or CRCC. data), “0” is input from the terminal 12. Further, the data selector 8 outputs the output data of the average value calculation circuit 6 when the output from the latch circuit 14 is "1", and outputs the output data of the latch circuit 2 when the output is "0".

Now, if the reliability of the output data of the latch circuit 2 is high (in the case of non-error data), the latch circuit 14
The output of the latch circuit 2 is "0", and the data selector 14 outputs the output data of the latch circuit 2 as is. On the other hand, if the reliability of the output data of the latch circuit 2 is low ((in the case of error data), the latch circuit 14
Since the output of is "1", the output data of the average value calculation circuit 6 is outputted from the data selector. Since the output data of the average value calculation circuit 6 is the average value of the data immediately before and after the output data of the latch circuit 2, average value interpolation has been performed.

Here, the average value calculation circuit 6 is composed of, for example, a full adder circuit and a 1/2 multiplier using a 1-bit shift.
In this case, if the least significant bit of the input data of the 1/2 multiplier is "1", the output data of the average value calculation circuit 6 will necessarily be the data obtained by rounding down the calculation result.

This will be explained in more detail below. Assuming that the current data is 4 bits, if the data (A data) immediately before the error data (B data) is 1101 ₍₂₎ , and the data immediately after (C data) is 1001 ₍₂₎ , use the method described above to A+C. When calculating /2, A+C gives 10110 ₍₂₎ , and by shifting one bit lower, we get 1011 ₍₂₎ . Considering this in decimal notation, it becomes 13 + 9/2 = 11, which means that correct average value data has been obtained. However, if the A data is now 1101 ₍₂₎ and the C data is 1000 ₍₂₎ , then after obtaining 10101 ₍₂₎ with A + C, we will obtain 1010 ₍₂₎ as the average value data, but this is considered in decimal notation.
Since 13+8/2=10, the correct average value data is not obtained because the fraction of the calculation result is rounded down. In other words, the average value data will not be obtained correctly, and there is a probability of 1/2 that it will be 0.5 in decimal.
It will output a small amount of data.

However, since the analog original signal varies in whether it is larger or smaller than the average value data, the output data may have a large error with respect to the analog original signal due to this rounding down. Furthermore, unnatural high frequency components may be generated.
This also applies to the configuration in which fractions are rounded up.

In addition, even in conventional data processing devices other than the configuration described above, when obtaining interpolated data by calculation, rounding up or down greatly impairs the approximation of the output data to the original signal and generates unnatural high frequency components. There were times when I ended up doing something wrong.

<Object of the Invention> In view of the above-mentioned drawbacks, the present invention has been designed to improve the original output data by rounding up or down the calculation result when replacing error data with new interpolation data obtained by calculation of data before and after the error data. It is an object of the present invention to provide a data processing device capable of preventing loss of approximation to a signal and obtaining output data close to the original signal.

<Explanation based on examples> The present invention will be explained below using examples.

The following explanation will be made assuming that the analog signal is transmitted as 4-bit digital data. Also, 2 _'s complement is generally used in the binary system when converting audio and video signals into binary values. This is often used because the value corresponding to data in which all bits are "0" or all bits are "1" is around 0, which tends to occur when a system abnormality occurs. Since the circuit includes the 1/2 multiplier based on the 1-bit shift described above, the explanation will be made assuming that it handles binary data based on so-called offset binary. You may also think of it as processing data by converting 2 _'s complement data to offset binary data.

FIG. 2 is a diagram showing the main part configuration of a data processing device as an embodiment of the present invention. Components in FIG. 2 that are the same as those in FIG. 1 are given the same numbers and their explanations will be omitted. Furthermore, in the configuration of FIG. 2, for the sake of simplicity of explanation, it is assumed that one error data occurs independently. 1a, 1b, 1c, and 1d are terminals into which binary data is input, and the data input from these terminals is transmitted through the transmission system.
Input as bit data. 16 is a full adder circuit, which combines the 4-bit data supplied to the terminals 1a to 1d and the 4-bit data outputted from the latch circuit 4.
bit data and output as 5-bit data including carry. If the upper 4 bits of the 5-bit data including the carry are output, data obtained by rounding down the average value of the output data of the latch circuit 4 can be obtained as described above. 1
8 is a latch circuit that delays the output of latch circuit 4 by one sample period and outputs it; 20 and 22 are subtraction circuits; and 23 is a circuit that doubles the input data and outputs it.
A doubler circuit, 24 is a full adder circuit, and 30, 32, and 34 are inverters, respectively.

Next, before explaining the operation of each part according to the above-described configuration, the principle of the present invention will be briefly explained. FIGS. 3A and 3B are diagrams for explaining the present invention.
In Figure 3 A and B, the dotted line is the analog original signal, ○
indicates non-error data, and Δ and × indicate interpolated data, respectively. Furthermore, t ₁ , t ₂ , t ₃ , and t ₄ indicate sampling timings, and it is assumed that the data transmitted at time t ₃ is error data.

As shown in Figure 3A, if the analog original signal is convex upward at timing _t3 , that is, when the second derivative value is negative, the analog original signal is at a relatively large level, so the calculation result is a fraction. It is desirable to obtain interpolated data by rounding up. On the other hand, if the analog original signal is convex downward at timing _t3 as shown in FIG. 3B, it is desirable to obtain interpolated data by rounding down the fraction of the calculation result.

Next, an example of a method for determining whether a second-order differential value is positive or negative will be described. Let the respective data values at t ₁ , t ₂ , and t ₄ be d ₁ , d ₂ , and d ₄ . A positive second-order differential value means that the slope of the signal increases over time, so compare the average slope between t ₁ and t ₂ with the average slope between t ₂ and t ₄ . Just do it. In other words, all you have to do is compare (d ₂ - _{d 1} )/T (T indicates one sampling period) and (d ₄ + d ₂ )/2T, which is (d ₄ - d ₂ )+2(d ₁ - d ₂ ). When is positive, it is convex downward, and when it is negative, it is convex upward. Also
When using data (d ₅ ) at t ₅ , which is delayed by T from t ₄ , the positive or negative of 2 (d ₅ - d ₄ ) + (d ₂ - d ₄ ) or (d ₅ - d ₄ ) + It is sufficient to determine whether (d ₁ −d ₂ ) is positive or negative.

The operation of each part of the apparatus shown in FIG. 2 will be explained below using specific data. In this embodiment, it is assumed that the data input to the terminals 1a to 1d is obtained by sampling analog signals (for example, audio signals) that occur at approximately the same amplitude and at the same rate with the 0 level as the boundary, and the quantization is as follows. -8
There are 16 levels from +7 to +7. In other words, if the decimal data is -8, it will be 0000 ₍₂₎ , if it is 0, it will be 1000 ₍₂₎ , and if it is +7, it will be 1111 ₍₂₎ .

First, according to Figure 3A, d ₁ is 1000 ₍₂₎ (0) and d ₂ is
1011 ₍₂₎ (+3), d ₄ is assumed to be 1110 ₍₂₎ (+6). At this time, if d ₁ is input to terminals 1a to 1d, d ₂ is output from latch circuit 2,
The latch circuit 18 outputs _d4 . At this time, the output of the latch circuit 14 is at a high level, so
The data selector 8 outputs the upper 4 bits of data of the output of the full adder circuit 16, that is, (d ₂ +d ₄ )/2.

On the other hand, the positive input of the subtraction circuit 20 is d ₄ and the negative input is d ₂ , which are connected to the inverters 30 and 32 respectively.
Invert the most significant bit data (MSB) before inputting it. This is an operation using a subtraction circuit.
This is because it is done with data of 2′ _s complement,
Each inverter 30, 32, and 34 serves to convert offset binary data into 2 _'s complement data. Therefore, d ₁ input to the subtraction circuits 20 and 22 is 0000 ₍₂₎ , d ₂
is 0011 ₍₂₎ and d ₄ is 0110 ₍₂₎ . Therefore, subtraction circuit 2
The output data (d ₄ −d ₂ ) of 0 is 0011 ₍₂₎ (−3), and the output data (d ₁ −d ₂ ) of the subtraction circuit 22 is 1101 ₍₂₎ . The output data (d ₁ - d ₂ ) of the subtraction circuit 22 is doubled by the doubling circuit 23 and becomes 1010 _(2).
is added to the output data 0011 ₍₂₎ by the full adder circuit 24 to obtain an output 1101 ₍₂₎ . The output of the full adder circuit 24 is (d ₄ -d ₂ )+2(d ₁ -d ₂ ), and as described above, by distinguishing whether this data is positive or negative, the unevenness (secondary differential feature) of the signal can be determined. Data by 2 _'s complement is negative when its MSB is "1" and positive when it is "0". Therefore, since this MSB is "1", it is sufficient to round up the value of (d ₂ +d ₄ )/2.

The full adder circuit 16 uses offset binary d ₂
(1011 ₍₂₎ ) and d ₄ (1110 ₍₂₎ ) are added, and the output of the aforementioned full adder circuit 24 is used as a carry-in.
MSB “1” is entered and the output is 11010 ₍₂₎ .
Therefore, if these upper 4 bits are taken as average value data,
1101 ₍₂₎ (+5), meaning that the fraction has been rounded up. Therefore, the output data obtained from this data (indicated by △ in FIG. 3A) is approximated to the original analog signal waveform. The data indicated by x in FIG. 3A is output data when fractions are rounded down.

Next, according to Figure 3B, d ₁ is 0111 ₍₂₎ (-1) and d ₂ is
1000 ₍₂₎ (0), d ₄ is assumed to be 1101 ₍₂₎ (+5). At this time, the output of the subtraction circuit 20 is 0101 ₍₂₎ due to 2′ _s complement, and the output of the subtraction circuit 22 is
1111 ₍₂₎ , the output of the doubling circuit 23 is 1110 ₍₂₎ , and the output of the full adder circuit 24 is 0011 ₍₂₎ . Therefore, since the MSB of the full adder circuit 24 is "0", the carry-in of the full adder circuit 16 is "0". In the full adder circuit 16, d ₄ is calculated by offset binary.
(1101 ₍₂₎ ) and d ₂ (1000 ₍₂₎ ) are added, and the output is
10101 ₍₂₎ is obtained. And this top 4 bits 1010 ₍₂₎
Since we get +2, the fraction has been rounded down. Therefore, this output data (indicated by Δ in FIG. 3B) is much more approximated to the original analog signal waveform than when the fraction is rounded up (indicated by x in FIG. 3B).

As mentioned above, according to the configuration shown in Fig. 2, the fractions of the calculation results of the average value circuit are rounded up or down according to the second-order differential characteristics of the original analog signal. The error from the original analog signal does not increase due to rounding up or down, but rather output data that approximates the original analog signal can be obtained.

Next, a case will be explained using FIG. 4 in which the case where two or more pieces of unreliable data occur consecutively is also taken into consideration. FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention.
Components in FIG. 4 that are the same as those in FIG. 2 are designated by the same numbers and their explanations will be omitted. 36 is an inverter, 38 and 40 are AND gates, 42,
44 are data selectors, respectively. Further, FIG. 5 is a timing chart showing the state of each part in FIG. 4, and the operation will be explained below using FIG. 5.

The DATA-IN part in Figure 4 is the one in Figure 5.
As shown in DATA-IN, D0, D1, D2,...D19,
It is assumed that data is input in the order of D20. When the error detection signal supplied from the terminal 12 and input to the latch circuit 14 is "1", it indicates that the data being input from DATA-IN is error data. Therefore D4, D7, D9, D10 and D13~D18
have low reliability.

Now, when the output of the latch circuit 14 is "0", the data output from the latch circuit 2 is non-error data. At this time, and gate 38,
The output of 40 is at a low level, and data selectors 42 and 44 each select and output the data supplied to the L side in the figure. Therefore, at this time, the output of the latch circuit 14 becomes DATA-OUT as it is and is supplied to the latch circuit 4.

On the other hand, when the output of the latch circuit 14 is "1", the output data of the latch circuit 2 is error data and cannot be directly output as DATA-OUT via the data selectors 42 and 44. Therefore, it is necessary to replace it with some kind of interpolated data. Either replace this with non-error data that occurred in the past that was closest in time (hold the previous value), or
This is done by replacing the non-error data with data indicating the average value of the immediately following non-error data (average value interpolation).

This is determined by the reliability of the data immediately following the error data. In other words, if the immediately following data is non-error data, average value interpolation is possible;
The upper 4 bits of the output data of the full adder circuit 16 are replaced with average value data obtained as described above. In this case, the output of the AND gate 38 becomes high level, and the data selector 42 outputs the data input to the H side in the figure (that is, the upper bits of the output data of the full adder circuit 16), which is input to the data selector 44. It becomes DATA-OUT via the L side. The part where D4 is replaced with (D3+D5)/2,
This corresponds to the part where D7 is replaced with (D6+D8)/2.

On the other hand, when the immediately following data is error data, it is impossible to perform average value interpolation, so the data that was output immediately before is output again. At this time, the output of the AND gate 40 becomes high level, and the data selector 44 outputs the data outputted immediately before, delayed by one sample period by the latch circuit 4. The output data of the data selector 44 is set as DATA OUT and is again supplied to the latch circuit 4. This corresponds to the part where D9 is replaced with D8 and the part where D13 to 17 are replaced with D12.

Furthermore, when several pieces of error data continue and the last error data is output from the latch circuit 2, the output of the AND gate 38 is at a high level, and the output of the AND gate 4 is at a high level, as is clear from the above explanation.
Since the output of 0 is low level, DATA
The upper 4 bits of the output of the full adder circuit 16 are output to OUT. This full adder circuit uses the previous value hold data output from the latch circuit 4, that is, the non-error data that occurred in the most recent past, and the DATA−
Data that is the average value of the non-error data input to IN is output from DATA-OUT. D10
This corresponds to the part where D18 is replaced with (D8+D11)/2 and the part where D18 is replaced with (D12+D19)/2.

The output data of the full adder circuit 24 shows the second-order differential characteristics of the original analog signal, and when this data is positive, the original analog signal is convex downward, and when this data is negative, it is convex upward. The output of the full adder circuit 24 is 2′ _s
Since the data is based on complement, the
By supplying the MSB to the full adder circuit 16,
Similarly, the average value calculation result is rounded up or down.

It goes without saying that even in the above-described configuration, data similar to the original analog signal can be obtained even when coarse quantization is performed.

Although the above explanation uses offset binary 4-bit data, the present invention is applicable regardless of the type of data and the number of quantizations. Also, as a calculation means for obtaining interpolated data, only the average value calculation was explained, but 3
The present invention can also be applied to the case of rounding up or down the calculation result in the case of the second-order interpolation method.

<Description of Effects> As explained above, according to the present invention, when error data is replaced with interpolated data according to the calculation output of data before and after the error data, the output data is thereby approximated more closely to the original signal. The present invention provides a data processing device capable of rounding up or down the calculation result.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration example of a conventional general data processing device, FIG. 2 is a diagram showing a main part configuration of a data processing device as an embodiment of the present invention, and FIGS. 3A and 3B are A diagram for explaining data replacement by the device of the present invention, FIG. 4 is a diagram showing the main part configuration of a data processing device as another embodiment of the present invention, and FIG. 5 shows waveforms of each part of FIG. 4. This is a timing chart. 2, 4, 14 and 18 are latch circuits, 8,
42 are data selectors included in the replacement means, respectively;
16 is a full adder circuit included in the calculation means. 2
0 and 22 are subtraction circuits, 23 is a doubling circuit, and 24
is a full adder circuit, which is included in the determining means.

Claims (1)

[Scope of Claims] 1. A device for processing data obtained by sampling a temporally continuous analog signal after transmission, comprising: a calculation means for calculating data before and after error data; and a calculation means for calculating data in the vicinity of the error data. a discriminating means for discriminating the quadratic differential feature of the analog signal waveform using the above-described method; A data processing device comprising: generating means for generating new data by rounding down the calculation result when the calculation result is convex; and replacing means for replacing the error data with data obtained by the generating means.