JPH0547130B2 - - Google Patents
Info
- Publication number
- JPH0547130B2 JPH0547130B2 JP61077602A JP7760286A JPH0547130B2 JP H0547130 B2 JPH0547130 B2 JP H0547130B2 JP 61077602 A JP61077602 A JP 61077602A JP 7760286 A JP7760286 A JP 7760286A JP H0547130 B2 JPH0547130 B2 JP H0547130B2
- Authority
- JP
- Japan
- Prior art keywords
- value
- logical value
- circuit
- logic
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
〔産業上の利用分野〕
本発明は多値論理回路のうち特に4値論理信号
を2値論理信号に変換する4値2値変換回路に関
する。
〔従来の技術〕
半導体論理集積回路において、集積度が増すに
つれてその配線に要する面積のチツプ全体に占め
る割合は増加する。従来よりこの配線領域を減ら
す手段として多層配線技術が開発されて実用化さ
れている。
〔発明が解決しようとする問題点〕
上述した従来の多層配線技術では、配線ネツト
数は依然として増加する欠点がある。
そこでチツプ内の信号の伝送を4値で行なうこ
とにより配線数そのものを半減させる方式が提案
されている。
本発明の目的は、このチツプ内4値信号伝送方
式を実現するための回路の1つであり、4値論理
信号を2値論理信号に変換する4値2値変換回路
を提供することにある。
〔問題点を解決するための手段〕
本発明の4値2値変換回路は、電源電圧範囲を
4つの電圧範囲に分割しその分割された電圧範囲
に低電圧側から論理値0、1、2、3を割り当て
る4値論理信号を入力信号とする論理回路におい
て、論理値0および論理値1と、論理値2および
論理値3とを判定して2値信号で出力する第1の
判定回路と、論理値3を論理値2に、論理値2を
論理値1に変換する論理値減算回路と、論理値0
を論理値1に、論理値1を論理値2に変換する論
理値加算回路とを備え、前記4値入力信号が前記
第1の判定回路と前記論理値減算回路および前記
論理値加算回路に入力され、該第1の判定回路の
出力結果を第1の出力信号となし、更に該第1の
判定回路の判定結果が(論理値0または論理値
1)のときには前記論理値加算回路の出力信号を
第2の判定回路に通して得られる信号を選択し、
判定結果が(論理値2または論理値3)のときに
は前記論理値減算回路の出力信号を前記第2の判
定回路を通して得られる信号を選択して第2の出
力信号としている。
〔実施例〕
次に本発明について図面を参照して説明する。
第1図は本発明の一実施例を示すブロツク図で
ある。
4値入力信号は入力端子10に入力され、その
信号は判定回路11、論理値加算回路12、論理
値減算回路13の入力信号となる。判定回路1
1,15は4値入力信号が論理値0または論理値
1の時には2値論理信号0,1の論理値0を出力
し、4値入力信号が論理値2または論理値3の時
には2値論理値1を出力する。論理値加算回路1
2は4値入力信号が論理値0の時には4値論理値
1を出力し、4値入力信号が論理値1の時には4
値論理値2を出力する。論理値減算回路13は4
値入力信号が論理値3、論理値2の時にはそれぞ
れ4値論理値2、4値論理値1を出力する。選択
回路14は判定回路11の出力が2値論理値0の
時は論理値加算回路12からの信号を出力し、判
定回路11の出力が2値論理値1の時は論理値減
算回路13からの信号を出力するスイツチであ
る。
次に動作原理につき詳細に説明する。
(1) 4値入力信号が論理値0のときは、判定回路
11は2値論理値0を出力する。論理値加算回
路12は4値論理値1を出力する。よつて選択
回路14の出力は4値論理値1となり、判定回
路15の出力は2値論理値0となる。つまり、
出力端子16および17に現われる2値出力信
号AおよびBはとも論理値0となる。
(2) 4値入力信号が論理値1のときは、判定回路
11は2値論理値0を出力する。論理値加算回
路12は4値論理値2を出力する。よつて選択
回路14の出力は4値分論理値2となり、判定
回路15は2値論理値1を出力する。つまり、
前記2値出力信号AおよびBはそれぞれ論理値
1および論理値0となる。
(3) 4値入力信号が論理値2のときは、判定回路
11は2値論理値1を出力する。論理値減算回
路13は4値論理値1を出力する。よつて選択
回路14の出力は4値論理値1となり、判定回
路15は2値論理値0を出力するから前記2値
出力信号AおよびBはそれぞれ論理値0および
論理値1となる。
(4) 4値入力信号が論理値3のときは、判定回路
11は2値論理値1を出力する。論理値減算回
路13は4値論理値2を出力する。よつて選択
回路14の出力は4値論理値2となり、判定回
路15の出力は2値論理値1を出力するから前
記2値出力信号AおよびBはともに論理値1と
なる。
以上(1)〜(4)より表1に示す真理値表が得られ、
4値入力信号が2値出力に変換される。
[Industrial Field of Application] The present invention relates to a multi-value logic circuit, and particularly to a four-value binary conversion circuit that converts a four-value logic signal into a binary logic signal. [Prior Art] In semiconductor logic integrated circuits, as the degree of integration increases, the area required for wiring increases as a percentage of the entire chip. Conventionally, multilayer wiring technology has been developed and put into practical use as a means of reducing this wiring area. [Problems to be Solved by the Invention] The conventional multilayer wiring technology described above still has the drawback that the number of wiring nets increases. Therefore, a method has been proposed in which the number of wiring lines itself is halved by transmitting signals within the chip using four values. An object of the present invention is to provide a 4-value to binary conversion circuit which is one of the circuits for realizing this intra-chip 4-value signal transmission system, and which converts a 4-value logic signal into a binary logic signal. . [Means for Solving the Problems] The four-value to binary conversion circuit of the present invention divides the power supply voltage range into four voltage ranges and assigns logical values 0, 1, and 2 to the divided voltage ranges from the low voltage side. , 3 is assigned as an input signal, a first determination circuit that determines a logical value 0 and a logical value 1, and a logical value 2 and a logical value 3, and outputs the result as a binary signal. , a logical value subtraction circuit that converts logical value 3 to logical value 2, logical value 2 to logical value 1, and logical value 0.
and a logic value addition circuit that converts the logic value 1 to a logic value 1 and the logic value 1 to a logic value 2, and the four-value input signal is input to the first determination circuit, the logic value subtraction circuit, and the logic value addition circuit. and sets the output result of the first determination circuit as a first output signal, and furthermore, when the determination result of the first determination circuit is (logical value 0 or logical value 1), the output signal of the logical value addition circuit. select the signal obtained by passing it through the second judgment circuit,
When the determination result is (logical value 2 or logical value 3), a signal obtained from the output signal of the logical value subtraction circuit through the second determination circuit is selected as the second output signal. [Example] Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. A four-value input signal is input to an input terminal 10, and the signal becomes an input signal to a determination circuit 11, a logic value addition circuit 12, and a logic value subtraction circuit 13. Judgment circuit 1
1 and 15 output the logical value 0 of binary logic signals 0 and 1 when the 4-value input signal is a logical value 0 or 1, and output the logical value 0 of the binary logic signal 0 and 1 when the 4-value input signal is a logical value 2 or 3. Outputs the value 1. Logical value addition circuit 1
2 outputs a 4-value logical value 1 when the 4-value input signal is a logical value 0, and outputs a 4-value logical value 1 when the 4-value input signal is a logical value 1.
Outputs the value logical value 2. The logic value subtraction circuit 13 is 4
When the value input signal is a logical value 3 and a logical value 2, a four-value logical value 2 and a four-value logical value 1 are output, respectively. The selection circuit 14 outputs a signal from the logical value addition circuit 12 when the output of the determination circuit 11 is a binary logical value 0, and outputs the signal from the logical value subtraction circuit 13 when the output of the determination circuit 11 is a binary logical value 1. This is a switch that outputs a signal. Next, the principle of operation will be explained in detail. (1) When the four-value input signal has a logical value of 0, the determination circuit 11 outputs a binary logical value of 0. The logic value addition circuit 12 outputs a four-value logic value 1. Therefore, the output of the selection circuit 14 becomes a four-value logic value 1, and the output of the determination circuit 15 becomes a two-value logic value 0. In other words,
Both binary output signals A and B appearing at output terminals 16 and 17 have a logic value of 0. (2) When the four-value input signal has a logical value of 1, the determination circuit 11 outputs a binary logical value of 0. The logic value addition circuit 12 outputs a four-value logic value 2. Therefore, the output of the selection circuit 14 becomes a four-value logical value 2, and the determination circuit 15 outputs a binary logical value 1. In other words,
The binary output signals A and B have a logic value of 1 and a logic value of 0, respectively. (3) When the four-value input signal has a logical value of 2, the determination circuit 11 outputs a binary logical value of 1. The logic value subtraction circuit 13 outputs a four-value logic value 1. Therefore, the output of the selection circuit 14 becomes a four-value logic value 1, and since the determination circuit 15 outputs a binary logic value 0, the binary output signals A and B become a logic value 0 and a logic value 1, respectively. (4) When the four-value input signal has a logical value of 3, the determination circuit 11 outputs a binary logical value of 1. The logic value subtraction circuit 13 outputs a four-value logic value 2. Therefore, the output of the selection circuit 14 is a four-value logical value 2, and the output of the determination circuit 15 is a binary logical value 1, so the binary output signals A and B both have a logical value 1. From (1) to (4) above, the truth table shown in Table 1 is obtained,
A four-value input signal is converted to a two-value output.
以上説明したように本発明は、4値論理信号を
2値論理信号に変換する回路を比較的容易に提供
でき、これを集積回路内に適用してチツプ内信号
伝送を4値論理信号で行なわせることにより、チ
ツプ内配線数を減少させチツプ全体に占める配線
領域が著しく減少するので、チツプ面積の縮小化
ができる効果がある。
As explained above, the present invention can relatively easily provide a circuit that converts a four-valued logic signal into a two-valued logic signal, and can be applied within an integrated circuit to perform intra-chip signal transmission using the four-valued logic signal. By doing so, the number of wiring lines within the chip is reduced and the wiring area occupied by the entire chip is significantly reduced, which has the effect of reducing the chip area.
第1図は本発明の一実施例を示すブロツク図、
第2図は第1図における4値2値変換回路を
CMOS回路で実現した一例を示す回路図である。
10,20……4値信号入力端子、11,1
5,21,25……判定回路、12,22……論
理値加算回路、13,23……論理値減算回路、
14,24……選択回路、16,17,26,2
7……2値信号出力端子。
FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 shows the 4-value to binary conversion circuit in Figure 1.
FIG. 2 is a circuit diagram showing an example realized using a CMOS circuit. 10, 20...4-value signal input terminal, 11, 1
5, 21, 25... Judgment circuit, 12, 22... Logical value addition circuit, 13, 23... Logical value subtraction circuit,
14, 24...Selection circuit, 16, 17, 26, 2
7...Binary signal output terminal.
Claims (1)
分割された各電圧範囲に低電圧側から論理値0、
1、2、3を割り当てる4値論理信号を入力信号
とする論理回路において、論理値0および論理値
1と、論理値2および論理値3とを判定して2値
信号で出力する第1の判定回路と、論理値3を論
理値2に変換し論理値2を論理値1に変換する論
理値減算回路と、論理値0を論理値1に変換し論
理値1を論理値2に変換する論理値加算回路とを
備え、前記4値入力信号が前記第1の判定回路と
前記論理値減算回路および前記論理値加算回路に
入力され、該第1の判定回路の出力結果を第1の
出力信号となし、更に該第1の判定回路の判定結
果が(論理値0または論理値1)のときには前記
論理値加算回路の出力信号を第2の判定回路に通
して得られる信号を選択し、判定結果が(論理値
2または論理値3)のときには前記論理値減算回
路の出力信号を前記第2の判定回路に通して得ら
れる信号を選択して第2の出力信号となすことを
特徴とする4値2値変換回路。1 Divide the power supply voltage range into four voltage ranges and set each divided voltage range with logic values 0, 0, and 0 from the low voltage side.
In a logic circuit whose input signal is a four-value logic signal that assigns 1, 2, and 3, a first logic circuit that determines logic value 0 and logic value 1, logic value 2 and logic value 3, and outputs it as a binary signal. A determination circuit, a logical value subtraction circuit that converts logical value 3 to logical value 2, logical value 2 to logical value 1, logical value 0 to logical value 1, and logical value 1 to logical value 2. a logical value addition circuit, the four-value input signal is input to the first determination circuit, the logical value subtraction circuit, and the logical value addition circuit, and the output result of the first determination circuit is input to the first output. selecting a signal obtained by passing the output signal of the logical value addition circuit through a second determination circuit when the determination result of the first determination circuit is (logical value 0 or logical value 1); When the determination result is (logical value 2 or logical value 3), the output signal of the logical value subtraction circuit is passed through the second determination circuit, and the obtained signal is selected and used as the second output signal. A four-value to two-value conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61077602A JPS62233927A (en) | 1986-04-03 | 1986-04-03 | Tetral/binary converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61077602A JPS62233927A (en) | 1986-04-03 | 1986-04-03 | Tetral/binary converting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62233927A JPS62233927A (en) | 1987-10-14 |
| JPH0547130B2 true JPH0547130B2 (en) | 1993-07-15 |
Family
ID=13638486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61077602A Granted JPS62233927A (en) | 1986-04-03 | 1986-04-03 | Tetral/binary converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62233927A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2818449B2 (en) * | 1989-09-29 | 1998-10-30 | 関西日本電気株式会社 | Logic integrated circuit |
| JP6253418B2 (en) * | 2014-01-17 | 2017-12-27 | エスアイアイ・セミコンダクタ株式会社 | Voltage regulator and semiconductor device |
| CN104579310A (en) * | 2014-11-14 | 2015-04-29 | 浙江工商大学 | QB32 (Quaternary-Binary 32) module circuit unit based on CMOS (complementary metal oxide semiconductor) |
| CN104320127A (en) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | CMOS circuit unit for converting QC into BC13 |
| CN104333370A (en) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | Quaternary-binary clock based QBC20 circuit |
| CN104320126A (en) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | Circuit unit converting QC into BC21 |
| CN104320128A (en) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | QBC23 circuit based on CMOS |
-
1986
- 1986-04-03 JP JP61077602A patent/JPS62233927A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62233927A (en) | 1987-10-14 |
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