JPH0547995A - Multichip module - Google Patents

Abstract

(57) [Summary] [Construction] A multi-chip module in which there is a connecting terminal 14 connected to each chip 11, and an interconnecting region 16 in which each opposing terminal 14 is connected by a covered wiring 15 is formed. [Effect] Even when the number of connection terminals 14 is large and the wiring pattern is complicated, it is possible to realize free connection without short-circuiting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module, and more particularly to a multi-chip module containing a plurality of chips such as integrated circuits.

[0002]

2. Description of the Related Art As one of high-density and high-performance technologies for semiconductor integrated circuits, there is a multi-chip module in which functional element chips such as a plurality of integrated circuits are housed in a single package. When housing functional element chips such as a plurality of integrated circuits in a single package, wiring between chips becomes necessary.

FIG. 3 shows a conventional multi-chip module mounting a plurality of chips. In the figure, 33 indicates a multi-chip module, and the multi-chip module 33
A plurality of chips 31 are mounted in the inner recess 33a. The chip 31 is connected via a wire 32 to a corresponding connection terminal 34. That is, the chips 31 are connected to each other via the wires 32 and the connection terminals 34.

When forming the above multi-chip module, the multi-chip module 3 provided with the connection terminals 34 is provided.
3, the chip 31 is mounted, and the wire 32 is bonded to each connection terminal 34 and the pad of the chip 31.

This is an example of using wire bonding, but there is also an example of face down bonding using a Philip chip and not using wire bonding.

[0006]

By the way, in the conventional multi-chip module, there is a problem that the connection terminal 34 is fixed, there is no freedom in wiring, and flexibility is lacking.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a multi-chip module which can realize a connection between a plurality of chips with a great degree of freedom. There is.

[0008]

In order to achieve the above object, a multi-chip module according to the present invention comprises a plurality of ICs.
In the multi-chip module in which the chips are stored, programmable wiring means is arranged between the IC chips.

[0009]

According to the above-mentioned structure, in the multi-chip module in which the chips of a plurality of ICs are housed, each I
Since the programmable wiring means is provided between the C chips, each wiring can be freely wired without short-circuiting each wiring. In addition, if there is a connecting terminal connected to each chip and an interconnecting area in which opposing terminals are connected via a multilayer wiring board is formed, even if the wiring is complicated, a short circuit occurs. Free wiring between chips becomes easier.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a multichip module according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic perspective view showing an embodiment of a multichip module according to the present invention. Reference numeral 13 in the figure denotes a multi-chip module.
A plurality of recesses 13a are formed in the. The IC chip 11 is disposed in the one recess 13a, while the other recess 13a serves as the interconnection region 16. This recess 1
3a includes a connection terminal 14a. This recess 13a
The connection terminals 14a are connected by connection wiring 14b. The IC chip 11 has a connection terminal 1 via a wire 12.
4 is connected. The connection terminals 14a facing each other in the mutual wiring region 16 are connected by the coated wire 15.

In the manufacturing process of the multi-chip module constructed as described above, the interconnection region 16 is formed on the multilayer substrate 10 and the connection terminals 14a are arranged. Next, the IC chip 11 is die-bonded to the recess 13a, and the pad portion (not shown) of the chip 11 and each connection terminal 14 are wire-bonded. After that, the connection terminals 14 in the mutual wiring region 16 are connected to each other by using the coated wire 15 so as to form a desired wiring pattern. At this time, since the wire is coated, even if the coated wire 15 crosses, there is no risk of causing a short circuit.

In the multi-chip module according to the above-mentioned embodiment, the mutual wiring region 16 is formed on the multilayer substrate 10, and the connection terminal 14a is formed inside the mutual wiring region 16 so as to face each other. The connection terminals 14a are connected by a coated wire 15. On the other hand, a connection wiring 14b is formed between each IC chip 11 and the mutual wiring area 16. Therefore, as a result of free wiring in the mutual wiring region 16, the connection between the IC chips 11 can be performed in a programmable manner, and various functions by the multi-chip can be realized, but the manufacturing period can be shortened. Can be promoted. Figure 2
FIG. 3 is a schematic enlarged perspective view showing another embodiment of the multi-chip module according to the present invention.
3 shows a portion of the interconnection region 26 in FIG. In the figure, reference numeral 24a is a connection terminal, which is connected to a connection wiring 24b connected to an IC chip (not shown). Recess 1
A wiring pattern chip 27 is arranged between the connection terminals 24a facing each other in 3a. Wiring patterns 27a and 27b are formed on the wiring pattern chip 27, and the terminals of these wiring patterns 27a and 27b are connected to the connection terminals 24a via the wires 25.

In the manufacturing process of the multi-chip module thus constructed, the connection terminal 24a is formed in the interconnection area 26, and then two layers of wiring are formed to form the wiring patterns 27a and 27b. 24a and wiring patterns 27a and 27b are connected by a wire 25. At this time, if the wiring pattern area is complicated, four layers 5
Multi-layered wiring patterns 27a and 27b are formed from layers and the like. The wiring pattern chip 27 is formed with wiring patterns 27a and 27b only for wiring, and the wiring patterns 27a and 27b are easily realized on the substrate by a multilayer Al wiring technique or the like.

Yet another embodiment is shown in FIGS. In the multi-chip module 43 according to this embodiment, the wiring chip 4 in which the EEPROM 41 is arranged in the wiring between the IC chips
0 is used. The wiring in the wiring chip 40 is formed in a matrix, and a chip 44 whose electrical on / off state can be changed is connected to the intersection of these matrix wirings, and the output side can be programmable.

Incidentally, FIG. 4 shows a logical connection,
It is easy to bring the actual positions of the connection terminals to the left and right positions of the wiring chip 40 as shown in FIG. This is PLD (Programmable Logic Device), FPGA
It can be realized by using a technology such as (Field Programmable Gate Array).

As described above, in the multi-chip modules 13, 23 and 43 according to the above embodiment, I
Since the programmable wiring means is formed in addition to the C chip 11, the wiring between the IC chips can be programmed, and the existing IC chip 11 can be used to fabricate a high-density and high-performance multi-chip module in a short period of time. it can.

[0017]

As described above in detail, in the multi-chip module according to the present invention, in the multi-chip module accommodating a plurality of IC chips, each of the ICs
Since the programmable wiring means is provided between the chips, each wiring can be freely wired without short-circuiting each wiring. In addition, if there is a connecting terminal connected to each chip and an interconnecting area in which opposing terminals are connected via a multilayer wiring board is formed, even if the wiring is complicated, a short circuit occurs. Free wiring between chips becomes easier.

Therefore, a high-density and high-performance multi-chip module can be manufactured in a short period of time by using the existing chip.

[Brief description of drawings]

FIG. 1 is a partial schematic perspective view showing an embodiment of a multi-chip module according to the present invention.

FIG. 2 is a partially enlarged schematic perspective view showing another embodiment of the multi-chip module according to the present invention.

FIG. 3 is a partially enlarged schematic perspective view showing still another embodiment of the multi-chip module according to the present invention.

FIG. 4 is a partially enlarged schematic perspective view showing still another embodiment of the multi-chip module according to the present invention.

FIG. 5 is a partial schematic perspective view showing a conventional multi-chip module.

[Explanation of symbols]

 11 IC chips 13, 23, 43 Multi-chip modules

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // H01L 21/82 9169-4M H01L 21/82 S

Claims (1)

[Claims] 1. A multi-chip module in which a plurality of IC chips are housed, wherein a programmable wiring means is arranged between the IC chips.