JPH0548431B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a partial discharge measuring device for electrical equipment,
In particular, the present invention relates to a partial discharge measuring device equipped with a dielectric breakdown signal detection circuit that can accurately determine whether dielectric breakdown has occurred in a device under test.

[Background of the invention]

In partial discharge testing of electrical equipment, there is a five-signal detection device shown in Figure 9 that is known to have a configuration that can eliminate all kinds of electrical noise that may be an obstacle to measurement and accurately measure partial discharge signals. ing.

That is, two loop antennas 4, 5 and five detection impedances 6, 7, 8, 9, 10 are arranged in a partial discharge test circuit consisting of a device under test 1, a power source 2, and a coupling capacitor 3. With the measuring device 11,
Five signals v ₁ , v ₂ , v ₃ , v ₄ , and v ₅ are detected.

The sources of interference noise can be roughly divided into power supply noise entering from the power supply 2, airborne corona discharge noise generated in the coupling capacitor 3, and radio noise due to spatial magnetic fields.
The current distribution in the test circuit is different for these signal sources. The polarity of the five signals v ₁ , v ₂ , v ₃ , v ₄ , v ₅ is the 10th
As shown in the figure, the polarity combinations differ depending on the signal source.

As shown in FIG. 11, the measuring device 11 includes a detector 12 consisting of five detection impedances, an amplifier 13 that amplifies the five signals to an appropriate level, and a device that discriminates between noise and signals from the polarity combination of the five signals. It consists of a noise discriminator 14 for counting discharge pulses, and a pulse measuring device 15 for counting discharge pulses. Signal input terminal P ₁ in the same figure,
P ₂ , P ₃ , P ₄ , and P ₅ correspond to the nodes shown in FIG. 9, respectively.

As the pulse measuring device 15, a computer-applied wave height analyzer or the like may be used in addition to a normal partial discharge measuring device. The noise discriminator 14 is a device that discriminates between a signal and noise based on the polarity combination of five signals and outputs only the signal as an analog signal, and has a circuit block configuration shown in FIG. In the same figure, the waveform shaping circuit 16
converts each of the five input analog signals into a digital signal that indicates the positive or negative polarity. The logic circuit 17 discriminates whether the polarity combination of the five signals is a signal or noise, and outputs a digital signal _v6 indicating either one. The first half-wave discrimination circuit 18 outputs a digital signal _v7 that discriminates between the first half-wave at the wave head and the subsequent wave tail of the input signal. The signal and first half-wave circuit 19 outputs a digital signal v ₈ which indicates a signal only when v ₆ and v ₇ are a signal and a first half wave, and a noise under other conditions. The SN gate circuit 20 outputs the first half wave _v9 of the analog signal _v2 when _v8 is a signal.

By the way, the phases of the five analog signals v ₁ to v ₅ detected in the partial discharge test do not necessarily match. For example, in the case of noise input, the signal
The V ₆ outputs not only a noise display signal, but also a narrow signal display signal. In this case, even though it is originally noise, an output signal _v9 is produced as shown in the figure.

In this way, if the phases of the five signals are uneven,
Conventional noise discriminators had the disadvantage of malfunctioning.

[Purpose of the invention]

An object of the present invention is to provide a noise discriminator that does not malfunction in distinguishing between noise and signals even when five signals with phase misalignment are input by removing narrow pulses caused by phase misalignment of five signals. It is on offer.

[Summary of the invention]

In order to achieve this purpose, two loop antennas are placed in a partial discharge test circuit consisting of a power supply, a coupling capacitor, and a specimen connected in parallel. A waveform shaping circuit is provided that detects the current flowing through each of the loop antennas, and a waveform shaping circuit that converts the terminal voltage of the impedance into a signal indicating positive polarity or negative polarity. A logic circuit that discriminates between a partial discharge signal and a noise signal based on the combination and outputs a high level signal for a partial discharge signal and a low level signal for a noise signal, and a logic circuit that inputs the output of the waveform shaping circuit and outputs a signal in the first half wave period of the signal. A first half-wave discrimination circuit that generates a high-level signal and a low-level signal thereafter, and the outputs of the logic circuit and the first half-wave discrimination circuit are input, and when both of the two signals are high-level signals, the signal becomes high. A signal and first half-wave circuit that generates a level signal, an output of the signal and first half-wave circuit, and a terminal voltage of an impedance provided in the circuit of the test object are input, and the signal and first half-wave circuit When the output signal of is a high level signal, outputs the first half wave of the terminal voltage of the impedance.
In a partial discharge measuring device comprising an SN gate circuit and a discharge pulse measuring device for measuring the output of the SN gate circuit, the logic circuit and the signal AND first
A narrow-width pulse removal circuit is inserted between the half-wave circuit and the high-level signal outputted from the logic circuit to pass through when the time width exceeds a certain preset time in the range of 100 ns to 1 μs. This is the characteristic of the partial discharge measuring device.

Further, it is preferable that a delay circuit that delays the analog signal by a delimiting time is inserted between the detector and the SN gate circuit.

[Embodiments of the invention]

FIG. 1 shows a circuit block configuration of an embodiment of a noise discriminator for partial discharge measurement according to the present invention. In addition to the waveform shaping circuit 16, logic circuit 17, first half-wave discrimination circuit 18, signal AND first half-wave circuit 19, and SN gate circuit 20, which function in the same manner as shown in FIG.
A narrow pulse removal circuit 21 and a delay circuit 22 according to the present invention are additionally constructed. The logic circuit 17 discriminates whether it is a signal or noise by comparing the polarity combinations of the five signals with the combinations shown in _FIG.
=H, produces an output signal v ₆ where v ₆ =L in the case of noise or no signal. However, H is a pulse of 1.5V or more, and L is a pulse of 1.5V or less. If the pulse width at which v ₆ =H is T _H , a narrow pulse around T _H =100 ns is generated as the output signal v ₆ of the logic circuit 17 into which noise that causes phase misalignment in the five signals is input. On the other hand, in the case of a signal input, it produces a signal v ₆ of T _H =1 μs to 10 μs. As described above, T _H due to the partial discharge signal clearly tends to be longer than T _H due to phase misalignment noise. Therefore, the narrow-width pulse removal circuit 21 is a circuit that eliminates malfunctions due to waveform irregularities by regarding the signal v ₆ with a short pulse width T _H as noise and the signal v ₆ with a long pulse width T _H as a partial discharge. That is, the circuit 21 determines the magnitude of T _H and the other cutting time width W _O as follows, and thereby outputs the signal v ₆
A signal that identifies whether it is noise or a signal and displays this
Output v ₁₀ .

When T _H ≧W _O , v ₁₀ =H When T _H <W _O , v ₁₀ =L However, v ₁₀ =H indicates a signal, and v ₁₀ =L indicates noise or no signal. W _O is 100ns~
It is best to set it to an appropriate value in the 1μs range.

FIG. 2 shows a situation in which the narrow pulse signal v ₆ caused by out-of-phase noise is removed. When power supply noise causing phase misalignment is input to the five signals v ₁ to v ₅ , the logic circuit 17 outputs a signal v ₆ . However, T _H < W _O
Therefore, the signal v ₁₀ =L.

FIG. 3 shows the situation when a partial discharge signal is input. In this case, since T _H ≧W ₀ , the signal v ₁₀ = H
becomes.

In FIG. 1 described above, the first half-wave discrimination circuit 1
8 outputs a signal _v7 which is H in the first half wave of the input signal and L in the second and subsequent half waves. This operating situation is shown in FIGS. 2 and 3.

The signal AND first half-wave circuit 19 has two signals v ₇ ,
When v ₁₀ is input and both conditions of v ₁₀ =H, that is, a partial discharge signal, and v ₇ =H, that is, the first half wave of the signal, are satisfied, an output signal v ₁₁ =H is produced. On the other hand, v ₇ =
If L or v ₁₀ =L, then v ₁₁ =L. In FIG. 2, v ₁₀ =L and v ₇ =H, so v ₁₁ =L. In FIG. 3, v ₁₀ =H and v ₇ =H, so v ₁₁ =H.

The SN gate circuit 20 receives an analog signal v ₁₂ and a digital signal v ₁₁ and produces an output signal of v ₁₃ =V 12 when v ₁₁ = H, and produces an output signal of v ₁₃ = V ₁₂ when v ₁₁ = L, regardless of v ₁₂ .
0V is output. In Figure 2, v ₁₁ = L and v ₁₃ =
0V, in FIG. 3, v ₁₁ = H and v ₁₃ = v ₁₂ .

By the way, v ₁₁ =H produces a phase lag W _O compared to v ₂ as shown in FIG. The delay circuit 22 is
This circuit delays the phase of input signal v ₂ by W _O , and outputs signal v ₁₂ .

This delay circuit 22 has the effect of outputting the signal v 13 as the signal v ₁₃ without attenuating the signal v ₂ .

FIG. 4 shows a narrow pulse removal circuit 2 according to the present invention.
An example of No. 1 is shown below.

In the figure, the truth table of the circuit operation of the buffer amplifier 4 is as shown in FIG. 5a, where the input signal and the output signal are equal. This circuit is a semiconductor circuit for impedance matching and power amplification.

The truth table of the circuit operation of the inverter 25 has the effect of inverting the input signal, as shown in FIG. 5b.

The truth table of the circuit operation of the AND circuits 26, 27, and 28 is as shown in FIG. produces an output signal L.

The truth table of the circuit operation of the exclusive OR circuits 29 and 30 is as shown in FIG. and if the two signals A and B are not equal, i.e. A=H, B=L or A=L, B
=H produces an output signal H.

The D-type flip-flop circuit 31 receives as input signals a clear pulse v _CL , a clock pulse v _CK ,
A data pulse v _D is input and produces an output signal Q,. The truth table of the circuit operation is as shown in Figure 5e, when v _CL = L, Q = regardless of the values of v _CK and v _D.
L, yielding =H. When v _CL = H, v _CK changes from L to H
When it changes to , Q = v _D , = _D occurs. v _CL
=H, v _CK =L, Q is held at the previous value Q _D , _D regardless of v _D .

The operation of the circuit shown in FIG. 4 described above will be explained with reference to FIG. As shown in FIG. 6, the input signal u _i with pulse width T _H
When input to the input terminal I in FIG. 4, the output signal _v14 of the buffer amplifier 24 requires charging of the CR circuit consisting of the resistor 32 and the capacitor 35, so that it has the waveform of _v14 shown in FIG.

v ₁₄ is an input signal of the AND circuit 26 when v ₁₄ <
It operates as L at 1.5V and H when v ₁₄ <1.5V.
Therefore, the AND circuit 26 to which the two signals v _i and v ₁₄ are input has a resistor 32 and a capacitor 35 for v _i.
A signal v ₁₅ is generated with a delay of a time W _O determined by the charging time constant of .

When v ₁₅ is added to the CR circuit consisting of resistor 33 and capacitor 36, the terminal voltage of capacitor 36 is
For _v16 , charging waveforms and discharging waveforms are obtained as shown in FIG.

v ₁₆ operates as an input signal to the exclusive OR circuit 30 as L when v ₁₆ <1.5V and as H when v ₁₆ >1.5V. Therefore, the circuit 30 to which _the two signals v ₁₅ and v ₁₆ are input, as shown in FIG.
→H and H→L synchronized output signals v ₁₇ are generated.

The AND circuit 27 to which the two signals v _i and v ₁₇ are input is
As shown in FIG. 6, a signal _v18 is output.

By the way, Fig. 6 shows the case where T _H > W _O , but if T _L < W _O , even if v _i is input, v ₁₄ < 1.5V.
Therefore, v ₁₅ =L remains.

Thus, the conditions for generating a pulse in which the signal _v18 goes high are as follows: when T _H < W _O , the pulse occurs at time t=W _O ;
It has the property of non-occurrence when T _H < W _O.

When v _i is applied to the CR circuit consisting of resistor 34 and capacitor 37, the terminal voltage v ₁₉ of capacitor 37 is
Since charging and discharging time is required, the signal waveform shown in FIG. 6 is obtained.

Exclusive OR circuit 29 to which two signals v _i and v ₁₉ are input
The output signal v ₂₀ has the waveform shown in FIG. Output signal v ₂₁ of inverter 25 to which signal v ₂₀ is input
As shown in FIG. 6, when the voltage of v _i changes, that is, from L to H or from H to L, v ₂₁ =L, and otherwise, V ₂₁ =H.

A clock pulse is applied to the flip-flop circuit 31,
When the signals v ₁₈ , v _i , and v ₂₁ are input as the data pulse and the clear pulse, respectively, the signal Q shown in FIG. 6 is output as the output signal Q, and furthermore, v _O is output as the output signal of the AND circuit 28. .

Thus, when a signal v _i of pulse width T _H is input, the circuit operation in Fig. 4 is in the time domain W _O when T _H > W _O
Generate a pulse such that v _O =H over <t<T _H ,
When T _H <W _O , v _O remains low and no pulse is generated.

One embodiment of the delay circuit 22 is shown in FIG.

Inguntans 38, 39, 40, 41, 4
2. It is composed of capacitors 43, 44, 45, 46, 47 and a resistor 48. An example of the frequency phase characteristics of this circuit is shown in FIG. That is, a high-frequency three-wave generator having a steep cut-off characteristic with a high-frequency cut-off frequency f _C =1 MHz and f=2f _{C and} a signal attenuation of -60 dB is used. As shown in Figure 7, this circuit not only has the signal delay effect of a ladder circuit consisting of an inductance and a capacitor, but also has a high frequency three-wave effect, so it reduces the amplifier thermal noise component in the input signal. It has the effect of removing

〔Effect of the invention〕

As described above, according to the present invention, a circuit removes narrow pulses from the output section of a logic circuit that discriminates polarity combinations using the internal configuration of a noise discriminator that detects five signals and discriminates between noise and signals by distinguishing polarity combinations. This arrangement has the effect of preventing noise discrimination from malfunctioning even if five signals with phase misalignment are input.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the partial discharge measuring device according to the present invention, FIGS. 2 and 3 are explanatory diagrams showing the operating principle of the partial discharge measuring device according to the present invention, and FIG. A circuit diagram showing an embodiment of a partial circuit of the partial discharge measuring device according to the invention, FIG.
6 is a timing diagram showing the operation of FIG. 4, FIG. 7 is a diagram showing an embodiment of a partial discharge measuring device according to the present invention, and FIG. The figure is an explanatory diagram showing the operating characteristics of Fig. 7,
Fig. 9 is a block diagram showing an example of a conventional partial discharge measuring device, Fig. 10 is an explanatory diagram showing the operating principle of the block diagram in Fig. 9, and Figs. FIG. 13 is a block diagram showing details, and a timing diagram showing the operation of FIG. 12. 1... Test sample, 2... Power supply, 3... Coupling capacitor, 4, 5... Loop antenna, 6, 7, 8,
9, 10...Detection impedance, 11...Measuring device, 12...Signal detector, 13...Signal amplifier,
14...Noise discriminator, 15...Pulse measuring device, 1
6... Waveform shaping circuit, 17... Logic circuit, 18...
...First half-wave discrimination circuit, 19... Signal and first half-wave circuit, 20... SN gate circuit, 21... Narrow pulse removal circuit, 22... Delay circuit, 24... Buffer amplifier, 25... Inverter ,26,2
7, 28...AND circuit, 29, 30...exclusive
OR circuit, 31...flip-flop circuit.

Claims (1)

[Claims] 1. Two loop antennas are arranged in a partial discharge test circuit configured by connecting a power supply, a coupling capacitor, and a specimen in parallel, and the power supply, the coupling capacitor, the specimen, and the two loop antennas are connected in parallel. a waveform shaping circuit that converts the terminal voltage of the impedance into a signal indicating positive polarity or negative polarity; A logic circuit that discriminates between a discharge signal and a noise signal and outputs a high level signal for a partial discharge signal and a low level signal for a noise signal, and a logic circuit that inputs the output of the waveform shaping circuit and outputs a high level signal during the first half wave period of the signal. After that, a first half-wave discrimination circuit that generates a low-level signal, the outputs of the logic circuit and the first half-wave discrimination circuit are input, and when both of the two signals are high-level signals, a high-level signal is generated. The signal and first half-wave circuit to be generated, the output of the signal and first half-wave circuit, and the terminal voltage of the impedance provided in the circuit of the specimen are input, and the output signal of the signal and first half-wave circuit is inputted. In a partial discharge measuring device comprising an SN gate circuit that outputs the first half wave of the terminal voltage of the impedance when is a high level signal, and a discharge pulse measuring device that measures the output of the SN gate circuit, the logic The time width of the high level signal output from the logic circuit is between 100ns and 1μs between the circuit and the signal AND first half-wave circuit.
A partial discharge measuring device characterized in that a narrow-width pulse removal circuit is inserted that allows a pulse to pass when it exceeds a predetermined time period set in advance. 2. The partial discharge measuring device according to claim 1, characterized in that a delay circuit that delays the analog signal by the delimitation time is inserted between the detector and the SN gate circuit.