JPH0548482B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a power supply for an information processing device, a power failure detection signal from a power failure detection circuit that detects a power failure or instantaneous interruption of input AC power is monitored by a counter, and when a set time is exceeded. The ready signal of the power supply is forcibly cut off, and the ready signal is turned on again after the input AC power is restored.This allows the monitoring time to be set extremely accurately and variably.
It has also become possible for the processing device to automatically restart processing.

[Industrial application field]

The present invention relates to a power supply in an information processing device, and more particularly to a power outage handling method for protecting the information processing device from malfunctioning when a power outage or instantaneous power outage occurs.

[Conventional technology]

In power supplies for information processing devices, the ready signal of the power supply is cut off to prevent malfunctions due to power outages, instantaneous interruptions, and other power supply abnormalities.

When the information processing device side detects that the "ready signal" is disconnected, it performs processing such as saving the register, and then enters a hibernation state, thereby protecting the information processing device from malfunctions.

However, since the DC output of the power supply control unit is held for a longer time, the power supply voltage of the information processing device may drop before the power supply control unit detects an abnormality and disconnects the "ready signal", causing malfunction. There is a danger that this will happen.

Therefore, a power outage detection section that detects a voltage drop in the input AC power supply is provided to detect a power outage caused by this, and thereby cut off the "ready signal".

Conventionally, a relay is used to detect this power outage, and it is connected to a DC voltage obtained by full-wave rectification of the input AC power supply, and when the voltage drops below a certain level for a certain period of time, it is detected as a power outage. "Ready signal"
I was trying to disconnect it.

[Problem that the invention seeks to solve]

The delay time from when the power outage detection circuit detects a power outage or instantaneous interruption until the "ready signal" is disconnected is as follows:
Guaranteed instantaneous interruption time of information processing equipment power supply (for example,
From a time T ₁ (e.g. 20ms) slightly larger than T 1 (e.g. 10ms) to a time T ₂ (e.g.
70ms).

The conventional power failure detection method described above has a problem in that the relay operation delay time is inaccurate and varies, and it is difficult to adjust it.

The present invention aims to provide a new power outage processing method that solves these problems.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the power outage processing method of the present invention.

In Fig. 1, 1 is a power failure detection circuit, which applies a DC voltage obtained by full-wave rectification of an input AC power source to a voltage divider circuit including a constant voltage diode, and connects the variable voltage side of the voltage divider circuit to a transistor circuit. A light emitting diode of a photocoupler is connected to the input and connected to its output circuit, the light emitting diode of the photocoupler is configured to emit light when the rectified voltage exceeds the Zener voltage of the voltage regulator diode, and a secondary side phototransistor of the photocoupler is connected to the output circuit of the photocoupler. outputs more photoelectric conversion voltage. The input AC power source and the photoelectric conversion voltage output are isolated by a photocoupler.

2 is a counter which counts clocks (CLK) from the time when the power outage detection circuit 1 detects a power outage and outputs a count over signal one hour later.

3 is a flip-flop which is inverted by the count over signal of counter 2;

Reference numeral 4 denotes a gate circuit which inputs the "ready signal" RDY ₁ from the power supply control section and the output signal of the flip-flop 3, and outputs the "ready signal" RDY ₂ which is cut off when a power failure is detected.

Reference numeral 5 denotes a means for generating a signal that receives a count-over signal, which is the output of the counter, and resets the flip-flop when a preset time has elapsed since the count-over signal was turned off.

[Effect]

With the above configuration, the "ready signal" of the power supply can be cut off when the voltage drop continues for a preset certain period of time.

This fixed time can be arbitrarily selected from the preset value setting of the counter 2, and since the time is measured by clock counting, it is extremely accurate.

By providing means 5 for sending a signal to reset the flip-flop 3, as shown by the broken line in FIG. Then, the "ready signal" can be input again.

〔Example〕

According to the embodiments shown in FIGS. 2 and 3 below,
The present invention will be explained in more detail.

FIG. 2 is a circuit diagram of the first embodiment of the present invention, which includes only the power failure processing section.

In FIG. 2, 11a, 11b, 11c, 1
1d is a bridge-connected diode, which performs full-wave rectification.

12 is a shunt resistor, resistors 13 and 15 and a constant voltage diode 14 form a voltage dividing circuit, and the resistor 13 and constant voltage diode 14 are held at a constant voltage (Zener voltage).

Therefore, transistor 16 is turned "on" when the input full-wave rectified voltage exceeds the Zener voltage value, and a square wave current flows.

When transistor 16 is turned on, resistor 1
A current flows through the light-emitting diode of the photocoupler 18 through the light-emitting diode 7 to emit light, and the phototransistor on the secondary side turns on.

The circuits 11a to 18 described above constitute the power failure detection circuit 1.

20 is the collector resistor of the secondary side phototransistor of the photocoupler 18, and as shown in the figure, the output signal of the photocoupler 18 is "low" level when the transistor 16 is "on" and "high" when it is "off".
It becomes a square wave with a level.

When the full-wave rectified voltage becomes equal to or less than the Zener voltage of the voltage regulator diode 14, the transistor 16 turns "off", and therefore the output of the phototransistor of the photocoupler 18 becomes a "high" level.

Reference numeral 21 denotes a flip-flop (FF1) which is operated by the output voltage of the photocoupler 18 and the clock voltage, inputs its output to the counter (CTR1) 22, and serves to prevent malfunctions by operating as a buffer.

The counter (CTR1) 22 is designed to count up the clock signal when the input is at a high level, and the output voltage of the photocoupler 18 is input as a reset signal to the counter (CTR1) 22, and the output voltage is set to a "low" level. It is reset when

Therefore, the counter (CTR1) 22 is immediately reset and does not count up while the AC input power is normal and the output signal of the photocoupler 18 is a rectangular wave.

However, if there is a power outage or a momentary interruption, and the photocoupler 18 goes into the "off" state and its output goes to the "high" level, the reset signal remains at the "high" level, and the counter (CTR1) 22 starts counting the clocks. do.

When the counter (CTR1) 22 counts over, a carry signal TC ₁ is sent to the counter (CTR2) 23
The counter (CTR2) 23 starts counting the clocks.

When the counter (CTR2) 23 counts over, a countover signal _TC2 is output, which inverts the flip-flop (FF2) 30.

By this, flip-flop (FF2) 3
The output of NAND gate 40 becomes "low" level, and the output of NAND gate 40 becomes "high" level, turning transistor 41 "on" and "ready signal" output RDY ₂
is considered to be a "low" level.

In other words, even if the "ready signal" RDY ₁ is received from the power supply control section, the "ready signal" is not output to the device side.
Can cut RDY ₂ .

Although there are two counters in FIG. 2, the number of counter stages is determined by the number of hours to be monitored and the period of the clock. For example, if the period of the clock is
If the time is 1μs and four 4-bit counters are used,
Accurate timekeeping up to approximately 65ms is possible.

Further, the monitoring time can be adjusted by setting a preset value of the counter.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, which includes a power recovery processing section.

In FIG. 3, the same symbols as in FIG. 2 indicate the same objects.

In this embodiment, the power supply is controlled by a microprocessor (MPU) 50.
"Ready signal" is microprocessor (MPU) 5
It is issued from 0.

Most of the circuitry is the same as in FIG. 2, and the operation is similar.

When a power outage occurs, the photocoupler 18 turns "off"
The counter (CTR1) 22,
(CTR2) 23 starts the counter, and if the power outage continues for more than the time set in the counter, the counter (CTR2) starts the counter.
2) A count over signal TC2 of 23 is output, and the flip-flop (FF2) 30 is inverted.

This allows the microprocessor (MPU)
Even if the "ready signal" RDY ₁ is output from the processor 50, the "ready signal" RDY ₂ output to the processing device side can be cut off.

In addition, when the input AC power is restored, the count over signal TC ₂ of the counter (CTR 2) 23 is received (the TC ₂ signal remains at the "low" level when the power is restored), and the internal microprocessor (MPU) 50 After monitoring the time, the flip-flop (FF2) is activated after a certain period of time (the time required for the DC voltage to rise).
A reset signal is sent to 30.

As a result, the "ready signal" is re-introduced.
The processing device side starts processing again.

In this way, in the event of an input power outage, the "ready signal" can be forcibly cut off before the DC power supply on the processing equipment side drops, preventing malfunctions on the processing equipment side. By sending out the "ready signal" again, the processing device can automatically resume processing.

〔Effect of the invention〕

As explained above, according to the present invention, malfunctions can be prevented by extremely accurately setting the time until the "ready signal" is forcibly disconnected after a power outage is detected, and its practical effects There is something big about it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit diagram of a first embodiment of the present invention, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. In the drawing, 1 is a power failure detection circuit, 2 is a counter, 3 is a flip-flop, 4 is a gate circuit, and 5
are reset signal sending means, 11a, 11b, 11
c, 11d are diodes, 12, 13, 15, 1
7, 20, 42 are resistors, 14 is a constant voltage diode, 16, 41 are transistors, 21, 30 are flip-flops (FF), 22, 23 are counters (CTR), 40 is a NAND gate, 50 is a microprocessor (MPU) ), respectively.

Claims (1)

[Claims] 1. A voltage obtained by direct full-wave rectification of an AC input power source is applied to a voltage dividing circuit including a constant voltage diode, and the variable voltage side of the voltage dividing circuit is connected to the input of a transistor circuit. A light emitting diode of a photocoupler is connected to the output circuit, and the light emitting diode of the photocoupler is configured to emit light when the rectified voltage exceeds the Zener voltage of the constant voltage diode, and a photoelectric conversion voltage is output from the secondary side phototransistor of the photocoupler. A power outage detection circuit 1 that outputs a power outage detection circuit 1, a counter 2 that receives the output voltage waveform of the power outage detection circuit 1 and counts clocks of a constant period while the light emitting diode does not emit light, and a flip-flop 3 that holds the count over signal of the counter 2. a gate circuit 4 which controls the transmission of the power ready signal from the output signal of the flip-flop 3; and a gate circuit 4 which receives the count over signal which is the output of the counter 2 and which is set in advance from when the count over signal is turned off. and a reset signal generating means 5 configured by using a power supply control microprocessor to generate a signal for resetting the flip-flop 3 when counting the time that the rectified voltage is applied to the zener of the constant voltage diode. The power supply ready signal is forcibly cut off when the voltage does not exceed the set time period, and when the AC input power is restored after the power supply ready signal is cut off, the counter 2 is reset and the counter 2 is reset to the count value. A power outage processing method characterized in that the flip-flop 3 is reset after a set time has elapsed since the over signal is turned off, and the ready signal is inputted again.