JPH054852B2 - - Google Patents
Info
- Publication number
- JPH054852B2 JPH054852B2 JP61185356A JP18535686A JPH054852B2 JP H054852 B2 JPH054852 B2 JP H054852B2 JP 61185356 A JP61185356 A JP 61185356A JP 18535686 A JP18535686 A JP 18535686A JP H054852 B2 JPH054852 B2 JP H054852B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- supply voltage
- reset
- main power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バツテリ等でバツクアツプされた
CPUシステムのリセツト回路に関するものであ
る。[Detailed description of the invention] [Industrial application field] The present invention
This relates to the reset circuit of the CPU system.
バツテリ等でバツクアツプされたCPUシステ
ム、例えば、CPUを組込んだ絶対値エンコーダ
等においては、リセツト信号入力の配線をコネク
タ等に準備した場合、誤操作した時や、バツクア
ツプの状態から主電源を立ち上げた時、回路内の
時定数の影響により誤リセツト信号を送出し、ト
ラブルが発生することがある。
In a CPU system that has been backed up due to a battery, for example, an absolute value encoder with a built-in CPU, if the reset signal input wiring is prepared in a connector, etc., it may be necessary to restart the main power supply in the event of an erroneous operation or from a backed up state. When this occurs, an erroneous reset signal may be sent due to the influence of the time constant within the circuit, causing trouble.
これを図面に基づき説明すれば次の通りであ
る。 This will be explained based on the drawings as follows.
第１図は従来のCPUシステムのリセツト回路
を示すもので、VBAはバツテリ電源電圧、Ｌは高
周波ノイズ消去用インダクタンス、D1はダイオ
ード、Ｒは抵抗、INVはインバータ、Ｃはコン
デンサである。 Figure 1 shows the reset circuit of a conventional CPU system, where VBA is the battery power supply voltage, L is the inductance for high frequency noise cancellation, D1 is the diode, R is the resistor, INV is the inverter, and C is the capacitor.
今、主電源電圧が＋5VでCPUシステムがリセ
ツトする場合を考えると、VCC＝VBA＝OV→VBA
＝3Vの状態、つまりCPUシステム全体の電源が
落ちていて、なおかつバツテリバツクアツプの接
続も行われていない状態から第３図に示すように
バツクアツプ電源VBAが印加された時、CPU、
INV用の電源VCCに3Vが入力されると同時に、リ
セツト信号RESが“Ｈ”となり、CPUはリセツ
トされる。 Now, if we consider the case where the main power supply voltage is +5V and the CPU system is reset, V CC = V BA = OV → V BA
= 3V, that is, when the entire CPU system is powered down and the battery backup is not connected, when the backup power supply V BA is applied as shown in Figure 3, the CPU,
At the same time that 3V is input to the INV power supply VCC , the reset signal RES becomes "H" and the CPU is reset.
この時のリセツト信号の長さは、インバータ
INVの入力電圧VaがインバータINVの入力論理
の“Ｌ”レベルの範囲内にある時間によつて決ま
り、RC時定数の違いによつてインバータINVの
入力電圧Vaの立ち上がり時間が変つてくる。 The length of the reset signal at this time is
It is determined by the time that the input voltage Va of the inverter INV is within the "L" level range of the input logic of the inverter INV, and the rise time of the input voltage Va of the inverter INV changes depending on the difference in the RC time constant.
この入力電圧Vaは、立ち上がると約3Vとな
り、バツクアツプの状態が確立する。 When this input voltage Va rises, it becomes approximately 3V, and a backup state is established.
ここで、主電源電圧＋5Vが入つた場合、IC用
電源VCCは＋5Vとなり、ダイオードD1を経てバ
ツテリ電圧VBAでバツクアツプされた時と同様の
経路に＋5Vは印加される。そして第３図に示す
ように入力電圧Vaを3V→5Vへと変化させるが、
この時、RC時定数によりリアルタイムには5Vに
ならない為、立ち上がりの初期段階においては、
入力電圧VaはインバータINV入力論理の“Ｌ”
レベルの範囲内にある事が考えられる。 Here, when the main power supply voltage +5V is applied, the IC power supply V CC becomes +5V, and +5V is applied through the same path as when it is backed up by the battery voltage V BA via diode D1 . Then, as shown in Figure 3, the input voltage Va is changed from 3V to 5V, but
At this time, because it does not reach 5V in real time due to the RC time constant, at the initial stage of rising,
Input voltage Va is “L” of inverter INV input logic
It is possible that it is within the level range.
この状況は、一般的なICの特性としてそのDC
電気的特性に記載されているように、入力論理を
“Ｈ”とみなすしきい値（高レベル入力電圧
VIH）が、IC電源電圧VCCに依存する事が要因と
なつており（VCC＝3VのときVIH＝2.0V、VCC＝
5VのときVIH＝3.5V）、主電源＋5Vが入力され
た事でIC用電源電圧（VCC）はステツプ状に上
昇、同時に高レベル入力電圧値VIHが大きくな
り、RC時定数により過渡的に上昇する入力電圧
値Vaを一時的超える為にインバータ入力論理が
“Ｌ”レベルとなる。 This situation is a characteristic of general ICs and its DC
As described in the electrical characteristics, the threshold value (high level input voltage
The factor is that VIH) depends on the IC power supply voltage V CC (when V CC = 3 V, VIH = 2.0 V, V CC =
(VIH = 3.5V when the main power supply +5V is input), the IC power supply voltage (V CC ) rises in steps, and at the same time the high level input voltage value VIH increases, causing a transient increase due to the RC time constant. In order to temporarily exceed the increasing input voltage value Va, the inverter input logic becomes "L" level.
よつて、その範囲内の間、リセツト信号は
“Ｈ”となり、時間的には１回目のリセツトより
も短いと考えられるが、再びCPUをリセツトし
てしまう。 Therefore, while within this range, the reset signal becomes "H", and although the time is considered to be shorter than the first reset, the CPU is reset again.
その状況は第３図のVa、RESに示す通りであ
る。 The situation is shown in Va and RES in Figure 3.
そこで、本発明は主電源（＋5V）の立ち上が
り時に生じる誤リセツトを防止するリセツト回路
を提供するものである。 Therefore, the present invention provides a reset circuit that prevents erroneous resets that occur when the main power supply (+5V) starts up.
本発明は上記の問題点を解決するためなされた
もので、バツクアツプ電源電圧に主電源電圧を順
方向ダイオードを介して重畳し、その重畳電圧を
RC時定数回路の抵抗を介してCPUシステムのリ
セツト端子に印加するリセツト回路において、前
記RC時定数回路の抵抗とコンデンサの共通接続
点に順方向ダイオードを介して主電源電圧を印加
するように構成したものである。
The present invention has been made to solve the above problems, and the main power supply voltage is superimposed on the backup power supply voltage via a forward diode, and the superimposed voltage is
The reset circuit applies power to the reset terminal of the CPU system through the resistor of the RC time constant circuit, and is configured to apply the main power voltage to a common connection point between the resistor and the capacitor of the RC time constant circuit through a forward diode. This is what I did.
第２図は本発明の実施例を示すもので、第１図
に示す従来回路において、インダクタンスＬと順
方向ダイオードＤとの共通接続点Ｂと、CR時定
数回路の抵抗ＲとコンデンサＣの共通接続点Ａ間
に順方向ダイオードD2を設けたものである。
FIG. 2 shows an embodiment of the present invention. In the conventional circuit shown in FIG. A forward diode D2 is provided between the connection points A.
ここではバツクアツプ電源電圧VBAが3Vから
5Vになる時にリセツトしてしまうのが問題であ
り、電源電圧＋5V印加時に時間的遅れなく、バ
ツクアツプ電源電圧VBAを変化させる事でこれを
解決する事ができる。リセツト信号RES′の電圧
変化は、第３図に示す通りである。 Here, the backup power supply voltage V BA starts from 3V.
The problem is that it resets when the voltage reaches 5V, and this can be solved by changing the backup power supply voltage V BA without any time delay when the power supply voltage +5V is applied. The voltage change of the reset signal RES' is as shown in FIG.
第１図に示した従来の接続では主電源電圧＋
5Vが印加された場合、インバータ入力電圧Vaの
立ち上がりはRC時定数に影響されるので、第１
図においてＢ点とＡ点を単に接続する事で時定数
に関係せずインバータ入力電圧Vaを立ち上げる
事ができる。 In the conventional connection shown in Figure 1, the mains voltage +
When 5V is applied, the rise of the inverter input voltage Va is affected by the RC time constant, so the first
In the figure, by simply connecting point B and point A, the inverter input voltage Va can be raised regardless of the time constant.
しかし、これだけではバツクアツプ時電流ｉが
流れてしまいCPU、INV用電源だけではなく、
不必要なICの電源をオンしてしまう。そこで本
発明ではD1ダイオードをＢ点とＡ点間に接続す
る事により主電源電圧＋5VはインバータINVに
直に印加され、しかもダイオードD2は逆方向な
ので電流ｉが流れないようにしたものである。 However, this alone causes the current i to flow during backup, and not only the CPU and INV power supply.
Turning on power to unnecessary ICs. Therefore, in the present invention, the main power supply voltage +5V is directly applied to the inverter INV by connecting the D1 diode between points B and A, and since the diode D2 is in the opposite direction, the current i does not flow. be.
これによりインバータ入力電圧Va′はVBA入力
時には従来と同様に機能し＋5V入力時にはRC時
定数の影響を受けずに主電源電圧＋5Vと同様に
瞬時に電圧印加が行なわれる為、高レベル入力電
圧値（VIH）の変化によつて入力論理が反転し
てしまう事を防止する。 As a result, the inverter input voltage Va' functions as before when inputting VBA , and when inputting +5V, the voltage is applied instantaneously in the same way as the main power supply voltage +5V without being affected by the RC time constant, resulting in a high level input voltage. Prevents the input logic from being reversed due to changes in the value (VIH).
従来の機能を満足させたまま、主電源電圧の立
ち上げ時のインバータ入力電圧Va′の過渡的な上
昇を抑制する事により、誤リセツトを防止する事
が可能となつた。
It has become possible to prevent erroneous resets by suppressing the transient rise in the inverter input voltage Va' when the main power supply voltage starts up, while still satisfying the conventional functions.
第１図は従来のリセツト回路図、第２図は本発
明の実施例の電気回路図、第３図は各部の電圧・
変化を示す図である。
D1，D2…ダイオード、Ｌ…インダクタンス、
Ｒ…抵抗、Ｃ…コンデンサ、INV…インバータ。
Fig. 1 is a conventional reset circuit diagram, Fig. 2 is an electric circuit diagram of an embodiment of the present invention, and Fig. 3 is a diagram of voltages and voltages at various parts.
It is a figure showing a change. D1 , D2 ...diode, L...inductance,
R...Resistor, C...Capacitor, INV...Inverter.
Claims (1)
ダイオードを介して重畳し、その重畳電圧をRC
時定数回路の抵抗を介してCPUシステムのリセ
ツト端子に印加するリセツト回路において、前記
RC時定数回路の抵抗とコンデンサの共通接続点
に順方向ダイオードを介して主電源電圧を印加す
るように構成したことを特徴とするCPUシステ
ムのリセツト回路。1 The main power supply voltage is superimposed on the backup power supply voltage via a forward diode, and the superimposed voltage is
In the reset circuit that applies the voltage to the reset terminal of the CPU system through the resistance of the time constant circuit,
A reset circuit for a CPU system, characterized in that the main power supply voltage is applied to a common connection point between a resistor and a capacitor of an RC time constant circuit via a forward diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185356A JPS6342517A (en) | 1986-08-08 | 1986-08-08 | Reset circuit for cpu system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185356A JPS6342517A (en) | 1986-08-08 | 1986-08-08 | Reset circuit for cpu system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6342517A JPS6342517A (en) | 1988-02-23 |
| JPH054852B2 true JPH054852B2 (en) | 1993-01-21 |
Family
ID=16169354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61185356A Granted JPS6342517A (en) | 1986-08-08 | 1986-08-08 | Reset circuit for cpu system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6342517A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0627117Y2 (en) * | 1989-01-13 | 1994-07-27 | 川澄化学工業株式会社 | Bag containing medium |
-
1986
- 1986-08-08 JP JP61185356A patent/JPS6342517A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342517A (en) | 1988-02-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |