JPH054866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse transmission method, and particularly to a transmission path coding method suitable for asynchronous time division multiplex transmission in which asynchronous pulse trains are synchronized and transmitted.

[Prior art]

Conventionally, as a method for synchronizing asynchronous pulse trains, methods as shown in FIGS. 1a and 1b have been proposed. In other words, “1” in the original signal pulse train a is encoded as “11” or “00”, and “0” is encoded as “1”.
Alternatively, it is encoded as "0", and when there is no signal (empty signal E), it is expressed as "111" or "000" and transmitted as code string b. When asynchronous signals are synchronized and transmitted in this way, there may be cases where the original signal does not exist (transmitted), so it is also necessary to define a block code corresponding to the empty signal "E". Furthermore, in this conventional encoding method, the length of the block code corresponding to each original signal is different, so that a change point is created at the boundary between blocks in order to identify the blocks. For this reason, two types of modes are prepared for each original signal, such as "11" and "00", in which the levels of all pulses in the block are inverted, and one of them is selected and used. This switching and use of multiple types of code strings representing one source signal information is called mode switching.

As can be seen from the figure, in this transmission code, the condition of DC balance is not satisfied and a DC component is generated. Since direct current components are generally cut off in a transmission path, when a code string including a direct current component as shown in FIG. 1b is transmitted, distortion occurs on the receiving side, causing code errors.

[Purpose of the invention]

An object of the present invention is to provide an encoding system that satisfies the conditions of DC balance as well as synchronization.

[Summary of the invention]

In order to achieve the above object, the present invention uses both a DC-balanced code within a block and a DC-balanced code by mode switching. First, the premise of the encoding method of the present invention is that (1) mode switching is performed between two types of modes in which the levels of all pulses are inverted so that changing points occur at the boundaries between blocks. . Furthermore, block codes such as "11" or "00" used in FIG. 1b are unbalanced within a single block, and the first and last levels of the block are the same. These block codes are relatively short and easy to distinguish from others. (2) One of the three types of original signal information, 1, 0, and E, is assigned a block code that is unbalanced within a single block and whose first and last levels are the same. point as the second premise.

The first feature of the present invention is that in addition to these premises, (3) the remaining 2 of the three types of original signal information 1, 0, and E
Each type has a different level at the beginning and end of the block, and a DC-balanced block code is assigned within the block.

An example in which "11" or "00" is assigned to original signal 1 will be explained. For example, when the original signal is 1111, the block code string becomes 11001100 according to condition (1), and DC balance is achieved. The problem arises when another block code is inserted between these block codes. If a block code with the same first and last level of the block, such as "1" or "0", is assigned to the original signal 0, the block code string will be 110110110 for the original signal 1010, resulting in DC imbalance. occurs. On the other hand, if block codes are assigned to the remaining 0 and E under the condition (3) above, such an imbalance will not occur. For example, when 0 is set to “10” or “01”, the original signal
For 1010, the block code string is 11010010110100. In other words, even if a block code corresponding to 0 is inserted, the block code corresponding to 1, which itself is unbalanced, always generates two modes of opposite polarity alternately, so DC balance is maintained. Also,
When the original signal is 000, the same mode continues as 010101, but since the block code for 0 is originally DC balanced, no unbalance occurs in this case either. E
The same thing can be said when a block code corresponding to the block code is inserted or when it is consecutive.

Figure 1c shows an example of the encoding method according to the first feature, in which "1" of the original signal a becomes "11" or "00" and "0" becomes "10" or "01". , and "E" is an example of converting the prefecture code to "111000" or "000111". No matter what the original signal string is, the converted block code string will be DC-balanced.

The second feature of the present invention is that, in addition to the premises (1) and (2) above, (3') the remaining two types of original signal information of three types, 1, 0, and E, are all block blocks. (4) Among the remaining two types of block codes, for intra-block unbalanced block codes, in addition to the two types of modes in which all pulses are inverted, There are four types of modes in total, two types of which are composed of combinations of pulses that have DC components with the same absolute value but different polarities and whose initial and final levels are the same. The point is encoded. For example, if "1110" is assigned to the original signal E, four types of mode switching are performed: 0001, which is the inverted mode, 1000, and 0111. If the original signal has consecutive modes with the same initial level, such as EE, 11101000 or
By alternately using DC component modes with different polarities such as 00010111, it is possible to perform encoding without causing unbalance.

FIG. 1d shows an example of the code conversion method according to the second feature, in which "1" of the original signal a becomes "11" or "00", "0" becomes "01" or "10", "E ” is converted to “0001” or “1110” or “1000” or “0111”. In this example as well, whatever the original signal string, the converted block code string will be DC-balanced.

[Embodiments of the invention]

The present invention will be explained below using examples. FIG. 2 is a block diagram of an embodiment implementing the pulse transmission line encoding method according to the present invention. FIG. 3 shows the waveforms of each part of the transmitter of the above embodiment.

In FIG. 2, the original signal S is applied to elastic memory 2. In FIG. This is set to “1”, “0” and “E” by clock C _RT (sending side read clock).
(empty signal).

The clock C _S corresponding to the original signal S is the correction circuit 1
(transmission side clock position correction circuit), the position is corrected by line clock Cl, and the write clock C _WT (transmission side write clock) is
The time point at which the original signal S is written to the elastic memory is determined. The reason for performing this correction is to avoid simultaneous writing and reading.

FIG. 2 “1”, “0” and “E” signals read from the elastic memory 2 are transmitted to the encoding circuit 3.
encoded in . In this encoding circuit, a read clock pulse C _RT is also generated at the same time.

The details of the clock correction circuit 1, the encoding circuit 3, and the elastic memory will be explained in the following sections.
This will be explained using Figure 6.

FIG. 4 shows one embodiment of the clock correction circuit 1. Clock pulse C _l applied to input terminal 10
is applied to one side of the AND circuit 15 via the constant delay circuit 11 to avoid overlap with the read pulse. On the other hand, the signal clock pulse C _S applied to the input terminal 12 is applied to the pulse expander 13, and its output drives the flip-flop 14 and inhibits the gate 15. The reason for the pulse stretching is to avoid the set and reset of flip-flop 14 occurring extremely close to each other. The output of the flip-flop 14 is transferred to a differentiating circuit (inverter 16 and AND gate 1).
7) to obtain the write clock pulse _CWT .

Next, the operation of the elastic memory 2 will be explained using FIG. In the same figure, the signal pulse S is
They are stored in the order of memories 31 to 33, and when the contents of memory 31 are read out, the contents of memory 32 are transferred and the contents of memory 33 are transferred to memory 32. A signal is stored in memory 32 only if the signal is already stored in memory 31. The same applies to the memory 33.

Memories 41-43 are used to indicate whether or not a signal is stored in memories 31-33.

The above operation will be explained using FIG. 3. In the figure, when the waveform M ₁ ' is in an "on" state, it indicates that a signal is stored in the memory 31. _M1 is whether the stored signal is “1” or “0”
It shows whether

When M ₂ ' is in the "on" state, memory 31 is already occupied when the next signal arrives, so that signal will be written to memory 32. Waveform M ₂ indicates whether the signal is "1" or "0".

The operation of preferentially writing data from memory 31 is performed using gates 34-39 and 45-47 as described below.

First, the gate 45 allows the write pulse _CWT to pass when the memory 41 is "OFF", so
The memory 41 itself becomes “on” and the gate 3
4 and 35 are opened, and if the signal is "1", the memory 31 is set, and if it is "0", it is reset. The fact that the memory 41 is “on” means that
Since the memory 31 is already occupied, the gate 45 is not opened. Instead,
If the memory 42 is "OFF", the gate 46 allows the write pulse _CWT to pass through and opens the gates 36 and 37, so that a signal is written to the memory 32. The same applies to the memory 33. As shown in FIG. 5, "0" is always applied to the input terminal 48, so when the contents of the memory 43 are transferred to the memory 42 by applying the clock C _RT , the clock C “0” is written to the memory 43 in synchronization with _RT , and the state of the memory 43 becomes “OFF”. As a result, it can be shown that the memory 33 is empty information.

The signals read as described above are transmitted through gates 51 to 51.
“1” by read clock C _RT through 53
It is read as “0” and “E”. As can be seen from Figure 5, the read clock C _RT is
It is also used as a shift pulse for 1-33 and 41-43.

Next, the encoding circuit will be explained using FIG. Signals "1", "0" and "E" read from the elastic memory 3 are applied to input terminals 61, 62 and 63 of the encoding circuit, respectively. The "1" signal is delayed by twice the clock period (2T) by the delay circuit 65. “0”
becomes two pulses delayed by T and 2T. “E”
becomes two pulses delayed by 3T and 6T. The waveform shown in Figure 3 is the result of combining these using the OR gate 70.
S _t , and when the trigger type flip-flop 71 is driven with this waveform, an encoded waveform S ₁ is obtained.

The outputs of the delay circuits 65, 67 and 69 are combined by the OR gate 72 to form the read clock pulse C _RT shown in FIG. 3, which is used as the read pulse for the elastic memory as described above.

That is, since "1" and "0" are encoded with 2 bits, after the "1" and "0" pulse signals shown in FIG. 3 are input from terminals 61 and 62, respectively, two time slots are minutes late or gate 7
2, and the C _RT shown in the figure is generated. Similarly, the "E" pulse signal is input to the OR gate 72 with a delay of 6 time slots, so that the C _RT shown in the figure is generated. Also, the reason why the C _RT is generated by delaying the “1” and “0” pulse signals by two time slots is because “1” and “0” are encoded into 2 bits, so This is because it is necessary to wait two time slots after the signal is read before reading the next signal. The same reason applies to "E". still,
The pulse signal that occurs first in C _RT in Fig. 3 is generated by a temporally earlier signal “0,” “1,” or “E” (not shown). .

The transmitter shown in FIG. 2 has been described above. In this transmitter, the asynchronous signal S is synchronized with the clock rate of the transmission line and is sent out as a DC-balanced signal S _l . This reaches the receiving section via the transmission path 5.

Next, the operation of the receiving section will be explained. The signal received via the transmission line 5 is pulse-regenerated in the regenerative repeater 101. From this regenerator, a regenerated signal 102 and a clock pulse 103 are supplied to a decoding circuit 104. The following operation will be explained using FIG.

FIG. 7e shows the regenerated pulse train (same as FIG. 3 S _l ), which is decoded as shown in FIG. 7i by the decoder 104 as described below. However, the waveform of i also includes the empty signal in decoded form (the section indicated by the arrow). Therefore, it is necessary to remove this section. For this purpose, the sky signal E detection signal j is used. This is detected from the shaded portion of the reproduced pulse train e, thereby erasing the shaded portions of the waveforms k and l. Pulse is “on” in waveform k
The part indicates that the signal “1” exists, and the part where the pulse is “on” in the waveform l indicates the signal “0”.
indicates the existence of Waveforms k and l are “off”
The section with a blank sign indicates that the signal is empty.

Next, set k and l to elastic memory 1.
05, but the empty signal E is not read. On the other hand, a frequency pull-in circuit 106 generates a clock pulse _CRR having the same repetition frequency as the original signal clock _CS . This is k and l
Input the logical sum C _WR ' into the frequency pull-in circuit 106,
The frequency of the oscillator may be controlled so that the number of pulses per unit time is counted and the count is equal to the number of counts of the read clock pulse _CRR . Clock correction circuit 107
The circuit operates in the same way as the pulse correction circuit 1 so that the write pulse C _WR and the read pulse C _RR do not occur at the same time. The auxiliary clock pulse C _RR ' supplied for this purpose is set to have a repetition period that is an integral multiple of the read clock pulse C _RR .

Regenerative repeater 101 and frequency pull-in circuit 10
6, it is clear that the conventional technology can be used as is, and the elastic memory 105
is the same as the elastic memory 2, and the pulse correction circuit 107 is the same as the pulse correction circuit 1, so only the decoding circuit 104 and its operation will be described in detail here.

An embodiment of the decoder is shown in FIG. Input terminal 1
The reproduced signal (Fig. 7e) applied to 20 has a delay time (T/2) of 1/2 of the pulse repetition period.
through the delay line 121 and the gate 122 with
Exclusive OR is performed at , and the waveform shown in FIG. 7f is generated. This waveform and its inverse are applied to shift registers 123 and 124, respectively, which are driven by word-synchronized clock pulses (Figure 7g, the generation of which will be explained later). Therefore, the waveform of the first stage of the shift register 123 is as shown in FIG. 7h. Since this waveform includes an empty signal as described above, it is necessary to remove this. For this purpose, the empty signal detection circuit 125 is used. This circuit uses six delay circuits 126 each having a delay time of T/2, and performs logical operations on their outputs and their outputs whose polarities are inverted by an inverter 127 using an AND gate 128 and an OR gate 129, as shown in FIG. 7a. The shaded area is detected and a detection pulse (FIG. 7j) is obtained. The reason for the extra delay circuit is to adjust the time of the detection pulse.

With this detection pulse, shift registers 123 to 12
By resetting 4, the empty signal portion can be removed as shown by diagonal lines in FIGS. 7(K) and (l). This waveform is a D-type flip-flop 132.
This is the output of The output being applied to the elastic memory 105 of the decoder 104 in FIG.
The output of the figure output terminal 134 is added. In order to read this into the elastic memory, output terminals 133 and 13 (not shown) are required.
4, that is, the logical product of the combination of waveforms k and l (FIG. 7) and the clock pulse C ₁ is used, C _WR '. This is read out by the output C _RR of the frequency pull-in circuit (Fig. 7i), and the waveform shown in Fig. 7n is restored.

Here, shift registers 123 to 124 and D
The word synchronization of the clock pulse 135 (FIG. 7g) driving the flip-flop 132 will now be described. This clock pulse is obtained by frequency-dividing the original clock pulse 130 by a trigger type flip-flop 132, but the phase of the division is determined by the falling edge of the empty signal detection pulse (FIG. 7f) 131. In Figure 7,
The divided clock (Figure 7g) is "off" at the falling edge of the empty signal detection pulse (Figure 7j), so it has a normal phase, no phase adjustment is performed, and word synchronization is not performed. You can see that it has been removed.

〔Effect of the invention〕

As described above, according to the present invention, a DC-balanced code can be generated in the process of synchronizing asynchronous signals, so that it can be sent as is to the transmission line. In other words, since synchronization and line coding can be achieved simultaneously, this is highly effective in practice for flexible and efficient synchronized transmission or synchronized multiplex transmission of asynchronous signals.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the principle of the present invention.
FIG. 2 is a configuration block diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the principle of the transmitting side.
4 to 6 are configuration diagrams of each block on the transmitting side of the embodiment of the present invention, FIG. 7 is a waveform diagram for explaining the principle of the receiving side of the embodiment of the present invention, and FIG. 8 is a diagram of the present invention. It is a block diagram of the receiving side decoding circuit in the Example. DESCRIPTION OF SYMBOLS 1,107...Pulse correction circuit, 2,105...Elastic memory, 3...Encoding circuit, 101...
Regenerative repeater, 104...decoding circuit, 106...frequency pull-in circuit.

Claims (1)

[Claims] 1. An asynchronous input signal pulse train having a data period independent of the transmission line clock is divided into three types of block codes "1", "0" and This is a pulse transmission line encoding method for transmitting signals in synchronization with the transmission line clock by encoding them into an empty signal "E", and each of the three types of block codes mentioned above inverts the level of all pulses in the block. In the pulse transmission line coding method, which has two types of modes and encodes by selecting one of the two types of modes so that a level change point always occurs at the boundary point between block codes, As one of the three types of block codes, a block code is generated in which the first and last levels within a single block are the same and DC unbalanced within the single block. A pulse transmission line coding method characterized by generating a block code composed of a combination of pulses whose first and last levels within a single block are different in high and low levels and which are DC-balanced within a single block. . 2 An asynchronous input signal pulse train with a data period independent of the transmission line clock is converted into three types of block codes "1", "0" and an empty signal "E" consisting of a combination of pulses with high and low levels. This is a pulse transmission line encoding method for transmitting signals in synchronization with the transmission line clock by encoding, and each of the three types of block codes has two types of modes in which the levels of all pulses in the clock are inverted. However, in the pulse transmission line coding method in which one of the two modes is selected and encoded so that a level change point always occurs at the boundary point between the block codes, the above three types of block codes are used. One type of block code is generated in which the first and last levels within a single block are the same and DC unbalanced within the single block. A block code is generated in which the last level is different from high to low, and furthermore, among the remaining two types of block codes, for a block code consisting of a combination of DC unbalanced pulses within a single block, the level of all pulses is In addition to the two inverted modes, there is also a pulse that has a DC component with the same absolute value and different polarity as each of the two modes, and whose initial and final levels within a single block are equal to each of the two modes. There are a total of 4 types of modes, 2 types of modes consisting of combinations, and the 4 types
A pulse transmission line encoding method characterized by selecting and encoding from among various modes.