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JPH0549124B2 - - Google Patents
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JPH0549124B2 - - Google Patents

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Publication number
JPH0549124B2
JPH0549124B2 JP62189101A JP18910187A JPH0549124B2 JP H0549124 B2 JPH0549124 B2 JP H0549124B2 JP 62189101 A JP62189101 A JP 62189101A JP 18910187 A JP18910187 A JP 18910187A JP H0549124 B2 JPH0549124 B2 JP H0549124B2
Authority
JP
Japan
Prior art keywords
transistor
power supply
circuit
channel mosfet
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62189101A
Other languages
Japanese (ja)
Other versions
JPS6432508A (en
Inventor
Hatsuhide Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18910187A priority Critical patent/JPS6432508A/en
Publication of JPS6432508A publication Critical patent/JPS6432508A/en
Publication of JPH0549124B2 publication Critical patent/JPH0549124B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は同相出力回路に関し、特に利得のある
同相出力回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a common mode output circuit, and more particularly to a common mode output circuit with gain.

〔従来の技術〕[Conventional technology]

従来、この種の回路は、第4図に示すようにN
チヤネルMOSFET11のゲートを入力としドレ
インを電源に接続しソースを負荷素子I11を介
して接地電位に接続し、さらにNチヤネル
MOSFET11のソースを出力とするソースフオ
ロワ回路が知られている。第3図の曲線Cにこの
回路の入出力特性を示すが、この回路は利得を有
していない事が判る。したがつて、この回路は入
力信号と出力信号との間のDCレベルを変えるレ
ベルシフタか、あるいはインピーダンス変換器と
してしか使えない。
Conventionally, this type of circuit has N
The gate of the channel MOSFET11 is input, the drain is connected to the power supply, the source is connected to the ground potential via the load element I11, and the N-channel
A source follower circuit in which the source of MOSFET 11 is used as an output is known. Curve C in FIG. 3 shows the input/output characteristics of this circuit, and it can be seen that this circuit has no gain. Therefore, this circuit can only be used as a level shifter that changes the DC level between input and output signals, or as an impedance converter.

一方、第5図に示すように反転増幅器A1およ
びA2をそれぞれ2段直列につなぐ方法もある。
この方法では、かなりの高利得が期待できるが、
信号の位相遅れも2倍になるため、位相補償回路
を必要とする。ところが、この方法は2段目の周
波数帯域を狭くすることを意味するため、増幅器
全体の周波数帯域も狭くなつてしまう。
On the other hand, there is also a method of connecting two stages of inverting amplifiers A1 and A2 in series, as shown in FIG.
This method can be expected to yield quite high profits, but
Since the phase delay of the signal also doubles, a phase compensation circuit is required. However, since this method means narrowing the frequency band of the second stage, the frequency band of the entire amplifier also becomes narrow.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来技術のソースフオロワ回路では同
相出力は得られても利得は1以下となる。また反
転増幅器を2段直列にした回路は、十分に利得が
あるものの周波数帯域が狭くなり高周波信号は扱
えないという欠点があつた。
In the conventional source follower circuit described above, even if an in-phase output is obtained, the gain is less than 1. Further, a circuit in which two stages of inverting amplifiers are connected in series has a drawback that, although it has sufficient gain, the frequency band is narrow and it cannot handle high frequency signals.

したがつて、本発明の目的は、十分に利得があ
り周波数帯域の広い同相出力回路を提供すること
にある。
Therefore, an object of the present invention is to provide an in-phase output circuit with sufficient gain and a wide frequency band.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の同相出力回路は、入力信号の供給を受
ける入力端子と、第1の電源電位を供給する第1
の電源端子と、第2の電源電位を供給する第2の
電源端子と、ゲート電極に前記入力端子を接続し
ドレイン電極に前記第1の電源端子を接続する一
導電型の第1のトランジスタと、ソース電極に前
記第1のトランジスタのソース電極を接続しゲー
ト電極に制御電圧を受ける前記第1のトランジス
タとは逆導電型の第2のトランジスタと、一端に
前記第2のトランジスタのドレイン電極を接続し
他端に前記第2の電源端子を接続する負荷素子
と、前記第2のトランジスタのドレイン電極と前
記負荷素子との接続点に接続し出力信号の供給を
受ける出力端子とを備えている。
The in-phase output circuit of the present invention has an input terminal that receives an input signal, and a first terminal that supplies a first power supply potential.
a second power supply terminal for supplying a second power supply potential; a first transistor of one conductivity type having a gate electrode connected to the input terminal and a drain electrode connected to the first power supply terminal; , a second transistor having a conductivity type opposite to that of the first transistor, the source electrode of which is connected to the source electrode of the first transistor and whose gate electrode receives a control voltage; and a drain electrode of the second transistor connected to one end thereof. and an output terminal connected to a connection point between the drain electrode of the second transistor and the load element to receive an output signal. .

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

本発明の第1の実施例の同相出力回路の回路図
を示す第1図を参照すると、この同相出力回路は
ゲートを入力に接続しドレインを電源に接続する
NチヤネルMOSFET1と、ソースをNチヤネル
MOSFET1のソースに接続しゲートを電圧源VB
に接続するPチヤネルMOSFET2と、一端をP
チヤネルMOSFET2のドレインに接続し他端を
接地電位に接続する負荷素子I1とを有する構成
である。また、この同相出力回路はPチヤネル
MOSFET2のドレインと負荷素子I1との接続
点から出力する構成である。
Referring to FIG. 1 showing a circuit diagram of a common mode output circuit according to a first embodiment of the present invention, this common mode output circuit includes an N-channel MOSFET 1 whose gate is connected to the input and whose drain is connected to the power supply, and whose source is connected to the N-channel MOSFET 1.
Connect the source of MOSFET1 and the gate to the voltage source V B
P-channel MOSFET2 connected to
This configuration includes a load element I1 connected to the drain of the channel MOSFET 2 and the other end connected to the ground potential. Also, this common mode output circuit is a P channel.
The configuration is such that the output is output from the connection point between the drain of MOSFET 2 and the load element I1.

次に、本発明の第1の実施例の同相出力回路の
特性を示す第3図の曲線Aを参照してこの同相出
力回路の動作を説明する。
Next, the operation of the common mode output circuit according to the first embodiment of the present invention will be explained with reference to curve A in FIG. 3 showing the characteristics of the common mode output circuit according to the first embodiment of the present invention.

まず、入力がLowレベル(以下“0”と略記
する)の時はNチヤネルMOSFET1がオフ状態
となつており、出力も“0”となる。入力信号が
“0”から上昇してNチヤネルMOSFET1をオ
ン状態にする時はNチヤネルMOSFET1のソー
ス電位およびPチヤネルMOSFET2のソース電
位VAも“0”から上昇する。しかし、Pチヤネ
ルMOSFET2は基板効果があり、容易にオン状
態にならない。しかもNチヤネルMOSFET1の
方もソース電位が上昇する分基板効果がかかるの
で十分にオン状態になることができソース電位
VAだけが入力信号の上昇と共に上昇する。
First, when the input is at a low level (hereinafter abbreviated as "0"), the N-channel MOSFET 1 is in an off state, and the output is also "0". When the input signal rises from "0" to turn on the N-channel MOSFET 1, the source potential of the N-channel MOSFET 1 and the source potential V A of the P-channel MOSFET 2 also rise from "0". However, the P-channel MOSFET 2 has a substrate effect and does not easily turn on. Moreover, N-channel MOSFET 1 is also affected by the substrate effect as the source potential increases, so it can be turned on sufficiently and the source potential
Only V A increases with increasing input signal.

この時、出力はPチヤネルMOSFET2がオン
状態ではないため、“0”を出力し続ける。さら
に、入力信号が上昇し続け、ついにPチヤネル
MOSFET2をオン状態にさせると、これらのN
チヤネルMOSFET1およびPチヤネル
MOSFET2は負荷素子I1よりDCインピーダン
スが低くなるように設計されていれば、出力は急
速に上昇する。この部分に入力信号をバイアスし
て使用すれば、利得が得られる。
At this time, since the P-channel MOSFET 2 is not in the on state, the output continues to be "0". Furthermore, the input signal continues to rise, and finally the P channel
When MOSFET2 is turned on, these N
Channel MOSFET1 and P channel
If MOSFET2 is designed to have a lower DC impedance than load element I1, the output will rise rapidly. Gain can be obtained by biasing an input signal to this portion.

次に、さらに入力信号がHighレベル(以下
“1”と略記する)側に寄ると、Nチヤネル
MOSFET1およびPチヤネルMOSFET2とも
十分にオン状態となり、この同相出力回路は負荷
素子I1に比べ十分低いDCインピーダンスを持
つようになるので従来技術のソースフオロワ回路
と同一の特性を有する。ここで、Pチヤネル
MOSFET2のゲートをバイアスしている電圧VB
を変えるか、またはPチヤネルMOSFET2の閾
値電圧を変えることにより、この回路の動作点、
つまり出力が“0”から上昇する点を変えること
ができる。
Next, when the input signal approaches the High level (hereinafter abbreviated as "1") side, the N channel
Both MOSFET 1 and P-channel MOSFET 2 are fully turned on, and this in-phase output circuit has DC impedance sufficiently lower than that of load element I1, so that it has the same characteristics as the source follower circuit of the prior art. Here, P channel
Voltage V B biasing the gate of MOSFET2
The operating point of this circuit can be adjusted by changing the threshold voltage of P-channel MOSFET2,
In other words, the point at which the output rises from "0" can be changed.

また、反転増幅回路は入出力間に付加されるミ
ラー容量が周波数帯域の上限を決めるのに対し、
同相回路では逆に減少を補償するように働く。し
たがつて、ソースフオロワ回路およびゲート接地
回路の組合せの回路構成である本発明の同相出力
回路は高周波領域で良好な特性を示す。
In addition, in an inverting amplifier circuit, the Miller capacitance added between the input and output determines the upper limit of the frequency band.
The common mode circuit works to compensate for the decrease. Therefore, the in-phase output circuit of the present invention, which has a circuit configuration of a combination of a source follower circuit and a common gate circuit, exhibits good characteristics in a high frequency region.

次に、本発明の第2の実施例の同相出力回路を
説明する。
Next, a common mode output circuit according to a second embodiment of the present invention will be explained.

第2の実施例の同相出力回路の回路図を示す第
2図を参照すると、この第2の実施例の同相出力
回路はゲートを入力に接続しドレインを電源に接
続するNチヤネルMOSFET21と、ソースをN
チヤネルMOSFET21のソースに接続するPチ
ヤネルMOSFET22と、一端をPチヤネル
MOSFET22のドレインに接続し他端を接地電
位に接続する負荷素子I21と、Nチヤネル
MOSFET21およびPチヤネルMOSFET22
のそれぞれのソースの接続点の電位VSを入力し
その出力をPチヤネルMOSFET22のゲートに
接続する反転増幅器A3とを有する構成である。
さらに、PチヤネルMOSFET22のドレインと
負荷素子I21との接続点から出力する構成であ
る。
Referring to FIG. 2, which shows a circuit diagram of the common-mode output circuit of the second embodiment, the common-mode output circuit of the second embodiment includes an N-channel MOSFET 21 whose gate is connected to the input and whose drain is connected to the power supply; N
P-channel MOSFET 22 connected to the source of channel MOSFET 21, and one end connected to the P-channel MOSFET 21.
A load element I21 connected to the drain of MOSFET22 and the other end connected to ground potential, and an N-channel
MOSFET21 and P-channel MOSFET22
The configuration includes an inverting amplifier A3 that inputs the potential V S at the connection point of each source of and connects its output to the gate of the P-channel MOSFET 22.
Furthermore, it is configured to output from the connection point between the drain of the P-channel MOSFET 22 and the load element I21.

すなわち、第1の実施例ではソースフオロ回路
のNチヤネルMOSFET1と負荷素子I1との間
に接続されるPチヤネルMOSFET2のゲートを
定電圧VBでバイアスしていたが、この第2の実
施例の同相出力回路ではNチヤネルMOSFET2
1およびPチヤネルMOSFET22のそれぞれの
ソースの接続点の電位VSを反転増幅器A3に入
力し、反転増幅器A3の出力をPチヤネル
MOSFET22のゲートに加えている。
That is, in the first embodiment, the gate of the P-channel MOSFET 2 connected between the N-channel MOSFET 1 and the load element I1 of the source filter circuit was biased with a constant voltage V B , but in the second embodiment, the in-phase In the output circuit, N-channel MOSFET2
The potential V S at the connection point of the respective sources of MOSFET 1 and P channel MOSFET 22 is input to the inverting amplifier A3, and the output of the inverting amplifier A3 is input to the P channel MOSFET.
It is added to the gate of MOSFET22.

次に、本発明の第2の実施例の同相出力回路の
特性を示す第3図の曲線Bを参照して、この同相
出力回路の動作を説明する。
Next, the operation of the common mode output circuit according to the second embodiment of the present invention will be explained with reference to curve B in FIG. 3 showing the characteristics of the common mode output circuit according to the second embodiment of the present invention.

入力に高い電圧が加わりNチヤネルMOSFET
21およびPチヤネルMOSFET22のそれぞれ
のソースの接続点の電位VSが反転増幅器A3の
閾値電圧より高い時は、PチヤネルMOSFET2
2のゲートは“0”でPチヤネルMOSFET22
は十分にオンし、接続点の電位VSを“0”側へ
引き落とそうとする。
When high voltage is applied to the input, N-channel MOSFET
When the potential V S at the connection point of the sources of each of P-channel MOSFET 21 and P-channel MOSFET 22 is higher than the threshold voltage of inverting amplifier A3, P-channel MOSFET 2
The gate of 2 is “0” and P channel MOSFET 22
turns on sufficiently and attempts to pull down the potential V S at the connection point to the "0" side.

一方、入力電圧が低くなり接続点の電位VS
反転増幅器A3の閾値電圧より低くなると、反転
増幅器A3の出力は“1”の方へ変化しPチヤネ
ルMOSFET22をオフ状態にさせるように働
く。
On the other hand, when the input voltage becomes low and the potential V S at the connection point becomes lower than the threshold voltage of the inverting amplifier A3, the output of the inverting amplifier A3 changes to "1" and acts to turn off the P-channel MOSFET 22.

この様にして、接続点の電位VSがある程度以
下にならないように制御されており、この結果、
NチヤネルMOSFET21の基板効果電圧が高い
値に保たれ、第3図の曲線Bに示すように変化点
が高い方にシフトする。入力電圧が高い電圧の時
は、NチヤネルMOSFET21およびPチヤネル
MOSFET22は十分にオン状態となり、通常の
ソースフオロワ回路と同じレベルになる。
In this way, the potential V S at the connection point is controlled so that it does not fall below a certain level, and as a result,
The substrate effect voltage of the N-channel MOSFET 21 is maintained at a high value, and the change point shifts to a higher value as shown by curve B in FIG. When the input voltage is high, N-channel MOSFET21 and P-channel
The MOSFET 22 is fully turned on and has the same level as a normal source follower circuit.

したがつて、より高利得を有する同相出力回路
が実現できる。
Therefore, a common mode output circuit with higher gain can be realized.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、従来技術のソー
スフオロワ回路の駆動用トランジスタと出力との
間に駆動用トランジスタとは逆導電型のトランジ
スタを備えることにより、同一位相で利得を有す
る回路を実現できる。
As described above, the present invention can realize a circuit having gain in the same phase by providing a transistor of a conductivity type opposite to that of the driving transistor between the driving transistor and the output of the conventional source follower circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の第1および第2
の実施例の同相出力回路の回路図、第3図は同相
出力回路の入出力特性図、第4図および第5図は
従来技術の同相出力回路の回路図である。 1,11,21……NチヤネルMOSFET、
2,22……PチヤネルMOSFET、I1,I1
1……負荷素子、A1,A2,A2……反転増幅
器、VB……電圧源、VA,VS……ソース接続点の
電位、VDD……電源電位。
FIG. 1 and FIG. 2 show the first and second embodiments of the present invention.
FIG. 3 is an input/output characteristic diagram of the common-mode output circuit, and FIGS. 4 and 5 are circuit diagrams of the common-mode output circuit of the prior art. 1, 11, 21...N channel MOSFET,
2, 22...P channel MOSFET, I1, I1
1... Load element, A1, A2, A2... Inverting amplifier, V B ... Voltage source, V A , V S ... Potential at source connection point, V DD ... Power supply potential.

Claims (1)

【特許請求の範囲】[Claims] 1 入力信号の供給を受ける入力端子と、第1の
電源電位を供給する第1の電源端子と、第2の電
源電位を供給する第2の電源端子と、ゲート電極
に前記入力端子を接続しドレイン電極に前記第1
の電源端子を接続する一導電型の第1のトランジ
スタと、ソース電極に前記第1のトランジスタの
ソース電極を接続しゲート電極に制御電圧を受け
る前記第1のトランジスタとは逆導電型の第2の
トランジスタと、一端に前記第2のトランジスタ
のドレイン電極を接続し他端に前記第2の電源端
子を接続する負荷素子と、前記第2のトランジス
タのドレイン電極と前記負荷素子との接続点に接
続し出力信号の供給を受ける出力端子とを備える
ことを特徴とする同相出力回路。
1. Connecting the input terminal to an input terminal receiving an input signal, a first power supply terminal supplying a first power supply potential, a second power supply terminal supplying a second power supply potential, and a gate electrode. The drain electrode has the first
a first transistor of one conductivity type to which the power supply terminal of the first transistor is connected, and a second transistor of a conductivity type opposite to that of the first transistor whose source electrode is connected to the source electrode of the first transistor and whose gate electrode receives a control voltage. a load element having one end connected to the drain electrode of the second transistor and the other end connected to the second power supply terminal, and a connection point between the drain electrode of the second transistor and the load element; An in-phase output circuit characterized by comprising an output terminal to which the output terminal is connected and receives an output signal.
JP18910187A 1987-07-28 1987-07-28 In-phase output circuit Granted JPS6432508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18910187A JPS6432508A (en) 1987-07-28 1987-07-28 In-phase output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18910187A JPS6432508A (en) 1987-07-28 1987-07-28 In-phase output circuit

Publications (2)

Publication Number Publication Date
JPS6432508A JPS6432508A (en) 1989-02-02
JPH0549124B2 true JPH0549124B2 (en) 1993-07-23

Family

ID=16235371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18910187A Granted JPS6432508A (en) 1987-07-28 1987-07-28 In-phase output circuit

Country Status (1)

Country Link
JP (1) JPS6432508A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753111A (en) * 1980-09-16 1982-03-30 Nippon Telegr & Teleph Corp <Ntt> Amplifying circuit

Also Published As

Publication number Publication date
JPS6432508A (en) 1989-02-02

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