JPH0550866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a conductivity modulation type semiconductor device that integrates a reverse conduction diode.

[Technical background of the invention and its problems]

In recent years, power
Although MOSFETs have appeared on the market, devices with sufficiently low on-resistance and blocking voltages of 1000V or higher have not yet been realized. The reason for this is that the higher the blocking voltage V _B becomes, the more the on-resistance R _ON of the element increases. Recently, conductivity modulation type MOSFETs have been attracting attention as a way to improve this point. Its basic configuration is shown in FIG. This structure is a power source commonly referred to as vertical DMOS, as shown in Figure 8.
The n ⁺ layer 11a, which will become the drain region of the MOSFET, is ^p
It can be said that the layer 11 is replaced. That is, there is a high-resistance n ^- layer 12 on the p ⁺ layer 11, a p ⁺ layer 13 is selectively formed on the surface of this n ^- layer 12, and an n ⁺ layer is selectively formed on the surface of this p ⁺ layer 13. A layer 14 is formed, and a surface region of the p ⁺ layer 13 sandwiched between the n ^- layer 12 and the n ⁺ layer 14 is used as a channel region 20, and a gate electrode 16 is formed thereon via a gate insulating film. Reference numeral 17 indicates a source electrode disposed to extend over the p ⁺ layer 17 to the n ⁺ layer 14, and 18 indicates a drain electrode.

The operation of this element is as follows. When the source electrode 17 is grounded and a positive voltage is applied to the gate electrode 16 and drain electrode 18, the channel region 20 on the surface of the p ⁺ layer 13 directly under the gate electrode 16 is reversed, and an electron channel is formed, based on the same principle as a vertical DMOS. I turn it on because I can. What is different from the vertical DMOS is that holes are injected into the n ^- layer 12 from the p ⁺ layer 11 on the drain side as well. The holes injected in this way accumulate in the n ^- layer 12 and make this region of the n ^- layer 12 low in resistance due to the conductivity modulation effect. Therefore, a sufficiently lower on-resistance can be obtained compared to the case of DMOS.

However, although this conductivity modulation type MOSFET has a lower on-resistance, it has the disadvantage that the turn-off time is longer than that of a DMOS. this is,
This is because a large number of carriers are accumulated in the n ^- layer 12 compared to DMOS, and it takes time for them to disappear.

Conventional conduction modulation MOSFETs also have the following drawbacks. That is, this type of power switching element is used as a main switch of a power conversion device such as an inverter, and generally has reverse conducting diodes (RCDs) connected in parallel. 8th in vertical DMOS
As is clear from the figure, the drain region is n ⁺ layer 1
1a, n ⁺ layer 11a, n ^- layer 12, p ⁺
Diode B constituted by layer 13 is
It is built in antiparallel to the MOSFET body A. Therefore, there is no need to connect an external reverse conduction diode. On the other hand, conductive modulation type
As is clear from Figure 7, MOSFETs do not have a built-in reverse conduction diode and must be connected externally.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and
The objective is to provide a conduction modulation type MOSFET with a built-in reverse conduction diode and excellent turn-off characteristics.

[Summary of the invention]

The conductivity modulation type MOSFET according to the present invention includes a first conductivity type drain layer, a second conductivity type first drain layer in contact with the first conductivity type drain layer, and
a base layer, a second base layer of the first conductivity type selectively formed on the surface of the first base layer, and a source layer of the second conductivity type selectively formed on the surface of the second base layer; The present invention is characterized in that a reverse conduction diode is integrally formed with a second conduction type layer that is in ohmic contact with the drain electrode in place of the drain layer located below a portion of the source electrode.

〔Effect of the invention〕

According to the present invention, by replacing a part of the drain layer in contact with the drain electrode with a layer of the opposite conductivity type, it is possible to obtain a conduction modulation type MOSFET with a built-in reverse conduction diode. In particular, if this reverse conduction diode is formed at the position where the external connection conductor of the source electrode is attached, the chip can be used effectively without particularly increasing the chip area.

[Embodiments of the invention]

Examples of the present invention will be described below. FIG. 1 shows the element structure of one embodiment. Portions corresponding to those in the conventional FIG. 6 are given the same reference numerals. This will be explained according to the manufacturing process.

The high-resistance n ^- layer 12 (first base layer) is the starting substrate, and in order to have an impurity concentration that can achieve a predetermined breakdown voltage, a layer of 6×10 ¹⁷ /cm ³ , 15 μm thick is formed on one side of the n ^- -Si substrate.
The front and rear n ⁺ layers 19 (buffer layers) are formed by vapor phase growth. Then at a depth of 5-8 μm p ⁺ layer 11
(drain layer) and p ⁺ layer 13 (second base layer) are formed by selective diffusion. Furthermore, an n ⁺ layer 19 that will become a source is formed in the p + layer 13 by a selective diffusion method, and an ^{n + layer} 19 that will become a cathode of a reverse conduction diode is formed in a region of the n ⁺ layer 19 where the p ⁺ layer 11 is not formed.
form a.

In this embodiment, the p ⁺ layers 11 and 13 have a surface concentration of about 4×10 ¹⁷ /cm ³ , and the n ⁺ layers 14 and 19
a is set so that the surface concentration is approximately 3×10 ²⁰ /cm ³ .

Following the above manufacturing process, the gate insulating film 15 is formed by high temperature thermal oxidation, and the n ⁺ layer 14 and the p ⁺ layer 13 are formed.
A hole is made in the gate insulating film 15 to form an ohmic electrode, and aluminum is deposited to a thickness of several μm and selectively etched to form a gate electrode 16 and a source electrode 17. A drain electrode 18 is formed by depositing a V-Ni-Au film on the back surface of the wafer.

In FIG. 1, A' is a conduction modulation type MOSFET main body region, and B' is a reverse conduction diode region. The n ⁺ layer 19 between the p ⁺ layer 11 and the n ^- layer 12 in the main body region A' is
This is to optimize the amount of carriers injected into the n ^- layer 12, and the total amount of impurities is 5×
10 ¹³ /cm ² or higher. Here, the total amount of impurities is defined as the value obtained by integrating the impurity concentration distribution in the thickness direction by the thickness of the n ⁺ layer 19, where N(x) is the impurity concentration distribution.

FIG. 2 shows the results of theoretically determining the proportion of electron current in the on-state liquid when the total amount of impurities in the n ⁺ layer 19 is varied in the device shown in FIG.
From this result, the total amount of impurities in the n ⁺ layer 19 is 5×
The proportion occupied by the electron current begins to increase when it exceeds 10 ¹³ /cm ² . Therefore, by setting the total amount of impurities in the n ⁺ layer 19 to 5×10 ¹³ /cm ² or more, the amount of holes injected from the p ⁺ layer 11 to the n ^- layer 12 can be suppressed, and the device The turn-off time can be shortened.

Even in the conventional conductivity modulation type MOSFET, the p ⁺ layer 11 and
Between the n ^- layers 12, a layer of 2×10 ¹⁶ /cm ³ and a thickness of about 15 μm is formed.
Techniques for increasing the punch-through voltage of the n ^- layer 12 by providing an n ⁺ layer are known. But in this case n ⁺
The total amount of impurities in the layer is about 3×10 ¹³ /cm ² , and as is clear from FIG. 2, the ratio of electron current hardly changes. That is, as in this embodiment, the effect of shortening the turn-off time can only be obtained by providing the n ⁺ layer 19 with a total impurity content of 5×10 ¹³ or more. Moreover, the total amount of impurities in the n ⁺ layer 19 is
If it is kept below about 10 ¹⁵ /cm ² , hole current also exists whenever electron current increases, and the on-resistance of the device can be made sufficiently lower than that of vertical DMOS.

Further, in this embodiment, as is clear from FIG. 1, the reverse conduction diode region B' is composed of the p ⁺ layer 13, the n ^- layer 12, the n ⁺ layer 19, and the n ⁺ layer 19a.
It has a so-called pin diode structure, and the recovery time here is short.

Note that it is effective to control the carrier lifetimes τ _A and τ _B of the MOSFET main body region A' and the diode region B' by electron beam irradiation, neutron beam, γ ray irradiation, etc. as necessary. By diffusing heavy metals such as Au and Pt, τ _A ,
τ _B may also be controlled. Furthermore, the values of τ _A and τ _B do not need to be the same. For example, if it is particularly desired to shorten the recovery time of the diode, it may be selectively controlled so that τ _A >τ _B.

FIG. 3 shows another embodiment of the invention. In this embodiment, a bonding wire 17 is used to take out the source electrode 17 to the outside of the package.
A reverse conduction diode is formed at the bonding pad portion 17b that connects the bonding pad 17b. In this way, it is possible to prevent the chip area from increasing due to the built-in reverse conduction diode.

FIG. 4 shows still another embodiment in which a reverse conduction diode is formed at the position of a bump electrode 17s for connecting the source electrode 17 to an external terminal. The bump electrode 17s is obtained by covering a region of the substrate surface other than the electrode formation region with an organic insulating film 21, performing solder plating, and raising it into a hemispherical shape due to the surface tension at that time. A large number of such bump electrodes are formed within the chip and are crimped to external terminals to allow a large current to flow. In this embodiment, as in the previous embodiment, a reverse conduction diode can be incorporated without increasing the chip area.

FIG. 5 shows yet another embodiment. In this embodiment, the reverse conducting diode is a Schottky diode. That is, a part of the p ⁺ layer 13 is replaced with a high-resistance p ^- layer 13k, and a part of the source electrode 17 is replaced with a short key electrode 17 made of platinum or the like in this region.
k. By selecting the material of the shot key electrode 17k, a so-called bipolar mode shot key diode utilizing injection of minority carriers may be formed.

FIG. 6 shows yet another embodiment. In this embodiment, the reverse conduction diode is made into a shot key diode using the shot key electrode 17F, and
The p ^- layer 13K is divided into a plurality of parts to reduce the voltage drop at the diode portion and improve the switching speed. Further, the gate electrode 16 is made of polycrystalline silicon, covered with a silicon oxide film, and separated from the source electrode 17G. On the drain side, n ⁺
The layer is divided into a part 19C with a large amount of impurities and a part 1 with a small amount of impurities.
It is made in 9D parts, and the part with the highest total amount of impurities is 19C.
This suppresses the injection of minority carriers and improves switching speed. The source metal 17J is continuously provided on the source electrode 17G to improve adhesion to the solder layer 17M. In this embodiment, the position of 19C may be under the gate electrode.

The present invention can be modified in various other ways. For example, in Figure 1, the diode region
It is effective to set the distance C between B' and the closest channel region 20 to be larger than the effective carrier diffusion length L of the n ^- layer 12. As a result, the p ⁺ layer 1 is
1, n ⁺ layer 19, n ^- layer 12, p ⁺ layer 13, n ⁺ layer 14
It is possible to prevent a malfunction in which a parasitic thyristor consisting of a thyristor is turned on.

Further, in the above embodiment, the first conductivity type is p type,
Although we have explained an example using n-type as the second conductivity type,
The present invention is also effective when these conductivity types are reversed.

[Brief explanation of drawings]

Figure 1 shows a conduction modulation type of one embodiment of the present invention.
A diagram showing the MOSFET structure, Figure 2 is the n ⁺ layer 19
Figures 3 to 6 are diagrams showing the conduction modulation type MOSFET structure of other ^embodiments , and Figure 7 is the conventional conduction modulation type MOSFET structure. FIG. 8 is a diagram showing a vertical type MOSFET. 11... p ⁺ layer (drain layer), 19... n ⁺ layer (buffer layer), 12... n ^- layer (first base layer),
13... p ⁺ layer (second base layer), 14... n ⁺ layer (source layer), 19a... n ⁺ layer, 15... gate insulating film, 16... gate electrode, 17... source electrode, 18...Drain electrode, 20...Channel region, A'...Conductivity modulation type MOSFET main body region, B'...
...reverse conduction diode region.

Claims (1)

[Claims] 1. A drain layer of a first conductivity type, a first base layer of a second conductivity type in contact with the drain layer, and a first base layer of a second conductivity type that is in contact with the drain layer.
a second base layer of the first conductivity type selectively formed on the surface of the base layer; a source layer of the first conductivity type selectively formed on the surface of the second base layer; a gate electrode formed on the surface of the second base layer in the region sandwiched between the first base layers as a channel region via a gate insulating film; and a drain electrode in contact with the drain layer;
a source electrode that contacts the source layer and the second base layer at the same time; and a part of the drain layer that is in ohmic contact with the drain electrode instead of the drain layer so that a diode is formed between the source electrode and the drain electrode. A semiconductor device comprising: a reverse conduction diode configured by providing a second conductivity type layer. 2. The first base layer includes a highly-concentrated buffer layer provided on the drain layer side and a high-resistance base layer provided on the second base layer side, and the total amount of impurities in the buffer layer is 5×. 10 ¹³ / ^cm2
A semiconductor device according to claim 1, which is the above. 3. The semiconductor device according to claim 2, wherein the total amount of impurities in the buffer layer is 10 ¹⁵ /cm ² or less. 4. The semiconductor device according to claim 1, wherein the reverse conduction diode is provided at a position where a connection conductor to the outside of the source electrode is provided. 5. The semiconductor device according to claim 4, wherein the connecting conductor is a bonding wire or a bump electrode. 6. The semiconductor device according to claim 1, wherein the reverse conduction diode is a Schottky diode in which the source electrode and the second base layer are in Schottky contact at that position. 7. The semiconductor device according to claim 1, wherein the second conductivity type layer is located below a region where a source electrode is formed.