JPH0551206B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a gain control circuit whose gain is controlled by a gain control bias, and which eliminates fluctuations in output bias due to the gain control bias. Related to gain control circuits.

(Prior Art) Conventionally, gain control circuits in which the gain is controlled by a gain control bias have been used in electronic devices (TVs, VTRs, communication devices, etc.), such as AGC (Automatic Gain Control) circuits. .

FIGS. 7 and 8 are circuit diagrams showing the configuration of a conventional gain control circuit whose gain is controlled by a gain control bias Vco.

In the gain control circuit shown in FIG. 7, the base is connected to the input terminal Vin1, and the collector is connected to the output terminal out1.
an NPN type bipolar transistor Q1,
It has a differential amplifier pair composed of an NPN bipolar transistor Q2 whose base is connected to the input terminal Vin2 and whose collector is the output terminal out2.

Transistors Q1, which constitute this differential amplifier pair,
Between the emitters of transistors Q2, NPN bipolar transistors Q3 and Q4, each of which has a gain control bias Vco applied to its base and whose collectors are connected, connect the respective emitters of transistors Q1 and Q3. Q2,Q
4 by connecting their respective emitters. Furthermore, resistors R1 and R2 are connected between the collectors of transistors Q1 and Q2 and the voltage source Vcc.
is inserted, and an emitter resistor R3, is inserted between the emitters of transistors Q1 and Q2 and ground GND.
R4 is inserted.

In such a configuration, the transistor Q
3, Q4 is operated in the saturation region without supplying current to its collector, and the saturation resistance of transistors Q3 and Q4 is changed by gain control bias Vco, so that transistors Q3 and Q4 act as variable impedance elements. Therefore, the gain of this gain control circuit is controlled by changing the current flowing through the load resistors R1 and R2 by changing the impedance between the emitters of the transistors Q1 and Q2 that constitute the differential amplifier pair. There is.

The gain control circuit shown in FIG.
PNP type bipolar transistors Q5 and Q6, each of which has a gain control bias Vco applied to its base and whose collectors are connected, are connected to the emitters of transistors Q1 and Q5, and the emitters of transistors Q2 and Q6 are connected to each other. It is inserted by connecting, and the other configuration is the same as that in FIG. 7. Even in such a configuration, the gain of the gain control circuit is controlled in the same manner as in FIG. 7.

(Problems to be Solved by the Invention) As explained above, in the gain control circuit shown in FIGS. 7 and 8, the The saturation resistance of a bipolar transistor is used as the variable impedance element.

This bipolar transistor Q3, Q4 and Q
5.Q6 operates in the saturation region, so when these transistors are integrated, it becomes a PNP
A type of parasitic transistor will be formed for each transistor Q3, Q4, Q5, Q6. For example, the transistor Q5 shown in FIG.
In this case, a PNP type parasitic transistor is formed by using the collector as a P type substrate, and using the base and emitter as the base and emitter of transistor Q5.

In this way, when a parasitic transistor is formed in a variable impedance element, a current flows into the substrate via this parasitic transistor. For example, a portion of the current flowing from the emitter of the transistor Q1 to the transistor Q5 flows into the substrate via the parasitic transistor.

In addition, bipolar transistors Q3, Q4, Q
5, Q6 has a finite value of hfe (current amplification factor), so a base current flows through it. Furthermore, since no current is supplied to the collectors of each of the transistors Q3, Q4, Q5, and Q6, for example, when a gain control bias Vco is applied to the base of the transistor Q3, the collector potential becomes lower than the base potential. The base current is multiplied by hfe through the collector and flows into the emitter.

In this way, by forming parasitic transistors in the bipolar transistors Q3, Q4, Q5, and Q6, which serve as variable impedance elements,
There was a problem in that the base current flowing through Q4, Q5, and Q6 changed the current flowing through the load resistors R1 and R2, causing the output bias to fluctuate.

Therefore, the present invention has been made in view of the above, and its purpose is to provide a gain control circuit that stabilizes the output bias and has good consistency with the next stage. It is in.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides first and second transistors forming a differential amplification pair; and a load means serving as a load for the second transistor, the gate terminal of which is connected to a gain control bias, and the load means connected between the emitter terminals or between the source terminals of the first and second transistors.
a FET (field effect transistor), a first current setting means connected between the emitter terminal or source terminal of the first transistor and the power supply to set the emitter current or source current of the first transistor; and a second current setting means connected between the emitter terminal or source terminal of the second transistor and the power supply to set the emitter current or source current of the second transistor.

(Function) In the above configuration, the present invention inserts an FET between the emitter terminal or source terminal of the first transistor and the emitter terminal or source terminal of the second transistor, and provides a gate terminal of the FET. By changing the gain control bias, the impedance of the FET is varied and the gain of the circuit is controlled.

(Example) Hereinafter, an example of the present invention will be described using the drawings.

1 to 6 are circuit diagrams showing the configurations of gain control circuits corresponding to first to sixth embodiments of the present invention, respectively. Like the gain control circuits shown in FIGS. 7 and 8, the gain control circuit of each embodiment has a differential amplification pair composed of bipolar transistors, and a MOS transistor is used as the variable impedance element. It is. Note that in Figures 1 to 6, Figures 7 and 8
Components with the same reference numerals as those in the figure have the same functions, and their explanation will be omitted.

In the first embodiment shown in FIG. 1, an N-channel MOS transistor (hereinafter referred to as "NMOS")
) N1 and N2 are variable impedance elements. NMOSN1 has its gate supplied with gain control bias Vco, and its drain connected to the emitter of transistor Q1.
NMOSN2 has a gain control bias on its gate.
Vco is applied, the drain is connected to the emitter of transistor Q2, and the source is connected to the source of NMOSN1. In this way, NMOSN
By connecting 1 and N2, NMOSN1,
A N2 variable impedance element is inserted between the emitters of transistors Q1 and Q2.

In such a configuration, NMOSN1, N
By changing the gain control bias applied to the gates of NMOSN1 and N2, the ON resistance when NMOSN1 and N2 are in the conductive state is changed.
is operated as a variable impedance element. Therefore, the gain of this gain control circuit is determined by the gain control bias Vco of NMOSN1 and N2.
By changing the ON resistance, the load resistance R1,
It is controlled by changing the current flowing through R2.

As explained above, since NMOSN1 and N2 are used as variable impedance elements,
When a circuit is integrated, it is possible to prevent a parasitic transistor from being formed in a variable impedance element. Furthermore, in the case of a MOS transistor, the current flowing between the source and drain is controlled by applying a voltage to the gate, and almost no current flows from the gate to the source or drain.

Therefore, even if gain control bias Vco is applied to the gates of NMOSN1 and N2, NMOSN1 and
The current flowing from the drain of N2 to the substrate and the current flowing from the gate to the emitter resistors R3 and R4 are eliminated, making it possible to prevent fluctuations in the output bias due to the gain control bias Vco.

Also, only when a potential difference occurs between the differential input signals applied to input terminal Vin1 and input terminal Vin2,
NMOSN1, in which the generated potential difference is connected in series,
Since it is applied to both ends of NMOSN2, when the differential input signals are at the same potential, no current flows through NMOSN1 and N2.

Furthermore, even if the gain of the circuit is extremely small, that is, even if the impedance of NMOSN1 and N2 is large, the transistor Q
Since the emitter currents of Q1 and Q2 are independently set by emitter resistors R3 and R4, stable and reliable operation is guaranteed. Therefore,
It becomes possible to secure a wide dynamic range.

FIG. 2 is a circuit diagram showing the configuration of a gain control circuit according to a second embodiment of the invention. The feature of this second embodiment is that P-type MOS transistors (hereinafter referred to as "PMOS") P1 and P2 are used as variable impedance elements, and even in this configuration, the first Effects similar to those of the embodiment can be obtained.

FIGS. 3 and 4 are circuit diagrams showing the configurations of gain control circuits according to third and fourth embodiments of the present invention. The feature of the third and fourth embodiments is that the variable impedance element is integrated into one MOS
In the third embodiment, the variable impedance element is NMOSN.
3, and in the fourth embodiment, the variable impedance element is PMOSP3. Even in such a configuration, the same effects as in the first embodiment can be obtained.

FIG. 5 is a circuit diagram showing the configuration of a gain control circuit according to a fifth embodiment of the present invention. The feature of this fifth embodiment is that the transistors Q1 and Q constituting the differential amplification pair are different from the first embodiment.
2 load is a PNP type bipolar transistor Q
7, Q8, and the emitter currents of transistors Q1 and Q2 are set by constant current sources I ₀ /2 instead of emitter resistors R3 and R4, respectively. Even in such a configuration, the same effects as in the first embodiment can be obtained.

FIG. 6 is a circuit diagram showing the configuration of a gain control circuit according to a sixth embodiment of the present invention. The feature of this sixth embodiment is that a differential amplification pair is formed by PNP type bipolar transistors Q9 and Q10, and the load of this differential amplification pair is NPN type bipolar transistors Q11 and Q12. The emitter currents of Q9 and Q10 are supplied independently by their respective constant current sources I ₀ /2, and the variable impedance elements are configured with PMOSP1 and P2. Even in such a configuration, the first
The same effects as in the embodiment can be obtained.

Note that the load of the transistors constituting the differential amplifier pair may be, for example, an inductance in addition to the resistors and active elements such as transistors shown in the above embodiments. Furthermore, it goes without saying that the transistors constituting the differential amplifier pair may be MIS type transistors in addition to bipolar transistors.

Therefore, the present invention is not limited to the above embodiments, but can be implemented in other embodiments by making appropriate design changes.

[Effects of the Invention] As explained above, according to the present invention, the variable impedance element inserted between the emitter terminals of the first transistor and the second transistor constituting the differential amplifier pair is a FET (field effect transistor). ), it is possible to eliminate fluctuations in the output bias caused by supplying the gain control bias to the variable impedance element. Therefore, it is possible to provide a gain control circuit that stabilizes the output bias and has good matching with the next stage.

Further, according to the present invention, the emitter currents or source currents of the first and second transistors constituting the differential amplifier pair are independently set by the corresponding first and second current setting means. As a result, sufficient operation is possible even in a small gain range, and a wide dynamic range can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a gain control circuit according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing the configuration of a gain control circuit according to a second embodiment of the invention, and FIG. The figure is a circuit diagram showing the configuration of a gain control circuit according to a third embodiment of the invention, FIG. 4 is a circuit diagram showing the configuration of a gain control circuit according to a fourth embodiment of the invention, and FIG. FIG. 6 is a circuit diagram showing the configuration of a gain control circuit according to a fifth embodiment of the present invention, FIG. The figure is a circuit diagram showing a conventional configuration of a gain control circuit. (Explanation of symbols representing main parts of the figure), Q1,
Q2, Q11, Q12...NPN type bipolar transistor, Q7, Q8, Q9, Q10...
PNP type bipolar transistor, N1, N2,
N3...N channel MOS transistor, P1,
P2, P3...P channel MOS transistor,
R1, R2...Load resistance, R3, R4...Emitter resistance, _I0 ...Current source.

Claims (1)

[Claims] 1. First and second transistors forming a differential amplification pair in response to an input signal, load means serving as a load for the first and second transistors, and a gate terminal connected to a gain control bias. a FET (field effect transistor) connected between the emitter terminals or the source terminals of the first and second transistors; and a FET (field effect transistor) connected between the emitter terminal or the source terminal of the first transistor and a power supply; a first current setting means for setting the emitter current or source current of the first transistor; and a first current setting means configured to set the emitter current or source current of the second transistor; A gain control circuit comprising: second current setting means for setting a current.