JPH0551212B2 - - Google Patents
Info
- Publication number
- JPH0551212B2 JPH0551212B2 JP62038801A JP3880187A JPH0551212B2 JP H0551212 B2 JPH0551212 B2 JP H0551212B2 JP 62038801 A JP62038801 A JP 62038801A JP 3880187 A JP3880187 A JP 3880187A JP H0551212 B2 JPH0551212 B2 JP H0551212B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pll
- transmitting
- receiving
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/10—Internal combustion engine [ICE] based vehicles
- Y02T10/12—Improving ICE efficiencies
Landscapes
- Transceivers (AREA)
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は単信方式(プレストーク方式)の無線
機において、送信用と受信用の2つの電圧制御発
振回路を具備したPLLシンセサイザ回路に関す
るものである。[Detailed Description of the Invention] "Industrial Application Field" The present invention relates to a PLL synthesizer circuit equipped with two voltage-controlled oscillator circuits for transmission and reception in a simplex system (press talk system) radio device. It is.
「従来の技術」
従来、この種の回路は第2図に示すように、送
信局部発振用電圧制御発振回路(以下送信用
VCOという)1と、受信局部発振用電圧制御発
振回路(以下受信用VCOという)2とは、それ
ぞれバツフアアンプ3,4を介してアイソレータ
5,6に結合され、さらに、このアイソレータ
5,6の出力側をカプラ7,8によつて分岐し
て、送信側は送信PLLシンセサイザ出力端子9
とプリスケーラ10に結合され、受信側は受信
PLLシンセサイザ出力端子11と前記プリスケ
ーラ10に結合され、また、このプリスケーラ1
0には位相比較器と可変分周器を含んだPLL用
IC12が結合され、このPLL用IC12の入力側
には、分周回路13を介して基準発振回路14が
結合され、出力側には切換回路15を介して送信
用ループフイルタ16と受信用ループフイルタ1
7が結合され、送信用ループフイルタ16は前記
送信用VCO1に結合され、受信用ループフイル
タ17は前記受信用VCO2に結合されて構成さ
れていた。“Prior Art” Conventionally, this type of circuit has been known as a voltage controlled oscillation circuit for transmitting local oscillation (hereinafter referred to as a transmitting local oscillation circuit), as shown in Figure 2.
VCO) 1 and a voltage controlled oscillation circuit for receiving local oscillation (hereinafter referred to as receiving VCO) 2 are coupled to isolators 5 and 6 via buffer amplifiers 3 and 4, respectively, and the outputs of these isolators 5 and 6 are The side is branched by couplers 7 and 8, and the transmitting side is connected to the transmitting PLL synthesizer output terminal 9.
is coupled to the prescaler 10, and the receiving side receives
is coupled to the PLL synthesizer output terminal 11 and the prescaler 10;
0 is for PLL including phase comparator and variable frequency divider
A reference oscillation circuit 14 is connected to the input side of this PLL IC 12 via a frequency dividing circuit 13, and a transmitting loop filter 16 and a receiving loop filter are connected to the output side via a switching circuit 15. 1
The transmitting loop filter 16 was coupled to the transmitting VCO 1, and the receiving loop filter 17 was coupled to the receiving VCO 2.
「発明が解決しようとする問題点」
第2図に示すような従来の回路では、送信用
VCOと受信用VCOとの後に、反射波の防止のた
めに、それぞれアイソレータやカプラなどの特殊
な部品を必要として高価になるという問題があつ
た。``Problems to be solved by the invention'' In the conventional circuit shown in Figure 2, the transmission
There was a problem in that the VCO and the receiving VCO each required special parts such as isolators and couplers to prevent reflected waves, making them expensive.
「問題点を解決するための手段」
本発明は上述のような問題点を解決するために
なされたもので、プレストーク方式の無線機であ
つて、1つのPLL用ICを、切換回路を介して送
信用VCOと受信用VCOの2つのVCOに切換可能
に結合して送信と受信の周波数を制御するように
したPLLシンセサイザ回路において、前記送信
用VCOの出力を、バツフアアンプを介してハイ
ブリツド回路の一方の入力端子に結合し、前記受
信用VCOの出力を、バツフアアンプを介して前
記ハイブリツド回路の他方の入力端子に結合し、
前記ハイブリツド回路の一方の出力端子を前記切
換回路と連動する切換回路を介してPLLシンセ
サイザ出力端子に結合し、前記ハイブリツド回路
の他方の出力端子をプリスケーラを介して前記
PLL用ICに結合してなるものである。"Means for Solving the Problems" The present invention has been made to solve the above-mentioned problems, and is a press talk type radio device in which one PLL IC is connected via a switching circuit. In a PLL synthesizer circuit that is switchably coupled to two VCOs, a transmitting VCO and a receiving VCO, to control the transmitting and receiving frequencies, the output of the transmitting VCO is connected to a hybrid circuit via a buffer amplifier. coupling the output of the receiving VCO to the other input terminal of the hybrid circuit via a buffer amplifier;
One output terminal of the hybrid circuit is coupled to the PLL synthesizer output terminal via a switching circuit interlocking with the switching circuit, and the other output terminal of the hybrid circuit is coupled to the PLL synthesizer output terminal via a prescaler.
It is combined with a PLL IC.
「作用」
ハイブリツド回路のすべてのポート(入出力端
子)がこれに接続されている回路と整合がとれて
いるものとすると、ハイブリツド回路の性質によ
りバツフアアンプの出力は所定値だけ減衰されて
2つのポートに分岐される。分岐された後段の回
路の入力端子で反射した信号は送信時は受信用バ
ツフアアンプで、また受信時は送信用バツフアア
ンプで吸収され、他方のバツフアアンプへの反射
はなく、電圧制御発振回路への悪影響を及ぼさな
い。``Operation'' Assuming that all ports (input/output terminals) of a hybrid circuit are matched with the circuits connected to it, the output of the buffer amplifier is attenuated by a predetermined value due to the nature of the hybrid circuit, and the two ports are attenuated. It is branched into. The signal reflected at the input terminal of the branched subsequent circuit is absorbed by the receiving buffer amplifier when transmitting, and by the transmitting buffer amplifier when receiving, and is not reflected to the other buffer amplifier, causing no adverse effect on the voltage controlled oscillator circuit. Not affected.
「実施例」
以下、本発明の一実施例を図面に基づき説明す
る。“Example” An example of the present invention will be described below based on the drawings.
本発明では、第1図に示すように、第2図の従
来回路における2個のアイソレータ5,6と2個
のカプラ7,8を省き、ブランチライン形の3dB
減衰のハイブリツド回路18を用いたものであ
る。すなわち、送信用VCO1には送信用バツフ
アアンプ3を介して前記ハイブリツド回路18の
一方の入力端子19に結合され、同様に、受信用
VCO2には受信用バツフアアンプ4を介してハ
イブリツド回路18の他方の入力端子20に結合
され、このハイブリツド回路18の一方の出力端
子21は切換回路23の共通端子24に結合さ
れ、他方の出力端子22はプリスケーラ10に結
合される。前記切換回路23は切換回路15と連
動して切換えられる。その他の構成は第2図の従
来回路と変りはない。 In the present invention, as shown in FIG. 1, two isolators 5, 6 and two couplers 7, 8 in the conventional circuit of FIG. 2 are omitted, and a branch line type 3 dB
This uses an attenuation hybrid circuit 18. That is, the transmission VCO 1 is coupled to one input terminal 19 of the hybrid circuit 18 via the transmission buffer amplifier 3, and similarly, the reception VCO 1 is connected to one input terminal 19 of the hybrid circuit 18.
The VCO 2 is coupled to the other input terminal 20 of the hybrid circuit 18 via the receiving buffer amplifier 4, one output terminal 21 of this hybrid circuit 18 is coupled to the common terminal 24 of the switching circuit 23, and the other output terminal 22 is coupled to prescaler 10. The switching circuit 23 is switched in conjunction with the switching circuit 15. Other configurations are the same as the conventional circuit shown in FIG.
以上のような構成において、送信時には切換回
路23,15を送信側へ切換える。 In the above configuration, during transmission, the switching circuits 23 and 15 are switched to the transmitting side.
ここで、ハイブリツド回路18のすべての入出
力端子19,20,21,22が、これらに接続
されている回路3,4,23,10と整合がとれ
ていると、3dB減衰のハイブリツド回路18の性
質上、送信用バツフアアンプ3の出力は3dBの減
衰をもつて2つの出力端子21,22に分岐され
る。分岐された後の回路23,10の入力端子で
反射した信号は受信用バツフアアンプ4の出力整
合回路で吸収させるので、送信用バツフアアンプ
3への反射はなく、送信用と受信用の2つの
VCO1,2への悪影響を及ぼさない。 Here, if all the input/output terminals 19, 20, 21, 22 of the hybrid circuit 18 are matched with the circuits 3, 4, 23, 10 connected to these, the hybrid circuit 18 with 3 dB attenuation Due to its nature, the output of the transmitting buffer amplifier 3 is branched into two output terminals 21 and 22 with 3 dB attenuation. The signals reflected at the input terminals of the circuits 23 and 10 after being branched are absorbed by the output matching circuit of the receiving buffer amplifier 4, so there is no reflection to the transmitting buffer amplifier 3, and two signals, one for transmitting and one for receiving, are absorbed by the output matching circuit of the receiving buffer amplifier 4.
No adverse effect on VCO1 and 2.
受信時には切換回路23,15を受信側へ切換
えることにより送信時と略同様の動作をなす。 During reception, switching circuits 23 and 15 are switched to the receiving side, thereby performing substantially the same operation as during transmission.
なお、送信時には送信用VCO1が動作して、
受信用VCO2は発振を停止し、また、受信時に
は受信用VCO2が動作して、送信用VCO1は発
振を停止する。また、2つのバツフアアンプ3,
4は常時動作している。 In addition, when transmitting, the transmitting VCO1 operates,
The reception VCO 2 stops oscillation, and during reception, the reception VCO 2 operates and the transmission VCO 1 stops oscillation. In addition, two buffer amplifiers 3,
4 is always in operation.
「発明の効果」
本発明は上述のように構成したので、ハイブリ
ツド回路によつてアイソレータとカプラの働きを
代用でき、極めて安価に提供できるものである。[Effects of the Invention] Since the present invention is configured as described above, the functions of an isolator and a coupler can be substituted by a hybrid circuit, and it can be provided at an extremely low cost.
第1図は本発明によるPLLシンセサイザ回路
の一実施例を示す電気回路図、第2図は従来の回
路図である。
1……送信局部発振用電圧制御発振回路(送信
用VCO)、2……受信局部発振用電圧制御発振回
路(受信用VCO)、3……送信用バツフアアン
プ、4……受信用バツフアアンプ、9……送信用
出力端子、10……プリスケーラ、11……受信
用出力端子、12……PLL用IC、13……分周
回路、14……基準発振回路、15……切換回
路、16……送信用ループフイルタ、17……受
信用ループフイルタ、18……ハイブリツド回
路、19,20……入力端子、21,22……出
力端子、23……切換回路、24……共通端子。
FIG. 1 is an electric circuit diagram showing an embodiment of a PLL synthesizer circuit according to the present invention, and FIG. 2 is a conventional circuit diagram. 1... Voltage controlled oscillation circuit for transmitting local oscillation (VCO for transmitting), 2... Voltage controlled oscillating circuit for receiving local oscillation (VCO for receiving), 3... Buffer amplifier for transmitting, 4... Buffer amplifier for receiving, 9... ... Output terminal for transmission, 10 ... Prescaler, 11 ... Output terminal for reception, 12 ... PLL IC, 13 ... Frequency division circuit, 14 ... Reference oscillation circuit, 15 ... Switching circuit, 16 ... Transmission Reliable loop filter, 17... Loop filter for reception, 18... Hybrid circuit, 19, 20... Input terminal, 21, 22... Output terminal, 23... Switching circuit, 24... Common terminal.
Claims (1)
PLL用IC12を切換回路15を介して送信局部
発振用と受信局部発振用の2つの電圧制御発振回
路1,2に切換可能に結合して送信と受信の周波
数を制御するようにしたPLLシンセサイザ回路
において、 前記送信局部発振用電圧制御発振回路1の出力
を、バツフアアンプ3を介してハイブリツド回路
18の一方の入力端子19に結合し、 前記受信局部発振用電圧制御発振回路2の出力
を、バツフアアンプ4を介して前記ハイブリツド
回路18の他方の入力端子20に結合し、 前記ハイブリツド回路18の一方の出力端子2
1を前記切換回路15と連動する切換回路23を
介してPLLシンセサイザ出力端子9,11に結
合し、 前記ハイブリツド回路18の他方の出力端子2
2をプリスケーラ10を介して前記PLL用IC1
2に結合してなることを特徴とするPLLシンセ
サイザ回路。 2 ハイブリツド回路は3db減衰のブランチライ
ン形からなる特許請求の範囲第1項記載のPLL
シンセサイザ回路。[Claims] 1. A press-talk type radio device, which has one
A PLL synthesizer circuit in which a PLL IC 12 is switchably coupled to two voltage controlled oscillation circuits 1 and 2 for transmitting local oscillation and receiving local oscillation via a switching circuit 15 to control the transmitting and receiving frequencies. The output of the voltage controlled oscillation circuit 1 for transmitting local oscillation is coupled to one input terminal 19 of the hybrid circuit 18 via the buffer amplifier 3, and the output of the voltage controlled oscillating circuit 2 for receiving local oscillation is coupled to the buffer amplifier 4. to the other input terminal 20 of the hybrid circuit 18 via one output terminal 2 of the hybrid circuit 18 .
1 to the PLL synthesizer output terminals 9 and 11 via a switching circuit 23 interlocking with the switching circuit 15, and the other output terminal 2 of the hybrid circuit 18.
2 to the PLL IC 1 via the prescaler 10.
2. A PLL synthesizer circuit characterized in that the PLL synthesizer circuit is formed by combining two. 2. The hybrid circuit is a PLL according to claim 1 consisting of a branch line type with 3db attenuation.
synthesizer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038801A JPS63206028A (en) | 1987-02-20 | 1987-02-20 | PLL synthesizer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038801A JPS63206028A (en) | 1987-02-20 | 1987-02-20 | PLL synthesizer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63206028A JPS63206028A (en) | 1988-08-25 |
| JPH0551212B2 true JPH0551212B2 (en) | 1993-08-02 |
Family
ID=12535396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62038801A Granted JPS63206028A (en) | 1987-02-20 | 1987-02-20 | PLL synthesizer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63206028A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101836357A (en) * | 2007-11-21 | 2010-09-15 | 富士通株式会社 | Power amplifier |
| JP5514501B2 (en) * | 2009-10-08 | 2014-06-04 | 日本無線株式会社 | Impedance matching circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62186621A (en) * | 1986-02-12 | 1987-08-15 | Hitachi Ltd | Local oscillator for satellite communication |
-
1987
- 1987-02-20 JP JP62038801A patent/JPS63206028A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63206028A (en) | 1988-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |