JPH0551997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a data read circuit.

(Prior art) As semiconductor memory becomes more highly integrated, the memory cell size becomes smaller, and in static RAM in particular, the driver transistors that make up flip-flops become smaller, reducing the drive ability and increasing the load on bit lines and other devices. Since the stray capacitance of the bit line increases, the voltage change of the bit line becomes slower, and the read speed becomes slower.

Therefore, when reading, a one-shot pulse is generated by detecting a change in the address, thereby making the bit line, data line, etc. equal potential.Then, the word line is turned on, and the bit line pair is slightly changed by the selected memory cell. It has been proposed to operate a sense amplifier controlled by a clock after a potential difference is generated to amplify the potential difference between the bit lines and thereby speed up the read operation.

Furthermore, in order to reduce average operating current and instantaneous current consumption, the memory cell array is divided into multiple blocks, and the common data line is also divided into multiple blocks, and signals are sent to the data output circuit via the divided block selection circuit. A method of communicating this is being considered.

FIG. 2 is a diagram showing a conventional semiconductor memory device divided into two parts using the above method. In this diagram,
All transistors are enhancement type
A MOS transistor whose arrow points toward the gate side represents an N type, and one whose arrow points outward represents a P type. Also, in the figure, 1
A and 1B are memory cells, 2A and 2B are column sense amplifiers, and 3 is a buffer sense amplifier. Further, 4A, 5A, 4B, and 5B are bit lines, and 6A, 7A, 6B, 7B, 8, and 9 are data lines. Also, 10, 11, 12, 13,
14 and 15 are outputs of a Y decoder circuit (not shown). Furthermore, 16 and 17 are word lines, 1
Reference numerals 8 and 19 are lines for activating the divided block column sense amplifier, and 20 is a line for activating the buffer sense amplifier. Also, T1,
T2, T3, T4, T5, T6, T7, T8 are connected between the bit line and the data line,
These are transistors that constitute a transfer gate, and T9, T10, T11, T12, T13, T
14, T15, and T16 are transistors forming divided block selection circuits A and B. moreover,
C1, C2, C3, C4 are bit line stray capacitances, C5, C6, C7, C8, C9, C1
0 is the stray capacitance of the data line.

The operation of the device configured in this way will be explained.
Now, consider the case where the word line 16 rises and selects the memory cell 1A. At this time, it is assumed that each bit line and data line has been precharged to the power supply voltage Vcc by a one-shot pulse or the like. When word line 16 rises, memory cell 1A begins discharging bit line 4A (or bit line 5A). At this time, the output 10 of the Y decoder circuit,
11, 14, 15 are fixed, and transistors T1, T2, T3, T4, T9, T10, T1
1, T12 is in the on state. For this reason,
The memory cell 1A discharges the charges of the stray capacitances C1, C5, and C9 (or the stray capacitances C2, C6, and C10). And bit lines 4A, 5
After a certain degree of potential difference is generated at A, the signal on the line 18 is set to the "H" level, and the column sense amplifier 2A is operated to amplify the signal on the bit line. Furthermore, after a suitable time, the signal on line 20 is set to "H".
level to operate the buffer sense amplifier 3 and transmit the signal to an output circuit (not shown) connected to the data lines 8 and 9. Note that the above operation is for the case where memory cell 1A is selected, but
When memory cell 1B of another block is selected, word line 17 rises and transistors T5, T6, T7, T8, T13, T14, T
15 and T16 are turned on, and the signal on line 19 becomes "H" level, and the same operation occurs.

(Problem to be Solved by the Invention) However, in such a conventional device, since the wiring lengths of the data lines 6A, 7A and 6B, 7B differ depending on the positions of the divided block selection circuits A, B, the stray capacitance C5 , C6, C7, and C8 are unbalanced. Therefore, memory cells 1A and 1B
Discharge times will be different, and the timing of lines 18 and 20 (or lines 19 and 20) must be adjusted to match the worst conditions, resulting in slower read speeds and lower operating margins. It was hot.

Therefore, an object of the present invention is to enable faster and more stable read operations.

(Means for Solving the Problems) In the semiconductor memory device of the present invention, a sense amplifier circuit is provided on each data line corresponding to each of the divided memory cell arrays, and a transfer amplifier circuit consisting of an NMOS transistor and a PMOS transistor is provided. The PMOS transistor of the divided block selection circuit constituted by an agate is made conductive after the sense amplifier circuit operates.

(Function) By doing this, it becomes possible to arrange the sense amplifier circuit and the divided block selection circuit close to the memory cells of the same block, and the variation between blocks in the stray capacitance to be discharged by the memory cells is reduced. In addition, the stray capacitance to be discharged is itself reduced.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention. In this figure, for convenience of explanation, the same parts as in FIG. 2 are given the same numbers.

In FIG. 1, 1A and 1B are memory cells, respectively. Memory cell 1A is connected to bit lines 4A and 5A and word line 16, and memory cell 1A is connected to bit lines 4A and 5A and word line 16.
B is connected to bit lines 4B, 5B and word line 17. 2A and 2B are column sense amplifiers, respectively. The column sense amplifier 2A is connected to the bit lines 4A and 5A and the column sense amplifier activation signal line 18 of the divided block, and the column sense amplifier 2B is connected to the bit lines 4B and 5B.
and connected to line 19 of the column sense amplifier activation signal of the divided block. 6A, 7A, 6
B and 7B are data lines, and between these data lines 6A, 7A, 6B, and 7B and the bit lines 4A, 5A, 4B, and 5B, P and N pairs of MOS transistors forming transfer gates are connected, respectively. . That is, a PMOS transistor T is connected between the bit line 4A and the data line 6A.
1 and NMOS transistor T2 are connected. The sources and drains of these transistors T1 and T2 are connected in parallel, and the drain is connected to the bit line 4A.
The other source is connected to data line 6A. Between bit line 5A and data line 7A
NMOS transistor T3 and PMOS transistor T4 are connected. The connection state is the same as that of MOS transistors T1 and T2. Bit line 4B
A PMOS transistor T5 and an NMOS transistor T6 are connected between the data line 6B and the data line 6B.
The connection state is the same as that of MOS transistors T1 and T2. Bit line 5B and data line 7B
An NMOS transistor T7 and a PMOS transistor T8 are connected between them. The connection state is the same as that of MOS transistors T1 and T2. and,
NMOS transistors T2 and T3 have their gates connected in common and are connected to output 10 of a Y-decoder circuit (not shown), and similarly, PMOS transistors T1 and T4 have their gates connected to output 10 of a Y-decoder circuit (not shown).
Connected to 1. Also, NMOS transistor T
6 and T7 have their gates connected to the output 12 of the Y decoder circuit, and PMOS transistors T5 and T8 have their gates connected to the output 13 of the Y decoder circuit.
3A is a buffer sense amplifier (sense amplifier circuit), which is connected to data lines 6A and 7A. Further, a line 20 for the buffer sense amplifier activation signal of the divided block is connected to the buffer sense amplifier 3A. 3B is a buffer sense amplifier (sense amplifier circuit) equivalent to buffer sense amplifier 3A, and data lines 6B,
Connected to 7B. This buffer sense amplifier 3
A line 21 of the buffer sense amplifier activation signal of the divided block is connected to B. 8 and 9 are data lines connected to an output circuit (not shown). This data line 8, 9 and data line 7
A divided block selection circuit A is connected between A and 6A, in other words, between the output circuit and the buffer sense amplifier 3A. Similarly, data line 8,
9 and data lines 7B and 6B, in other words, a divided block selection circuit B is connected between the output circuit and the buffer sense amplifier 3B. The divided block selection circuit A includes NMOS and PMOS transistors T9 and T1 that constitute a transfer gate.
0, T12, and T11. NMOS
Transistor T9 and PMOS transistor T10
The source and drain are connected in parallel, the drain is connected to the data line 6A, and the source is connected to the data line 9. Similarly, NMOS transistor T12 and PMOS transistor T11
The source and drain are connected in parallel, the drain is connected to the data line 7A, and the source is connected to the data line 8. Also, the gates of the NMOS transistors T9 and T12 are connected to the output 14 of the Y decoder circuit, while the line 20
is connected to the gates of PMOS transistors T10 and T11 via an inverter 22. The divided block selection circuit B includes NMOS and PMOS transistors T13 and T1 that constitute a transfer gate.
4, T16, and T15. NMOS
Transistor T13 and PMOS transistor T1
4 has its source and drain connected in parallel, the drain is connected to the data line 9, and the source is connected to the data line 6B. Similarly, NMOS transistor T16 and PMOS transistor T15
The source and drain are connected in parallel, the drain is connected to the data line 8, and the source is connected to the data line 7B. Furthermore, the gates of the NMOS transistors T13 and T16 are connected to the output 15 of the Y decoder circuit, while the line 2
1 is connected to the gates of PMOS transistors T14 and T15 via an inverter 23. In addition,
C1, C2, C3, C4 are bit lines 4A, 5
A, 4B, 5B stray capacitance, C5, C6,
C7, C8, C9, C10 are data lines 6A,
These are the stray capacitances of 7A, 6B, 7B, 9, and 8.

The operation of the device configured in this way will be explained.
Now, consider the case where the word line 16 rises and selects the memory cell 1A. At this time, it is assumed that each bit line and data line has been precharged to the power supply voltage Vcc by a one-shot pulse or the like. When word line 16 rises, memory cell 1A begins discharging bit line 4A (or bit line 5A). At this time, the output 10 of the Y decoder circuit,
11 and 14 have been determined, and the transistors T1,
T2, T3, T4, T9, and T12 are in the on state. However, since the buffer sense amplifier activation signal on line 20 is at "L" level,
The inverted signal of the inverter 22 output is at "H" level, and the PMOS transistors T10 and T1
1 is in the off state. Therefore, the electric charge of stray capacitance C9 (or stray capacitance C10) is lower than the potential of data line 6A (or data line 7A).
Vcc−V _TN (V _TN is NMOS transistor T9, T12
(threshold voltage) can be ignored until it becomes less than the threshold voltage, so the only charges that the memory cell 1A should discharge are the stray capacitances C1 and C5 (or the stray capacitances C2 and C6).
Therefore, the potential difference between bit lines 4A and 5A is reduced by stray capacitance C compared to the conventional circuit.
9 (or stray capacitance C10). Therefore, the operation timing of the column sense amplifier 2A can be advanced, and high-speed reading becomes possible. Thereafter, the buffer sense amplifier activation signal on the line 20 is set to "H" level to drive the buffer sense amplifier 3A, and the PMOS transistors T10 and T11 are turned on to transmit a signal to the output circuit. At this time, MOS transistors T10 and T11 are PMOS
Since they are transistors, data lines 6A and 9, and 7A and 8 are connected at equal potential.

Although the above description is for the case where the memory cell 1A is selected, the same operation is performed when the memory cell 1B of another block is selected.

Further, in the above device, since the buffer sense amplifier and the divided block selection circuit are dedicated to each block, they are arranged close to the memory cells of the same block, and the data lines 6A, 7A, 6B, 7
The wiring lengths of B can be made equal and shorter. In other words, the stray capacitances C5, C6, C7, and C8 of the data lines 6A, 7A, 6B, and 7B are smaller than in the conventional configuration and have the same value, eliminating variations between each block. The operating margin is improved.

(Effects of the Invention) As described in detail above, the semiconductor memory device of the present invention includes a sense amplifier circuit provided on each data line corresponding to each of the divided memory cell arrays, and a transfer gate of the divided block selection circuit. Since the PMOS transistors constituting the sense amplifier circuit are made conductive after the sense amplifier circuit is activated, it is possible to reduce the stray capacitance that the memory cells must discharge, and it is also possible to eliminate the unbalance of the stray capacitance of each data line. This makes it possible to speed up the read operation and expand the operating margin.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor memory device of the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor memory device. 1A, 1B...Memory cell, 6A, 7A, 6
B, 7B, 8, 9...Data line, 3A, 3B
... Buffer sense amplifier, A, B ... Divided block selection circuit, T9, T12, T13, T16...
...NMOS transistor, T10, T11, T1
4, T15...PMOS transistor, 20,2
1... Line of buffer sense amplifier activation signal of divided block, 22, 23... Inverter.

Claims (1)

[Scope of Claims] 1. A memory cell that stores information; first and second bit lines that have different potential levels depending on the information in the memory cell; and first and second bit lines that have different potential levels depending on the first and second bit lines. a sense that is connected to the first and second data lines and starts an amplification operation at a first time when a minute potential difference occurs between the first and second data lines; a sense amplifier circuit that is an amplifier circuit and amplifies the minute potential difference between the first and second data lines; an output means; and a sense amplifier circuit that electrically connects the first data line and the output means. a first transistor circuit in which a first PMOS transistor and a first NMOS transistor are connected in parallel; a second PMOS transistor and a second NMOS electrically connect the second data line and the output means; a second transistor circuit in which a transistor is connected in parallel, and the first and second PMOS transistors after the first time and after the potential difference between the first and second data lines becomes sufficiently large. ON state, and before the first and second PMOS transistors become ON state, the first and second PMOS transistors are turned on.
1. A semiconductor memory device comprising: control means for turning on an NMOS transistor. 2. The semiconductor memory device according to claim 1, wherein the control means turns on the first and second NMOS transistors before the first time.