JPH0552952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a liquid crystal driving device that applies a driving potential to a common electrode and a select electrode of a liquid crystal (LCD).

(Prior Art) Conventionally, as a technology in this field, there is one shown in FIG. 2, for example.

FIG. 2 is a block diagram of a conventional liquid crystal driving device.
Although not shown in Figure 2, the output terminal OUT
is connected to the common electrode or select electrode of the liquid crystal display device. For example, when the liquid crystal panel is a matrix panel with a dot display method, such electrodes include a common electrode arranged in a plurality of strips in the horizontal direction, and a common electrode arranged in a vertical direction on the opposite side of this electrode and orthogonal to the common electrode. It consists of a plurality of select electrodes arranged in a strip shape, and a voltage selectively applied to both electrodes changes the LCD (liquid crystal) at a predetermined location to display a display.

A decoder 1 constituting the drive circuit is connected to input terminals for inputting drive input signals IN1 and IN2 from a higher-level control unit (not shown), and is supplied with a high power supply potential VDD and a low power supply potential VSS as power supplies. . The binary input signals IN1 and IN2 are converted into four signals D1 to D2 in the decoder 1 and output to the level shift circuit 2, but the level of this signal (first logic level signal) is at the high power supply potential.
It is set to a level between VDD and low power supply potential VSS. The level shift circuit 2 has the above potential VDD,
VSS is applied, and at the same time, the third bias potential V3 is applied. And level shift circuit 2
is the first logic level signal D1~ from decoder 1
D4 is converted into four signals S1, S2, S3, and S4, and the level of this signal (second logic level signal) is equal to the above-mentioned high power supply potential VDD and bias potential V
It is set at a level between 3 and 3.

The second logic level signal S1 is of P channel type.
The second logic level signal S2 is applied to the gate of MOSFET (hereinafter referred to as P FET) 11.
A second logic level signal S3 is applied to the gate of P
The second logic level signal 4 is applied to the gate of the FET 13, and the second logic level signal 4 is applied to the gate of an N-channel MOSFET (hereinafter referred to as N FET) 14. Further, the logic level signal S2 is inverted by the inverter 3,
The logic level signal S3 is applied to the gate of N FET 15 connected in parallel with P FET 12, and is inverted by an inverter 4 and applied to the gate of N FET 16 connected in parallel with P FET 13. Furthermore, the source of P FET11 is connected to a high power supply potential VDD, the sources of P FET12 and N FET15 are commonly connected to a first bias potential V1,
The sources of P FET13 and N FET16 are commonly connected to the second bias potential V2, and N
The source of the FET 14 is connected to the third bias potential V3. And P FET11, 12,
13 and the drains of N FETs 14, 15, and 16 are commonly connected to the output terminal OUT.

Next, the operation of the apparatus having the above configuration will be explained using the signal waveform diagram shown in FIG. Now, one drive input signal IN1 is at low level (hereinafter referred to as "L").
Assuming that the other drive input signal IN2 is at a high level (hereinafter referred to as "H"), the first logic level signals D1 to D4 output from the decoder 1 are as shown below.

IN1 IN2 D1 D2 D3 D4 L H L H H H Therefore, only P FET11 is turned on (conduction between the source and drain), and the other P FET12, 13 and N FET15, 16 are all off (the source and drain are cut off). ) remains as it was. As a result, as shown in Figure 3, the output terminal OUT has a P
A drive signal of high power supply potential VDD is outputted via FET11.

Next, drive input signals IN1 and IN2 are both “H”
, the first logic level signals D1 to D
4 is as shown below.

IN1 IN2 D1 D2 D3 D4 H H H H H L Therefore, only the N FET 14 is turned on, and the third bias potential V3 is output to the output terminal OUT.

Next, when the drive input signals IN1 and IN2 are both "L", the first logic level signals D1 to D4 become as shown below.

IN1 IN2 D1 D2 D3 D4 L L H L H H Therefore, only N FET15 and P FET12 are turned on, and the output terminal OUT shown in FIG.
A bias potential V1 is output.

Finally, one drive input signal IN1 is “H”,
When the other drive input signal IN2 is "L", the first logic level signals D1 to D4 are as shown below.

IN1 IN2 D1 D2 D3 D4 H L H H L H Therefore, only P FET13 and N FET16 are turned on, and the second bias potential V2 is outputted to the output terminal OUT.

In the device with the above configuration, for example, in order to drive the liquid crystal panel, |V1-V2| is applied between the common electrode and the select electrode to put the liquid crystal in an inactive state, and the magnitude of |VDD-V3| Threshold for activation (Vlcd)
Must be above. (Vlcd＞｜VDD−V
3 |).

(Problem to be Solved by the Invention) However, in the device with the above configuration, the threshold value of the liquid crystal is generally Vth = 2.5 to 20V, so
Set a potential difference of 5V between VDD and VSS, and
Set a potential difference of approximately 1.33 to 6.66V between VDD and V1, between V1 and V2, and between V2 and V3, respectively.
When the potential between VDD and V3 is set to 4 to 20V,
Although it is possible to apply a bias greater than the threshold Vth between the electrodes of the liquid crystal panel to drive it appropriately,
If the potential between VDD and V3 is set to 2.5V, for example, it becomes impossible to apply a bias higher than the threshold value Vlcd between the electrodes of the liquid crystal panel due to the potential drop between the source and drain of the FET. This means that if the potential between VDD and V3 is set to 2.5V,
This is because the potential difference between the gate and the source of both the N FET and the P FET becomes too small, resulting in a drop in the current between the source and drain, which causes the problem that the liquid crystal serving as the load cannot be sufficiently driven.

The present invention solves the problem that the conventional technology has, but if the potential between the high power supply potential VDD and the third bias potential V3 is set to about 2.5 to 4.0V, the gate-source potential of the FET becomes too low. sauce·
It is an object of the present invention to provide a liquid crystal driving device that solves the problem that the drain current decreases and can sufficiently drive the liquid crystal even when the potential difference between VDD and V3 is set to, for example, 4.0 V or less.

(Means for solving the problem) In order to solve the problem, the first invention provides the following:
a first power supply potential (for example, a high power supply potential VDD);
a second power supply potential having a first potential difference in a predetermined direction from the first power supply potential (for example, a low power supply potential VSS);
in a liquid crystal driving device that outputs from an output terminal a drive potential (for example, bias potential V3) having a second potential difference from the first power supply potential in the predetermined direction or a drive signal based on the first power supply potential; The following measures have been taken:

That is, in this first invention, in response to input signals (for example, IN1, IN2), substantially the first
Or the first control signal by the second power supply potential (for example,
decoder means for outputting a logic level signal D1) and a second control signal (e.g. logic level signal D4); and a third control responsive to the second control signal and substantially based on the first power supply potential or the drive potential. a conversion means for outputting a signal (for example, a logic level signal 30); and a first MOSFET connected between the first power supply potential and the output terminal, the first MOSFET having a gate electrode to which the first control signal is applied. A first MOSFET (for example, FET21) provided and a second MOSFET connected between the drive potential and the output terminal.
MOSFET, the gate electrode of which is connected to the second
A second MOSFET to which a control signal is applied (e.g.
FET27) in parallel with the second MOSFET,
The device includes a third MOSFET (for example, FET 24) connected between the drive potential and the output terminal, and to whose gate electrode the third control signal is applied.

When the second potential difference is sufficiently larger than the first potential difference, the drive signal based on the drive potential is mainly applied to the output terminal via the third MOSFET, and the second potential difference is When the potential difference is sufficiently smaller than the first potential difference, the drive signal due to the drive potential is mainly caused by the second potential difference.
The configuration is such that it is applied to the output terminal via a MOSFET.

In the second invention, a first power supply potential (for example, a high power supply potential is VDD) and a second power supply potential (for example, a low power supply potential VSS) having a first potential difference in a predetermined direction from the first power supply potential are arranged. supplied, said first
a first drive potential (for example, bias potential V1) having a second potential difference in the predetermined direction from the power supply potential;
Or in a liquid crystal drive device that outputs a drive signal from an output terminal using a second drive potential (for example, bias potential V3) having a third potential difference larger than the second potential difference from the first power supply potential in the predetermined direction. , has taken the following measures:

That is, in this second invention, in response to input signals (for example, IN1, IN2), substantially the first
Or the first control signal by the second power supply potential (for example,
decoder means for outputting a logic level signal D2) and a second control signal (e.g. logic level signal D4); a first MOSFET connected between the first drive potential and the output terminal, the first MOSFET having the first control signal on its gate electrode; a first MOSFET (e.g., FET25) to which the signal is applied;
a second MOSFET connected between the second drive potential and the output terminal, the second MOSFET having a gate electrode supplied with the second control signal;
MOSFET (for example, FET27) and the second
A third MOSFET (for example, FET24) connected in parallel with the MOSFET between the second drive potential and the output terminal, the third control signal being applied to the gate electrode of the third MOSFET. It has.

When the third potential difference is sufficiently larger than the first potential difference, the drive signal based on the second drive potential is mainly applied to the third MOSFET.
When the third potential difference is sufficiently smaller than the first potential difference, the drive signal based on the second drive potential is mainly applied to the output terminal via the second MOSFET. It is structured as follows.

(Operation) According to the first invention, since the liquid crystal driving device is configured as described above, the decoder means decodes the input signal and outputs the first and second control signals.
This first control signal turns the first MOSFET on and off, and the second control signal turns the second MOSFET on and off.
MOSFET turns on and off. The second control signal is
It is converted into a third control signal by the conversion means, and the third MOSFET is turned on by the third control signal.
Turn off.

When the second potential difference is sufficiently larger than the first potential difference, the drive potential is mainly driven by the third potential difference.
The signal is sent to the output terminal via the MOSFET, and a drive signal is output from the output terminal and supplied to the liquid crystal driver. Further, when the second potential difference is sufficiently smaller than the first potential difference, the driving potential is mainly the second potential difference.
It is sent to the output terminal in the form of a drive signal via the MOSFET.

According to the second invention, the decoder means decodes the input signal and outputs the first and second control signals. This first control signal causes the first MOSFET to
is turned on and off, and the second
MOSFET turns on and off. The second control signal is
It is converted into a third control signal by the conversion means, and the third MOSFET is turned on by the third control signal.
Turn off.

When the third potential difference is sufficiently larger than the first potential difference, the second drive potential is sent to the output terminal mainly via the third MOSFET in the form of a drive signal. Furthermore, when the third potential difference is sufficiently smaller than the first potential difference, the second drive potential is sent to the output terminal mainly via the second MOSFET in the form of a drive signal. Therefore, the above-mentioned problems can be eliminated.

(Embodiment) FIG. 1 is a block diagram of a liquid crystal driving device showing an embodiment of the present invention. Note that the same elements as those in FIG. 2 are given the same reference numerals.

This liquid crystal driving device differs from the one shown in FIG. 2 in the following points. That is, the level shift circuit 20, which is a conversion means, inputs the first logic level signals D2 to D4 from the decoder 1, and
Second logic level signal S1 at potential between VDD and V3
It is configured to output 0, 20, 30. A P FET21 is connected between the high power supply potential VDD and the output terminal OUT, an N FET22 and a P FET25 are connected in parallel between the first bias potential V1 and the output terminal OUT, and the second bias potential V2 and the output N FET23 between terminals OUT
and P FET26 are connected in parallel, and further, N FET24 and P FET27 are connected in parallel between the third bias potential V3 and the output terminal OUT. Here, the first logic level signal D1 is applied to the gate of P FET21, and the first logic level signal D1 is applied to the gate of P FET21.
A second logic level signal S10, 2 is applied to each gate of N FET23 and N FET24.
0,30 are P FET25, P FET26,
First logic level signals D2, D3, and D4 are applied to each gate of the P FET 27.

The operation of the apparatus shown in FIG. 1 will be explained with reference to FIG. 3 mentioned above.

First, when one drive input signal IN1 is "L" and the other drive input signal IN2 is "H", logic level signals D1 to D4, S10, 2
0 and 30 are as shown below.

D1 D2 D3 D4 L H H H D10 20 30 H L3 L3 Here, "H" is the level of the high power supply potential VDD, "L" is the level of the low power supply potential VSS,
Set VDD−VSS=5V. Also, "L3" is the third
This is the level of the bias potential V3. Since these logic gate signals are input to the respective FET gates, only P FET 21 is turned on, and the others remain off. Therefore, as shown in FIG. 3, the high power supply potential VDD is
is output to the output terminal OUT in the form of a drive signal.

What should be noted here is that the first logic level signal D1 input to the gate of P FET 21 is "L" = VSS, so the potential difference between the source and gate of P FET 21 is always VDD - VSS = 5V.
This is fixed. Therefore, in the conventional device shown in FIG.
Compared to the case where 20V is input, the source-drain current will be lower, but considering the characteristics of the FET, if the gate-source potential is 4V or more, sufficient current can be supplied to drive the liquid crystal. No problems arise in terms of characteristics.

Conversely, in the conventional device shown in FIG. 2, the signal S at a potential between VDD and V3 output from the level shift circuit 2
1 turns the P FET 11 on and off, so when the potential difference between VDD and V3 is 4V or less, sufficient source-drain current cannot be obtained and the liquid crystal cannot be properly driven. On the other hand, in the device of the present invention shown in FIG. 1, the potential between the gate and source of P FET 21 is fixed at VDD-VSS = 5V, so even if the potential between VDD and V3 is lowered to 2.5V, the potential between the source and source is fixed. The drain-to-drain current does not decrease, so the liquid crystal can be appropriately driven.

Next, drive input signals IN1 and IN2 are both “H”
, the logic level signals D1 to D4, S1
0, 20, 30 are as shown below.

D1 D2 D3 D4 H H H L D10 20 30 H L3 H Therefore, only N FET24 and P FET27 are turned on, so the output terminal OUT is turned on as shown in Figure 3.
A third bias potential V3 appears at.

What should be noted here is that the signal given to the gate of P FET 27 is the first logic level signal D4=
This means that "L" = VSS. For this reason,
When VDD-VSS = 5V, when the potential difference between VDD and V3 is 4.3 to 20V, the gate-source potential becomes -0.7 to 15V, so P FET27 is turned off and does not contribute to liquid crystal drive, but between VDD and V3 When the potential difference is 2.5 to 4.3V, the gate-source potential is -2.5 to 0.7V, so the P FET 27 is turned on and contributes to driving the liquid crystal. Note that when the potential difference between VDD and V3 is 2.5 to 4.3V, the potential between the gate and source of N FET24 is also 2.5V.
Since it is ~4.3V, it is on like P FET27. N FET24 and P FET
When the potential difference between the gate and source of any of 27 is less than 4V, sufficient source-drain current cannot be obtained as a single unit due to the characteristics of the FET, but the N
Since the FET 24 and the P FET 27 are connected in parallel with each other, appropriate liquid crystal driving is possible.
This is because although the source-drain current of the N FET 24 decreases in proportion to the decrease in the potential difference between VDD and V3, the source-drain current of the P FET 27 increases and cancels each other out.

Next, drive input signals IN1 and IN2 are both “L”
, the logic level signals D1 to D4, 10
~S30 is as shown below.

D1 D2 D3 D4 H L H H D10 20 30 L3 L3 L3 Therefore, only N FET22 and P FET25 are turned on, and as shown in Figure 3, the first
A bias potential V1 is output.

Here, when the potential difference between VDD and V3 is 12.9 to 20V, the potential difference between VDD and V1 is generally VDD-V1≒(VDD-V3)/3=4.3 to
It becomes 6.7V. Therefore, the gate-source potential of the P FET 25 ranges from -0.7 to +1.7, which turns it off, and within this potential range, the P FET 25 does not contribute to driving the liquid crystal. However, since the gate-source potential of the N FET 22 is -8.6 to -13.3V, a source-drain current sufficient for driving the liquid crystal can be obtained.

When the potential difference between VDD and V3 is 0.6 to 12.9V,
The potential difference between VDD and V1 is 2.0 to 4.3V, so N
Both FET22 and pFET25 contribute to driving the liquid crystal.

On the other hand, the potential difference between VDD and V3 is 2.5V to 6V
In this case, the potential between VDD and V1 is VDD-V1≒(VDD-V3)/3=0.83~
2.0V, the gate-source potential of the N FET 22 becomes -1.67 to -4V, making it impossible to obtain a sufficient source-drain current. However, in this case, the gate-source potential of P FET25 is -
Since the voltage is 4.17 to 3V, they cancel each other out and can extract enough source-drain current to drive the liquid crystal.

Finally, one drive input signal IN1 is “H”,
When the other drive input signal IN2 is “L”,
The logic level signals are as shown below.

D1 D2 D3 D4 H H L H D10 20 30 H H L3 Therefore, N FET23 and P FET26 are turned on, and as shown in FIG.
A bias potential V2 appears.

Here, when the potential difference between VDD and V3 is 6.45 to 20V, the potential difference between VDD and V2 is VDD-V2=2・(VDD-V3)/3=4.3 to
Since the voltage becomes 13.3V, P FET26 is turned off and does not contribute to driving the liquid crystal. However, since the gate-source potential of N FET23 is 4.3 to 13.3V, N
The liquid crystal can be sufficiently driven by the source-drain current of the FET 23.

When the potential difference between VDD and V3 is 2.5 to 6.45V,
The potential difference between VDD and V2 is VDD-V2=2・(VDD-V3)/3=1.67~
It becomes 4.3V, and the potential between the gate and source of N FET23 also becomes 1.67 to 4.3V. Therefore, when the potential difference between VDD and V3 is close to 6.45V, sufficient source-drain current can be obtained with N FET23, but
As the potential difference between VDD and V3 decreases, the source-drain current decreases and eventually stops contributing to liquid crystal drive. However, on the contrary, P
The gate-source potential of FET26 is -3.33 to -
It changes to 0.7V as the potential difference between VDD and V3 decreases, and the source-drain current increases, so N
The source-drain currents of FET 23 and P FET 26 cancel each other out, making it possible to drive the liquid crystal appropriately.

In the above embodiment, another N FET is connected in parallel to the N FET 22, and a signal obtained by inverting the second logic level signal S10 is input to the gate.
A CMOS analog switch may also be configured. Furthermore, connect a P FET in parallel to N FET23 and input the inverted signal to the gate,
A CMOS analog switch may also be configured.

In addition, in the above embodiment, the potential difference between VDD and VSS is
Although it is set to 5V, it is not limited to this.
Furthermore, the channels of the FETs may be reversed to invert each logic level signal.

(Effects of the Invention) As described above in detail, according to the first invention, the first and second MOSFETs are connected between the first power supply potential and the drive potential and the output terminal, and the second
Connect a third MOSFET in parallel with the MOSFET of
When the second potential difference is sufficiently larger than the first potential difference, the drive signal based on the drive potential is mainly used as the third potential difference.
is applied to the output terminal through the MOSFET, and when the second potential difference is sufficiently smaller than the first potential difference,
The drive signal based on the drive potential is mainly used as the second
Since it is applied to the output terminal via the MOSFET, a sufficient source-drain current can be extracted even if the second potential difference becomes small.
Therefore, a liquid crystal driving device can be obtained that can sufficiently drive the liquid crystal even when the second potential difference is, for example, 2.5 to 20V.

Further, according to the second invention, the first and second voltages are connected between the first and second drive potentials and the output terminal.
When a MOSFET is connected and a third MOSFET is connected in parallel with the second MOSFET, and the third potential difference is sufficiently larger than the first potential difference, the drive signal from the second drive potential is mainly used to drive the third MOSFET.
is applied to the output terminal via the MOSFET, and when the third potential difference is sufficiently smaller than the first potential difference, the second
The drive signal based on the drive potential of
Since it is applied to the output terminal via the MOSFET, even if the third potential difference becomes small, a sufficient source-drain current can be extracted as in the first invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a liquid crystal drive device showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional liquid crystal drive device,
FIG. 3 is a signal waveform diagram when the liquid crystal driving device shown in FIGS. 1 and 2 is operated. 1... Decoder, 2, 20... Level shift circuit, D1-D4... First logic level signal (control signal), S1, S2, S3, 4, S10, 2
0, 30...Second logic level signal (control signal), VDD...High power supply potential (first power supply potential),
VSS...Low power supply potential (second power supply potential), V1 to V
3...first to third bias potentials (drive potentials),
IN1, IN2...drive input signal, OUT...output terminal.

Claims (1)

[Scope of Claims] 1. A first power supply potential and a second power supply potential having a first potential difference in a predetermined direction from the first power supply potential are supplied, and a second power supply potential is supplied from the first power supply potential in the predetermined direction. In a liquid crystal driving device that outputs a drive signal based on a drive potential having a potential difference or the first power supply potential from an output terminal, the first or second power supply potential substantially responds to an input signal.
decoder means for outputting first and second control signals based on a power supply potential;
a conversion means for outputting a third control signal based on the power supply potential or the driving potential; a first MOSFET connected between the first power supply potential and the output terminal, the first MOSFET having the first control signal on its gate electrode; the first signal is given
a second MOSFET connected between the drive potential and the output terminal, the second MOSFET having its gate electrode supplied with the second control signal;
and a third MOSFET connected between the drive potential and the output terminal in parallel with the second MOSFET.
MOSFET, and the gate electrode is connected to the third
and a third MOSFET to which a control signal is applied, and when the second potential difference is sufficiently larger than the first potential difference, the drive signal by the drive potential is mainly transmitted to the third MOSFET through the third MOSFET. applied to the output terminal, and when the second potential difference is sufficiently smaller than the first potential difference, the drive signal based on the drive potential is mainly applied to the output terminal via the second MOSFET. LCD drive device. 2. When there is not a sufficient difference between the second potential difference and the first potential difference, the second and third MOSFETs cooperate to provide the drive signal based on the drive potential to the output terminal. A liquid crystal driving device according to claim 1. 3. The liquid crystal according to claim 1 or 2, wherein the first and second MOSFETs are of the first channel type, and the third MOSFET is of the second channel type. Drive device. 4 A first power supply potential and a second power supply potential having a first potential difference in a predetermined direction from the first power supply potential are supplied, and a first power supply potential having a second potential difference in the predetermined direction from the first power supply potential are supplied. the driving potential or the first
In a liquid crystal driving device that outputs from an output terminal a drive signal based on a second drive potential having a third potential difference larger than the second potential difference in the predetermined direction from a power supply potential, first or second
decoder means for outputting first and second control signals based on a power supply potential;
a conversion means for providing a third control signal based on the power supply potential or the second drive potential; a first MOSFET connected between the first drive potential and the output terminal; a first control signal to which a first control signal is applied;
a second MOSFET connected between the second drive potential and the output terminal, the second MOSFET having a gate electrode supplied with the second control signal;
MOSFET, and a third MOSFET connected in parallel with the second MOSFET between the second drive potential and the output terminal.
MOSFET, and the gate electrode is connected to the third
and a third MOSFET to which a control signal is applied, and when the third potential difference is sufficiently larger than the first potential difference, the drive signal by the second drive potential mainly controls the third MOSFET. When the third potential difference is sufficiently smaller than the first potential difference, the drive signal based on the second drive potential is mainly applied to the output terminal via the second MOSFET. A liquid crystal driving device characterized in that: 5 When there is not a sufficient difference between the third potential difference and the first potential difference, the second and third MOSFETs cooperate to provide the drive signal based on the second drive potential to the output terminal. A liquid crystal driving device according to claim 4, characterized in that: 6. The liquid crystal driving device according to claim 4 or 5, wherein the first and second MOSFETs are of a first channel type, and the third MOSFET is of a second channel type.