JPH0555908B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a microprocessor system having a bus cycle asynchronous interface.

(Conventional technology) In recent years, with the rapid development of semiconductor technology, memory
LSIs, high-performance peripheral LSIs (large-scale integrated circuits), and microprocessors became available at low prices.
By functionally connecting these, a relatively high-performance microprocessor system can be constructed.
In the above microprocessor system, when the microprocessor is replaced from an old generation to a new generation, the system functions and timing,
In particular, how to protect system bus cycle timing is an important design issue. This determines whether the many input/output devices accumulated up to that point can be used as is, and is generally referred to as hardware compatibility.

(Problem to be solved by the invention) Normally, when a microprocessor is replaced from an old generation to a new generation, the processing speed of the microprocessor increases, and the system bus cycle also increases accordingly. Clothing becomes incompatible.

The present invention was made based on the above-mentioned circumstances, and provides a means for maintaining hardware compatibility.It is an object of the present invention to utilize conventional hardware as is, and to improve the performance of a new generation of microprocessors. The aim is to provide a microprocessor system that maximizes the

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides a system between a microprocessor and a plurality of input/output devices connected thereto via a system bus. , by inserting an asynchronous interface circuit that controls the interface with a bus cycle compatible with a microprocessor of a different generation from the above microprocessor,
This asynchronous interface circuit has the function of synchronizing the signals sent and received using the microprocessor's operating clock with the bus cycle clock, and the function of synchronizing the signals sent and received using the bus cycle clock with the microprocessor clock. I set it. The asynchronous interface circuit includes a bus status timing circuit, a wait control circuit, a hold control circuit, and a bidirectional address data bus transceiver.

(Function) The operating clock of a new generation of microprocessors
CLK ₁ and the operating clock of the old generation microprocessor are CLK ₂ (CLK ₁ > CLK ₂ ). Due to the existence of an asynchronous interface circuit with the above configuration,
Realizes system bus cycle timing based on CLK ₂ , which is independent of CLK ₁ . That is, when accessing the system bus from the microprocessor, the asynchronous interface circuit generates bus control status and timing signals based on _CLK2 . This signal is sent to the bus control circuit, where a system bus control signal is generated. on the other hand,
The system bus status signal is synchronized to the CLK ₁ timing within the asynchronous interface circuit and then sent to the microprocessor. The timing of data and address transmission and reception on the system bus is also synchronized by a bidirectional bus transceiver built into the asynchronous interface circuit.

This ensures 100% hardware compatibility while making full use of the performance of the new generation microprocessor.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a new generation microprocessor, and 2 is a memory for storing programs and data. Reference numeral 3 denotes an asynchronous interface circuit added according to the present invention, and its internal configuration and other details will be described later. 4 is a bus control circuit, 5 is a standard input/output device, and 6 is an optional input/output device. The input/output devices 5 and 6 are commonly connected to the asynchronous interface circuit 3 via a system bus 7.

Incidentally, the input/output devices 5 and 6 connected to the bus control circuit 4 and the system bus 7 are the constituent elements of a system using an old generation microprocessor. For reference, FIG. 3 shows an example of the configuration of a conventional microprocessor system. In the figure, the first
Blocks with the same numbers as those in the figures are the same as those in FIG.

FIG. 2 is a block diagram showing the internal structure of the asynchronous interface circuit 3 shown in FIG. 1. In the figure, numeral 31 is a bus status timing circuit that performs bus status conversion and timing synchronization between the new generation microprocessor 1 and the old generation bus control circuit 4. 32 is a wait control circuit of the microprocessor 1, and 33 is a hold control circuit. 34 is an address bus transceiver for transmitting and receiving address signals, and 35 is a data bus transceiver for transmitting data signals.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail using the drawings. FIG. 3 shows a configuration diagram of a system using an old generation microprocessor. The part surrounded by a broken line in the figure is the first embodiment of the present invention.
It is the same as that in the figure. The new generation microprocessor 1 is faster than the old generation microprocessor. The operating clock in the former is CLK ₁ ,
The operating clock in the latter case is CLK ₂ . Their frequencies are CLK ₁ > CLK ₂ . If CLK ₁ is an integer multiple of CLK ₂ , timing compatibility of system bus cycles can be maintained relatively easily by dividing CLK ₁ . But in general,
CLK ₁ cannot satisfy the above conditions in order to maximize the performance of the new generation microprocessor 1. Therefore, an asynchronous interface circuit 3 was provided. With this asynchronous interface circuit 3 ,
System bus cycle timing can be realized based on CLK ₂ , which is independent of CLK ₁ .

That is, when the microprocessor 1 accesses the system bus 7, the asynchronous interface circuit 3 generates bus control status and timing signals based on _CLK2 . This signal is sent to the bus control circuit 4, where a control signal for the system bus 7 is generated. On the other hand, the status signal of the system bus 7 is transmitted within the asynchronous interface circuit 3 .
Synchronize with CLK ₁ timing and send to microprocessor 1. The asynchronous interface circuit 3 also synchronizes the timing of data and address transmission and reception on the system bus 7.

FIG. 2 is an internal configuration diagram of the asynchronous interface circuit 3 , and its operation is as follows. That is, the bus status timing circuit 31
It receives bus status signals W/R#, D/C#, M/IO#, ADS#, etc. from the microprocessor 1 and decodes the bus status using _CLK1 . The timing of this decoding result is synchronized using CLK ₂ , and bus status signals S ₀ #, S ₁ #,
Create M/IO#.

The wait control circuit 32 controls the microprocessor 1 to wait until the bus cycle is completed. Ready signal from system bus 7
When BSRDY# becomes active, it is CLK ₁
synchronize with and make the ready signal CPRDY# to microprocessor 1 active.

The hold control circuit 33 is a timing synchronization circuit that holds the operation of the microprocessor 1 like DMA transfer and controls data transfer between the input/output devices 5 and 6 and the memory 2 during that time. be. A hold request BSHOLD from the system bus 7 is synchronized with CLK ₁ to create a hold request CPHOLD to the microprocessor 1.
On the other hand, the hold response from microprocessor 1
CPHLDA is synchronized with CLK ₂ and output as the hold response BSHLDA of the system bus 7.

The address bus transceiver 34 is bidirectional, and when the microprocessor 1 accesses the system bus 1, it moves to the right in the figure, while for DMA transfer, it moves to the left. When moving to the right, synchronize with CLK ₂ , and when moving to the left, synchronize with CLK ₁ . Here, BE ₃ # - BE ₀ # is an enable signal for each byte with a data width of 4 bytes, and is the enable signal for each byte of the data width of the system bus.
Interchanged with A ₁ , A ₀ , BHE#. The data bus transceiver 35 is also bidirectional, so that when the microprocessor writes data to the input/output devices 5, 6 on the system bus 7, or
When reading data from memory 2 using DMA transfer, or when reading data from memory 2 using DMA transfer, it moves to the right. On the other hand, when the microprocessor 1 reads data from the input/output devices 5 and 6 on the system bus 7, or
When writing data to memory 2 using DMA transfer, it moves to the left. Address bus transceiver 34
Similarly, when moving to the right, synchronize with CLK ₂ , and when moving to the left, synchronize with CLK ₁ . Here, it is assumed that the 32-bit data of the microprocessor 1 and the 16-bit data of the system bus are mutually converted by the bus sizing function.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1) Even if the microprocessor is changed, the existing hardware can be used as is. In other words, we can guarantee 100% hardware compatibility.

(2) The performance of new generation microprocessors can be maximized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the asynchronous interface circuit shown in FIG. 1, and FIG. 3 is a block diagram showing an example of the configuration of a conventional microprocessor system. FIG. 1... New generation microprocessor, 3 ... Asynchronous interface circuit, 7... System bus, 3
1... Bus status timing circuit, 32...
Wait control circuit, 33...Hold control circuit,
34... Address bus transceiver, 35... Data bus transceiver.

Claims (1)

[Scope of Claims] 1. A first microprocessor and a second microprocessor whose processing speed is lower than that of the first microprocessor.
The first microprocessor has an asynchronous interface circuit that controls the interface with the first microprocessor, and the interface circuit receives and receives information from the first microprocessor using the operating clock of the first microprocessor. is synchronized with the bus cycle clock of the second microprocessor, and the information from the second microprocessor sent and received by the bus cycle clock of the second microprocessor is synchronized with the first microprocessor. A first control circuit group consisting of at least a bus status timing circuit, a wait control circuit, and a hold control circuit for synchronization with the operating clock of the processor; A second control circuit group includes a bidirectional bus transceiver that synchronizes with the operating clock or the bus cycle clock of the second microprocessor and outputs desired address and data signals. microprocessor system. 2 The above bus status timing circuit is
receiving a bus status signal from at least a first microprocessor;
2. The microprocessor system according to claim 1, wherein the microprocessor system decodes the status, synchronizes the decoded result with a clock 2, and uses it as a bus status signal. 3. Claim 1, characterized in that the wait control circuit synchronizes at least the ready signal obtained via the bus with the clock 1 and uses it as the ready signal to be sent to the first microprocessor. The microprocessor system described. 4. The hold control circuit synchronizes at least a hold request that arrives via the bus with clock 1 and uses it as a hold signal to be sent to the first microprocessor, as well as synchronizes the hold request that arrives via the bus with 2. The microprocessor system according to claim 1, wherein the hold response signal is synchronized with the clock 2 and sent to the bus.