JPH0556064B2 - - Google Patents

Description

[Detailed Description of the Invention] [Prior Art] Conventionally, there has been a method in which information such as code data sent from a host computer etc. is developed as a bit image on an internal random access memory, and then this is read out and output. In an output device such as a laser beam printer (LBP), writing to the random access memory requires so-called overwriting.

That is, for example, when outputting the pattern shown in Figure 1a, first write the pattern shown in Figure 1b, and then write the pattern shown in Figure 1b.
The pattern in Figure c is overwritten. Since it is very difficult to judge whether a pattern to be written is one that is simply written or one that should be overwritten, it is necessary to clear the random access memory to be written in advance.

Therefore, it is necessary to clear the portion that has been expanded onto the random access memory, read it out again, and finished printing each time.

However, if the text output device is slow and the processing speed of the CPU is sufficient, the above operation can be achieved by the operation of the CPU only.
For high-speed printers such as laser beam printers,
The CPU's operation cannot keep up, and a high-speed sub-processor is usually used to perform parallel processing with the CPU, which has the disadvantage that the entire processing device becomes extremely expensive.

〔the purpose〕

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and it is possible to perform the overwriting process of dot pattern information on the memory, the reading of the dot pattern information from the memory, and the memory clearing process from the same timing generator. To provide a printer control device that can reduce the burden on a CPU by performing data overwrite processing and read/clear processing at high speed with an inexpensive configuration without using a high-speed processor by performing the processing based on format timing signals. be.

〔Example〕

The present invention will be described in detail below with reference to the drawings. FIG. 2 is an external view of a page printer which is a laser beam printer to which the present invention is applied.
1 is a printer body, 2 is an operation display section, and 3 is a power switch. Further, 4 is a paper discharge section. 5 is a transmission cable connected to the host. Note that the printer 1 may be a terminal or a fax machine in a network. As for the interface, Centronics' interface method, RS232-C method,
Alternatively, a video signal may be input.
In addition, the operation display section 2 has an "ON LINE" key to indicate that data is being transmitted from the host, an "ERROR SKIP" key to skip errors, and other keys for self-diagnosis, manual feeding, and printing for each page. It has a key etc. for outputting the data up to the point where it was transmitted. 6 is a ROM cartridge in which character fonts and programs such as alphabets and kanji are stored.

FIG. 3 is a block diagram showing an embodiment of the present invention.

In Figure 2, 101 consists of 8 bits.
It is a bidirectional data bus of the CPU, 102 is also a 16-bit address bus of the CPU, 103, 1
04 is AND gate, 105 is OR gate, 106
is, for example, a random access memory (hereinafter referred to as RAM) with a capacity of 128K bytes. Furthermore, RAM1
The information written in 06 is output to various output devices 999 such as an inkjet printer, an LED printer, and an LBP printer. Further, the RAM 106 may be an arithmetic device such as a microprocessor. 107 is a latch, 108 is a three-state gate, and 109 is a signal 111 and signal 1 after a certain period of time from the rise of signal 110 from the CPU.
A timing signal generating device that generates 12,
FIGS. 4 and 5 are timing charts showing the timing of this occurrence.

Also, signal 113 is H when the CPU is in write operation.
This is a level signal that becomes L level during a read operation.

In FIG. 4, when the signal 113 is at H level, that is,
The timing of each signal during CPU write operation is
In FIG. 5, when the signal 113 is at L level, that is,
The timing of each signal during CPU read operation is shown.

The operation of this embodiment will be explained below based on FIGS. 3 to 5.

First, we will explain the CPU write operation.
Code information sent from a host device (not shown) is converted into corresponding dot pattern information by a CPU (also not shown), and the data bus 10
1 is output. Next, the CPU is data bus 101
The dot pattern data output to RAM106
In order to expand the address information 102 upward, the address information 102 is output to the RAM 106, and the signal 113 is set to H level (during CPU write operation). Thereafter, a signal 110 is sent to the timing signal generator 109 to start the timing signal generator 109 (FIG. 4).

RAM 106 given address information 102
After obtaining a predetermined access time (FIG. 4), the read data 114 is output at timing 401 in FIG. The read data 114 is latched in the latch 107 by the signal 111 (FIG. 4).
be done. Since the signal 113 is at H level,
AND gates 103 and 104 are open. Therefore, information 116 and information 117 and information 101 and information 118 have the same content.

Furthermore, the three-state gate 108 is closed.

The information 117 and the information 118 are ORed by the OR gate 105, and the information 115 is sent to the RAM 10.
Write signal 112 to RAM 106
(Figure 4).

In other words, OR information with data previously written to RAM is written, which corresponds to overwriting.

Next, referring to FIG. 5, the read operation of the CPU will be described.

The dot pattern data developed on the RAM 106 is sent to a printing section (not shown) after completion of development. Since the dot pattern data once sent to the printing section no longer needs to be saved, the contents of the RAM at that address must be cleared.

In order to send the dot pattern data developed on the RAM 106 to a printing section (not shown) via the data bus 101, the CPU sets the signal 113 to L level (during a read operation of the CPU), and sends the dot pattern data developed on the RAM 106 to the RAM 106 in order to read the contents of the RAM 106. Address information 102 is sent to the recipient.

Further, as shown in FIG. 5, a signal 110 is sent to the timing signal generator 109 to start the timing signal generator 109 (FIG. 5).

After a predetermined access time (Figure 5),
Read data 114 is output from the RAM 106, and is latched into the latch 107 by the latch signal 111 (FIG. 5).

Since the signal 113 is at L level, the three-state gate 108 is open and the data bus 10
1, the same contents as the read gater 114 from the RAM are sent. Also, AND gate 103
and 104 are both closed, information 117 and information 118 are both all 0, and therefore information 115 is also all 0.

At the same time, write signal 1 is sent to RAM106.
12, information 115 whose contents are all 0 is written (FIG. 5), that is, the RAM 106 is cleared.

〔effect〕

As explained above, according to the present invention, the process of overwriting the dot pattern information in the memory, the reading of the dot pattern information from the memory, and the process of clearing the memory are performed based on timing signals of the same format from the same timing generation means. So,
By simply instructing the CPU with a signal indicating the type of processing, a start signal, dot pattern information, and address information, there is no need for actual overwriting or data clearing processing, which reduces the burden on the CPU and allows high-speed processors to be used. Data overwriting processing and read-out clearing processing can be performed at high speed with an inexpensive configuration without the need for such a configuration.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of overwriting in which pattern b is written, then pattern c is overwritten, and pattern a is output. FIG. 2 is an external view of a printer to which the present invention is applied. FIG. 3 is a block diagram showing an embodiment of the present invention. In Fig. 4, the signal 113 is H.
This is a timing chart of the signal in the case of level. FIG. 5 is a signal timing chart when the signal 113 is at L level. 109 is a timing signal generator; 106 is a timing signal generator;
RAM, 113 is a level signal.

Claims (1)

[Scope of Claims] 1. In a printer control device that stores dot pattern information in a memory and then reads out the dot pattern information from the memory and outputs it to a printer, the dot pattern information sent from the CPU and the dot pattern information are stored in the memory. information input means for inputting address information representing a storage location of the dot pattern information; a signal representing a process of writing dot pattern information into the memory or a process of reading dot pattern information from the memory; and a signal for activating the write process or read process. Start signal of CPU
and a timing signal generating means that generates various timing signals in response to a start signal from the CPU, and when the signal input means inputs the signal representing the writing process and the start signal, , based on the timing signal from the timing signal generation means, the information input means reads out the dot pattern information stored in the input address information from the memory, and also reads out the read information and the CPU.
OR-synthesize the dot pattern information input from
When the OR-combined information is written into the memory location of the address information input from the CPU, and the signal input means inputs the signal representing the read processing and the start signal, the timing signal and the timing signal used during the write processing are input. Based on the timing signal from the timing signal generation means of the same format, the information input means reads and processes the dot pattern information stored in the input address information from the memory, and also reads data for clearing the memory. A printer control device characterized in that a memory clearing process is performed by writing address information input from the CPU to a memory location.