JPH0556645B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a mask alignment method used in the manufacturing process of semiconductor devices.

(Prior art and its problems) Conventionally, in a pattern forming process using a reduction projection light exposure method, in order to accurately transfer a pattern formed on a reticle to a predetermined position on a semiconductor substrate, A common method is to perform step-and-repeat exposure while controlling the position with high precision. When a desired mask pattern is step-and-repeat exposed on a semiconductor substrate by the above method, a blank area 13 where the pattern 12 is not formed generally occurs near the outer periphery of the semiconductor substrate 11, as shown in FIG. This is generally
This is because the vicinity of the outer periphery of a semiconductor substrate is easily damaged due to contact with various jigs and the like during the semiconductor device manufacturing process. Exposure area is several mm
Conventionally, this did not pose much of a problem because it is relatively small, ranging from a square to about 10 mm square, and the blank area generated near the outer periphery of the semiconductor substrate can be kept relatively small. However, in recent years, in order to increase the productivity of reduced projection light exposure, the exposed area per step has been increased to more than 10.
Exposure equipment with enlarged dimensions of mm square to 20 mm square has been developed and is now in general use. In addition, in X-ray exposure, which is attracting attention as a high-precision transfer technology for ultra-fine patterns, step-and-repeat exposure equipment has been developed in which the exposure area per step is approximately 10 mm square to 30 mm square. In the above exposure apparatus, as shown in FIG.
Chip pattern 2 is formed in the exposure area 21 of the step.
Generally, a plurality of alignment marks 2 and 23 are formed. In this case, as shown in the exposure example of FIG.
In this case, even though there is sufficient room for forming the chip pattern 33, mask alignment cannot be performed because the alignment mark 34, which is not formed near the outer peripheral edge of the exposure mask, protrudes outside the semiconductor substrate 31. This results in a large blank area, which is one of the causes of lower utilization efficiency and productivity of semiconductor substrates.

(Object of the Invention) An object of the present invention is to improve the drawbacks of the conventional mask alignment method as described above and to provide a mask alignment method that can effectively utilize almost the entire area of a semiconductor substrate.

(Structure of the Invention) According to the present invention, in a mask alignment method using visible light and an optical lens system, a mask having four or more optical lens systems and an alignment mark provided corresponding to each of the lens systems is provided. A mask alignment method is obtained, which is characterized in that it is carried out using a combination of any two systems from among the optical lens system and alignment mark.

(Detailed explanation of configuration) Hereinafter, details of the present invention will be explained using the drawings.

In the mask alignment method of the present invention, 4
A system alignment optical system and a mask having four alignment marks provided correspondingly are used.

FIG. 4 schematically shows the main parts of a mask used in the mask alignment method of the present invention, where 41 indicates a chip pattern and 42 indicates an alignment mark.

FIG. 5 schematically shows an embodiment of step-and-repeat exposure using the mask alignment method of the present invention. Conventionally, it has not been possible to form a chip pattern in the blank area 32 of a semiconductor substrate shown in FIG. To perform mask alignment using any two alignment marks among the four alignment marks 42 shown in
As shown in FIG. 5, chips 52 can be formed over the entire surface of a semiconductor substrate 51 without waste.

(Effects of the Invention) According to the mask alignment method of the present invention, when exposing a chip pattern of the same size on a semiconductor substrate of the same size, the number of chips is 10% compared to the conventional method.
% or more, thereby improving the productivity and lowering the cost of semiconductor devices.

[Brief explanation of drawings]

Figure 1 is a schematic plan view showing a chip pattern formation area on a semiconductor substrate by conventional step-and-repeat exposure, and Figure 2 is a schematic diagram showing a general pattern arrangement on a large-diameter reticle or X-ray exposure mask. FIG. 3 is a schematic plan view showing a chip pattern forming area on a semiconductor substrate by step-and-repeat light exposure using a large-diameter reticle or general step-and-repeat type X-ray exposure; FIG. 4 is a schematic plan view showing the main parts of a mask used in the mask alignment method of the present invention, and FIG.
FIG. 3 is a schematic plan view showing how a chip pattern is formed on a semiconductor substrate by repeated X-ray exposure. Each number in the figure indicates the following. 11,
31, 51... semiconductor substrate, 12, 22, 33,
41, 52...chip pattern forming area, 13,
32... Blank area, 23, 34, 42... Alignment mark.

Claims (1)

[Claims] 1. In a mask alignment method using visible light and an optical lens system, a mask having four or more optical lens systems and an alignment mark provided corresponding to each of the lens systems is used to align the optical lens system and the alignment. A mask alignment method characterized by using a combination of two arbitrary systems from among marks.