JPH0556825B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data creation device for multi-core cable testing, and relates to a multi-core cable suitable for the configuration of a cable tester that conducts continuity, insulation, and voltage resistance tests of multi-core cables. Related to test data creation device.

[Conventional technology]

Currently, multi-core cables consisting of a plurality of insulated core wires are often used in communication transmission networks.

In order to ensure high reliability in this multi-core cable, it is necessary to keep the insulation resistance and withstand voltage leakage current of each core wire extremely small within a predetermined range, so a preset test signal is used. In addition to detecting insulation resistance and breakdown voltage leakage current for each core wire, insulation characteristics and breakdown voltage characteristics were measured.

[Problem that the invention seeks to solve]

However, the insulation characteristics and voltage resistance characteristics of a multicore cable are greatly affected by the type of conductor and insulation coating used for the core wire, and the connection status of the connector connected to the multicore cable. For example, the resistance and inductance of each core wire, and the capacitance between the core wires tend to affect their insulation properties and withstand voltage characteristics. Accurate detection results for each core wire could not be obtained and were insufficient.

Furthermore, in multi-core cables, searching for terminal sets for each core wire at both ends is extremely complicated and requires a high degree of proficiency, so a simple and efficient terminal set detection method is desired.

The present invention was made under these circumstances, and it is easy to detect terminal set data for each core wire of a multicore cable, and it is easy to obtain accurate characteristic data for each core wire. The purpose of the present invention is to provide a multi-core cable test data creation device that can automatically obtain test data with a margin based on.

[Means for solving problems]

In order to solve such problems, the present invention has a configuration as shown in FIG. 1, which is a diagram corresponding to claims.

That is, the test signal output means 101 is a multi-core cable (sample cable) 1 having a plurality of core wires.
This is to switch the test signal to 00 and output it.

The terminal assembly detection means 102 detects the multicore cable 10
Corresponding terminal set data for each core wire at both ends of 0 is detected.

The recording means 103 records each terminal group data from the terminal group detecting means 102 as a heading item, and has a data recording area for each terminal group data.

The first time measuring means 104 measures each time from when the test signal is output to when each terminal set data is outputted, and stores the time in correspondence with each terminal set data in the data recording area of the recording means 103. Each measurement time is recorded.

The characteristic detection means 105 detects characteristic data for each terminal group based on the terminal group data of the recording means 103, and records each characteristic data in correspondence with each terminal group data in the data recording area of the recording means 103. It is something to do.

The second time measuring means 106 measures each time from when the test signal is output to when the characteristic data of each terminal group is output, and stores the data in the data recording area of the recording means 103 corresponding to each terminal group data. and record the measurement times.

The margin value setting means 111 sets margin values for at least one type of detection time, characteristic data, and characteristic data detection time corresponding to each terminal group data.

The test data creation means 112 is the recording means 10
The margin value from the margin value setting means 111 is added to the detection time of each terminal set data, the characteristic data, or the detection time of the characteristic data from 3 to output test data.

The test data recording means 113 records the test data from the test data creation means 112.

Further, the characteristic detecting means 105 is composed of an insulation characteristic detecting means 107 or a voltage withstanding characteristic detecting means 109, or an insulation characteristic detecting means 107 and a voltage withstanding characteristic detecting means 109, and the second time measuring means 106 is configured to detect each insulation characteristic. It is comprised of a time measuring means 108 until output and a time measuring means 110 until each breakdown voltage characteristic is output.

[Effect]

According to the present invention, the terminal set detection means 102 records each terminal set data of the multicore cable 100 in the recording means 103 as a heading item, and each time until each terminal set data is obtained is recorded as a first time. The measuring means 104 measures and records each terminal group data in the recording means 103, and the characteristic detecting means 105 detects each characteristic data for each core wire based on the terminal group data of the recording means 103, and records each terminal group data in the recording means 103. Each data is recorded in the recording means 103, and the second time measuring means 106 measures each time until each characteristic data is obtained.
Record within.

Furthermore, the test data creation means 112 adds the margin from the margin value setting means 111 to each characteristic data and each time data in the recording means 103 to create test data and records it in the test data recording means 113. .

〔Example〕

Examples of the present invention will be described below.

FIG. 2 is a block diagram showing an embodiment of the multi-core cable test data creation device according to the present invention.

First, before explaining the details of the present invention, an outline thereof will be explained.

In FIG. 2, a switching circuit 3 is connected to both ends of a multicore cable 1 having a plurality of core wires.
A continuity detection circuit 5, an insulation characteristic detection circuit 13, and a withstand voltage characteristic detection circuit 17 are connected to the switching circuit 3 in a switched manner.

The continuity detection circuit 5 includes the CPU 11 and the time measurement circuit 7, and the insulation characteristic detection circuit 13 includes the CPU 11.
and the time measurement circuit 15 is the withstand voltage characteristic detection circuit 1
7 is connected to a CPU 11 and a time measurement circuit 19, and these time measurement circuits 7, 15, 19
are each connected to the CPU 11.

Continuity detection circuit 5, insulation property detection circuit 13, withstand voltage property detection circuit 17, and time measurement circuits 15, 19
Both are controlled by a control circuit 9 controlled by the CPU 11, and are controlled so that data can be input from the CPU 11.

The CPU 11 includes a memory 21, an output terminal 23,
Printer 25a, CRT display 25b,
A test data creation circuit 27 is connected, a margin setting circuit 29 is connected to the test data creation circuit 27, and the margin setting circuit 29 and the CPU 1
A key input circuit 31 is connected to 1.

Next, details of the multi-core cable test data creation device according to the present invention will be explained.

The multicore cable 1 is for sample use, and for example, as shown in FIG.
b, a core wire 1c... having terminals T3, T53, and T54, each terminal T1 to T54...
... are the switch elements 3A to 3G of the switching circuit 3 consisting of a plurality of switch elements 3A to 3G...
is connected to the movable contact of the

Switch elements 3A to 3G of this switching circuit 3...
is formed of a relay circuit with 1 circuit and 3 contacts, for example, 192 switch elements 3A to 3G...
have. The three fixed contacts of each switch element 3A to 3G in the switching circuit 3 are connected to a continuity detection circuit 5, an insulation characteristic detection circuit 13, and a withstand voltage characteristic detection circuit 17, respectively, and are controlled by a control signal from a control circuit 9. Each terminal T1 to T5 of multi-core cable 1
4... is the continuity detection circuit 5 and the insulation characteristic detection circuit 1
3. It is designed to be switched and connected to the withstand voltage characteristic detection circuit 17.

The continuity detection circuit 5 shown in FIG. 2 includes 192 unit detection circuits 33 corresponding to the above-mentioned switch elements 3A to 3G. As shown in FIG. 4, this unit detection circuit 33 has a signal generation circuit 35 consisting of a TTL DC amplifier circuit that outputs a DC voltage of about 5V as a test signal, and a comparator connected in series with this signal generation circuit 35. Receiving circuit 37, signal generating circuit 35, and receiving circuit 37
The signal generating circuit 35 and the receiving circuit 37 can receive signals S ₁ and S ₂ for ON/OFF control. It's summery.

The input/output terminal 39 of each unit detection circuit 33 is connected to the fixed contact of each switch circuit 3A to 3G of the switching circuit 3, and the symbols D ₁ and D ₂ in the figure are protection diodes.

This unit detection circuit 33 includes a reception circuit 37 whose signal generation circuit 35 is turned on by control signals S ₁ and S ₂ .
When turned OFF, a 5V DC voltage is output as a test signal from the signal generation circuit 35 via the input/output terminal 39, and the terminals T1 to T of the multicore cable 1
54... can be applied.

On the other hand, the signal generation circuit 35 is turned off and the reception circuit 3
7 is turned ON, the input/output terminal 39
If the received signal from the receiving circuit 37 is at a predetermined level or higher, the receiving circuit 37 outputs the signal. That is, the unit detection circuit 33 functions as a test signal output circuit, and also functions as a signal detection circuit.

The continuity detection circuit 5 causes one of the unit detection circuits 33 to function as a test signal output circuit by the control circuit 9, causes the remaining unit detection circuits 33 to function as test signal detection circuits, and outputs a detection signal. The unit detection circuits 33 functioning as circuits and detection circuits are sequentially switched and controlled.

On the other hand, the CPU (central processing unit) 11 is an arithmetic unit,
It has an internal control device, an internal storage device, etc., and performs processing operations sequentially according to a predetermined program in the internal storage device or manual command input from the outside.
The core wire terminals connected to the unit detection circuits 33 that output test signals and the terminals connected to the unit detection circuits 33 to which the test signals are output are created as terminal group data.

For example, the control circuit 9 causes the unit detection circuit 33 connected to the terminal T1 of the multicore cable 1 via the switching circuit 3 to function as a test signal output circuit, while the unit detection circuit 33 connected to the remaining terminals T2 to T54 functions as a test signal output circuit. The detection circuit 33 is made to function as a detection circuit, and the CPU 11 detects the terminal T51 to which the signal is conducted, and creates the terminal T1 and the terminal T51 as terminal group data of the core wire 1a. Core wire 1b, core wire 1
The same applies to c...

In this way, the continuity detection circuit 5, the control circuit 9, and the CPU 11 detect which terminals of the core wires in the multicore cable 1 form a terminal group,
The CPU 11 is configured to record terminal set data in a data recording area A in the memory 21 as a heading item.

The memory 21 is an electronic recording medium whose writing and reading are controlled by the CPU 11, such as a general floppy disk or a built-in
It is a RAM type IC, and as shown in FIG. 5, predetermined data recording areas B, C, D, E, F, G, H, I, J...
have.

The time measurement circuit 7 is controlled by a control circuit 9 and is one unit detection circuit 33 in the continuity detection circuit 5.
After the test signal is output from the CPU, the time required to obtain each terminal set data is measured.
11, and the CPU 11 has a function of recording each of these time data in the data recording area B for each terminal group data in the memory 21.

As shown in FIG. 6, the insulation characteristic measurement circuit 13 includes a DC signal generator 41 that outputs a DC voltage of about 500 V as a test signal, and a DC signal generator 41 that outputs a DC voltage of about 500 V as a test signal, and a DC current obtained from the multicore cable 1 in response to the application of the test signal. An insulation characteristic data output section 43 outputs the insulation resistance value obtained by voltage conversion and A/D conversion to the CPU 11 and the time measurement circuit 15, and one switch of the switching circuit 3 based on the terminal set data of the memory 21. A DC voltage is applied to one of the fixed contacts in the elements 3a to 3G..., and the other switch elements 3A to 3
It consists of a switching section 45 that commonly connects the fixed contacts of G... and connects it to an insulation characteristic data output section 43.

In addition, the terminal set data of memory 21 is
Needless to say, the signal is input to the switching unit 45 by 1.

This insulation characteristic measuring circuit 13 applies a DC voltage of 500 V to one of the core wires of the multicore cable 1 from the DC signal generator 41, connects the remaining core wires in common, and leakage current flowing through the commonly connected core wires. is applied to the insulation characteristic data output section 43 to detect the insulation resistance value, and output the insulation resistance value to the CPU 11 for each core wire 1a, 1b, 1c, . . . .

The time measurement circuit 15 has a function of measuring each time from outputting a DC voltage until obtaining a stable leakage current and outputting it to the CPU 11.
11 has a function of recording the insulation resistance value and measurement time for each terminal group data in data recording areas D and E (see FIG. 5) of the memory 21.

As shown in FIG. 7, the withstand voltage characteristic measuring circuit 17 includes an AC signal generating section 47 that outputs an AC current of about 500 V as a test signal, and an AC current obtained from the multicore cable 1 by applying the test signal. The leakage current value obtained by A/D converting the
and a withstand voltage characteristic data output unit 49 that outputs to the time measurement circuit 15, and a fixed contact of one switch element 3A to 3G of the switching circuit 3 based on the terminal set data in the memory 21 input by the CPU 11. It consists of a switching section 51 that applies an alternating current to one switch element, commonly connects the fixed contacts of the other switch elements 3A to 3G, and outputs the data to the withstand voltage characteristic data output section 43.

The withstand voltage characteristic measuring circuit 17 causes an AC current of 500 V to flow from the AC signal generator 47 to one of the core wires of the multicore cable 1, and outputs a leakage current flowing through the remaining commonly connected core wires to the withstand voltage characteristic data output section 49. In addition, the leakage current value is detected, and each core wire 1a, 1b, 1c
...is output as the withstand voltage characteristics for each time.

The time measurement circuit 19 includes each core wire 1a, 1b, 1c.
……Measure each time from outputting alternating current until stable leakage current is obtained, and
11, and the CPU 11 has a function of recording these voltage resistance characteristic values and measurement times in the data recording areas H and I of the memory 21 (see FIG. 5) for each terminal set data.

The margin measurement circuit 29 measures the detection time, insulation resistance value, and the terminal set data recorded in the memory 21.
It has a function to set a margin for each of the insulation resistance measurement time and withstand voltage characteristics, and the test data creation circuit 27 adds the margin from the margin setting circuit 29 to each data in the memory 21 and creates each test data. It has the ability to create. This margin is determined by taking into account variations in the characteristics of the multicore cable 1 to be inspected. The CPU 11 outputs the data recorded in the memory 21 to the test data creation circuit 27, The test data created in the above is recorded again in the data recording areas C, F, G, and J (see FIG. 5) of the memory 21.

Note that the setting value in the margin setting circuit 29 is as follows:
One or more of the terminal set data detection time, insulation resistance value, insulation resistance measurement time, and withstand voltage characteristics can be set arbitrarily, and can also be set externally using the key input circuit 31, and the key input circuit 31 directly connects the CPU 11. It is also becoming controllable.

Furthermore, the CPU 11 transmits the detected data in the memory 21 and the created test data to the output terminal 23.
You can output it at any time from the printer 25a or
It is customized so that it can be output to a CRT display 25b.

Note that the operations of the components centered on the CPU 11 described above will be further clarified by the operation explanation based on the following flowchart.

Next, the operation of the multi-core cable test data creation device of the present invention configured as described above will be explained using the flowchart shown in FIG.

The program starts and the CPU 11 and other components start operating. In step 200, the sample multicore cable 1 is connected to the switching circuit 3, and in step 201, terminal set data and required time are obtained from the continuity detection circuit 5 and time measurement circuit 7. The set data and the required time are recorded in data recording areas A and B in the memory 21 as shown in FIG. 9.

In step 203, it is determined whether there are any unmeasured parts of the multicore cable 1, and if YES, the process returns to step 201 and the same operation is repeated.

After all terminals have been inspected, step 203 is completed.
If the result is NO, in step 204, the insulation characteristic test terminals of the multicore cable 1 are determined based on the terminal set data recorded in the memory 21, and in step 205, the insulation characteristic detection circuit 13 and the time measurement circuit are determined. The insulation resistance value and the required time for detection are obtained from step 15, and in step 206, the insulation resistance value and the required time for measurement are recorded in the data recording areas D and E of the memory 21 as shown in FIG.

Next, in step 207, it is determined whether there are any unmeasured locations, and if YES, the process returns to step 204 and the same operation is repeated.

If step 207 becomes NO, step 208 determines the voltage resistance characteristic test terminal of multicore cable 1 based on the terminal set data recorded in memory 21, and step 209 determines voltage resistance characteristic detection circuit 13.
The leakage current value and detection time are obtained from the time measurement circuit 19. In step 210, the leakage current value and the required measurement time are recorded in the data recording areas H and I of the memory 21 as shown in FIG. 9.

Then, in step 211, it is determined whether there are any unmeasured parts, and if YES, the process returns to step 208 and the same operation is repeated.

If step 211 is NO, step 212 adds a margin to the time required to obtain the terminal set data in memory 21 to create test data, and step 213 creates the insulation resistance value in memory 21 and the required measurement time. Create test data by adding margin to time.

Furthermore, in step 214, a margin is added to the leakage current value to create test data, and in step 215, test data is created.
Then, these test data are stored in the data recording areas C, F, G, and J of the memory 21 as shown in FIG. 9, 4 to 6.
Record it as test data and finish.

In FIG. 9, for convenience, each test data is shown individually according to its production order, but the recording state is recorded in a format as shown in FIG.

When step 211 is completed, the various data recorded in the memory 21 can be printed out in step 216, for example, via the printer 25a.
Furthermore, although not shown in the diagram, various data can be displayed on the CRT at any time.
It can be displayed on the display 25b.

In a cable tester using the multi-core cable test data creation device of the present invention, for example,
In a cable under test of the same type as the sample multicore cable 1 described above, a DC voltage is applied as an insulation test signal in accordance with the test time data stored in the data recording area G of the memory 21, and the obtained insulation resistance value is It is inspected whether the insulation resistance value in the data recording area F is within the range, and an alternating current is applied according to the test time data in the data recording area I in the memory 21, and the obtained value is the data. Recording area J
It is checked whether the value within is exceeded.

〔Effect of the invention〕

As explained above, the multi-core cable test data creation device of the present invention can conduct continuity tests for each core wire of a multi-core cable and acquire terminal set data in the minimum necessary time, and can accurately identify the continuity test for each core wire. It has the advantage that it is possible to test and detect highly accurate insulation and voltage resistance characteristic data in a short time, and that test data for each core wire with a margin added can be easily obtained from the obtained characteristic data.

Therefore, when the multi-core cable test data creation device of the present invention is used in a cable tester, the test efficiency will be extremely high.

[Brief explanation of the drawing]

FIG. 1 is a claim correspondence diagram showing the configuration of a multi-core cable testing data generating device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the multi-core cable testing data generating device according to the present invention, and FIG. The figure shows the multicore cable and switching circuit shown in Fig. 2, Fig. 4 is a circuit diagram showing the unit detection circuit that constitutes the continuity detection circuit shown in Fig. 2, and Fig. 5 shows the circuit diagram in the memory shown in Fig. 2. Figures 6 and 7 are diagrams explaining the recording area.
8 is a flowchart showing the operating procedure of the present invention, and FIG. 9 is a recording state in the memory that changes according to the operation shown in FIG. 8. FIG. 1...Multi-core cable, 3...Switching circuit, 5...
Continuity detection circuit, 7...Time measurement circuit, 9...Control circuit, 11...CPU, 13...Insulation property detection circuit, 15, 19...Time measurement circuit, 17...Withstand voltage property detection circuit, 21... Memory, 27... Test data creation circuit, 29... Margin setting circuit, 3
3... Unit detection circuit, 41... DC signal generation section,
43... Insulation property data output section, 45, 51...
Switching unit, 47...AC signal generation unit, 49...Voltage characteristic data output unit, 100...Multi-core cable, 1
01... Test signal output means, 102... Terminal assembly detection means, 103... Recording means, 104... First time measuring means, 105... Characteristic detection means, 106
... Second time measuring means, 107 ... Insulation property detecting means, 108, 110 ... Time measuring means, 10
9... Voltage characteristic detection means, 111... Margin value setting means, 112... Test data creation means, 113
...Test data recording means.

Claims (1)

[Scope of Claims] 1. Test signal output means for switching and outputting a test signal to a multi-core cable having a plurality of core wires; and terminal set detection means for detecting terminal set data for each of the core wires at both ends of the multi-core cable. and recording means for recording each of the terminal set data from the terminal set detection means as a heading item and having a data recording area for each of these terminal set data; A first method for measuring each time until each terminal group data is output from the test signal output means and recording the measured times in the data recording area of the recording means in correspondence with each terminal group data. time measuring means; detecting characteristic data for each terminal group based on the terminal group data of the recording means; and storing each characteristic data in correspondence with the terminal group data in the data recording area of the recording means; characteristic detecting means for recording the data recording area of the recording means; measuring each time from when the test signal is output from the test signal output means until each of the characteristic data is output from the characteristic detecting means; a second time measuring means for recording measurement times corresponding to each of the terminal set data; and at least one of the detection time of each of the terminal set data, each of the characteristic data, and the detection time of each of the characteristic data. A margin value setting means for setting a margin value; and a test by adding the margin value from the margin value setting means to the detection time of each terminal set data from the recording means, the detection time of each characteristic data or each characteristic data. 1. A multicore cable test data creation device, comprising: test data creation means for outputting test data; 2. Multicore cable test data according to claim 1, wherein the characteristic detecting means is an insulation characteristic detecting means, and the second time measuring means is a time measuring means until each insulation characteristic is output. Creation device. 3. The multi-core cable test data according to claim 1, wherein the characteristic detecting means is a withstand voltage characteristic detecting means, and the second time measuring means is a time measuring means until each withstand voltage characteristic is output. Creation device. 4. The characteristic detecting means includes an insulation characteristic detecting means and a withstand voltage characteristic detecting means, and the second time measuring means measures a time until each insulation characteristic is output and a time until each withstand voltage characteristic is output. A multi-core cable test data creation device according to claim 1, which is a means.