JPH0556871B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device used as a light receiving section of a switching device.

[Background technology]

2. Description of the Related Art A switching device having a circuit configuration shown in FIG. 2 is used as a switching device that performs switching by inputting a signal to an input terminal to operate a switching element in a circuit. This one has input terminal 38,
38, input a signal to this input terminal 38, 38.
The light emitting element 39 connected to the light emitting element 39 is caused to emit light, and the light is received by the photoelectric conversion element _D1 . The photoelectric conversion element D ₁ that receives the light converts the light into an electrical signal and converts it into a field effect transistor (hereinafter referred to as "FET") T ₁
FETT ₁ performs switching between output terminals 40 and 40 according to the electrical signal. As described above, in the switching device shown in FIG. 2, signals are exchanged between the input terminals 38, 38 and the output terminals 40, 40 by light, so there is no electrical connection between the two terminals. It is often used when it is necessary to be insulated (no common return wire).

Conventionally, in such a switching device, the light emitting element 39, the photoelectric conversion element _D1 , and the FETT ₁ are formed on separate semiconductor substrates, and the photoelectric conversion element _D1 and the FETT ₁ are connected by wire bonding, etc. It was supposed to be connected by wires. For this reason,
In manufacturing such a switching device, a large number of steps and parts are required for assembly, insufficient reliability is obtained, and the cost is high.

Also, in the case of FET, as mentioned above, FETT ₁
However, if it is formed singly on an independent semiconductor substrate, there is a risk that the insulated gate of FETT ₁ will suffer dielectric breakdown due to static electricity or the like during the period from cutting out the semiconductor substrate to bonding. For this reason, it is necessary to take measures against dielectric breakdown such as grounding for the semiconductor substrate on which FETT ₁ is mounted.
It was inconvenient to handle.

In order to solve the above problems, it is conceivable to integrate FETT ₁ and photoelectric conversion element D ₁ on the same semiconductor substrate. However, in a double-diffused FET that uses the semiconductor substrate itself as the drain region of the FET, it is virtually impossible to form another element, a photoelectric conversion element, on the semiconductor substrate.

Furthermore, even in the case of a FET that does not use the semiconductor substrate itself as the drain region of the FET, if photoelectric conversion elements are simply formed side by side on the same substrate, the output voltage will drop due to leakage current.
A practical switching device cannot be obtained.

Therefore, it is conceivable to arrange each of the above-mentioned elements separately on each isolation island of a dielectric isolation substrate (DI substrate), but this method has poor productivity and also
Because it is expensive, it has not been put into practical use.

[Purpose of the Invention] Therefore, the inventors have provided a useful semiconductor device that does not require a large number of steps or parts for assembly, has sufficient reliability, can reduce costs, and is highly practical. The purpose is to

[Disclosure of the invention]

In order to achieve the above object, the inventors conducted studies from various angles, and found that at least a photoelectric conversion element array is inserted between the gate and source of a field effect transistor, and serves as a light receiving section of a switching device. A semiconductor device was considered in which the photoelectric conversion element array is formed on a semiconductor substrate on which the field effect transistors are formed, with an insulating layer interposed therebetween.

The semiconductor device devised by the inventors will be explained with reference to FIG. 1 which specifically shows it.

A P layer 2 which is a P type (second conductivity type) impurity region is formed on the surface of the high resistance region 1b side of the semiconductor substrate 1 having an N type (first conductivity type) low resistance region 1a and a high resistance region 1b. ... are formed spaced apart from each other. Further, two N ⁺ layers 3, which are N type impurity regions, are formed on the surface of each P layer 2, spaced apart from each other. On the surface of the semiconductor substrate 1 on which each of the impurity regions is formed, an electrode 5 made of PolySi or the like is provided so as to connect each of the P layers 2 through an insulating film 4a. There is. Then, this electrode 5 is an insulated gate,
A plurality of double diffused FETs (DMOSFETs) T _{1 .} . . are formed using the N ⁺ layer 3 as a source and the N type semiconductor substrate 1 around each P layer 2 as a drain.
In such a double diffusion type FET, the channel length is the thickness of the P layer 2 sandwiched between the N type semiconductor substrate 1 and the N ⁺ layer 3, that is, the thickness of the P layer 2 to the semiconductor substrate 1. Since it is defined by the diffusion state of the N + layer 2 and the N ⁺ layer 3, it can be shortened without using photolithography technology, and high durability and high speed characteristics can be achieved.

An insulating film 4b that also serves as a protective film is provided on the upper surface of each electrode 5.
is formed, and a conductive thin film 6 of Al or the like is formed thereon between each FETT ₁ . As shown in the figure, this conductive thin film 6 consists of each N ⁺ layer 3...
... and each P layer (base) 2..., and is used as a source electrode. On the other hand, each electrode 5... is connected at a place not shown, and the drain of each FETT ₁ ... is a part of one semiconductor substrate 1 as described above, so this is also electrically connected. It is connected.
Therefore, each FETT ₁ ... is connected in parallel.

As described above, FETT _{1 .} . . is formed on the surface of the connected semiconductor substrate ₁ .
An insulating layer 7 is formed to cover.

This device is constructed by forming on this insulating layer 7 a photoelectric conversion element array in which a plurality of photoelectric conversion elements _D1 ... are connected in series.

The photoelectric conversion element _D1 has a structure as shown in the figure. That is, as many conductive thin films (Ni--Cr, etc.) 8 are formed on the insulating layer 7 as the number of photoelectric conversion elements _D1 necessary for the photoelectric conversion element array. Each conductive thin film 8... has a P layer 9, an I layer 10, and an N layer made of amorphous silicon, respectively.
Layers 11 are laminated in this order, and a transparent conductive film 12 such as In ₂ O ₃ is further provided thereon.
Each of the above layers constitutes a PIN layer photoelectric conversion element (amorphous silicon photodiode) _D1 .

As shown in the figure, the transparent conductive film 12 is in contact with the conductive thin film 8 of the adjacent photoelectric conversion element _D1 ,
As a result, a plurality of photoelectric conversion elements _D1 ... are connected in series in the same direction, forming a photoelectric conversion element array. As shown in the figure, the conductive thin film 8 of the photoelectric conversion element on the left side, which is one end of this photoelectric conversion element array, is
It is connected to the gate 5 of FETT ₁ via a conductive layer 6'. The conductive layer 6' is formed at the same time as the conductive thin film 6.
It is formed so as not to be connected to this conductive thin film 6. The transparent conductive film 12 of the right photoelectric conversion element _D1 , which is the other end of the photoelectric conversion element array, is connected to each FETT ₁ ... It is connected to a conductive thin film 6 which is a source electrode. As a result, the photoelectric conversion element array
It is inserted between the gate and source of the FET, forming a circuit that is almost equivalent to the right circuit (light receiving section) of the switching device shown in Figure 2, although the number of elements is different. As described above, an insulating protective film 13 can be further formed on the surface of the semiconductor substrate on which the FET and the photoelectric conversion element array are integrated, if necessary, as in the device shown in the figure.
In the figure, reference numeral 14 denotes a guard ring obtained by diffusing an impurity of a conductivity type different from that of the substrate (in this case P ⁺ type) in a shape surrounding the above elements, and is not necessarily used in this invention. Although it is not necessary, by doing so, it is possible to improve the dielectric strength of the double-diffused FET as in this case and achieve a high withstand voltage.

In the above case (of course, in this invention), the substrate is N
type, the first conductivity type was N type and the second conductivity type was P type. However, if the substrate is P type, the first
The conductivity type is P type and the second conductivity type is N type.
Needless to say.

In the case of the semiconductor device shown in FIG. 1, the photoelectric conversion element array is formed on the semiconductor substrate 1 with the insulating layer 7 in between, so this photoelectric conversion element array is of a double diffusion type. FETT ₁ ... is completely electrically isolated except for the output terminals at both ends. For this reason, the double-diffusion type
As described above, it becomes possible to form the FET and the photoelectric conversion element array on the same substrate.

The semiconductor device in Figure 1 does not require a DI board,
It is integrated, does not require many processes or parts for assembly, and is reliable.
Although it is highly practical because it reduces costs and suppresses output leakage from the photoelectric conversion element array, the operation stability and speed of the FET, which is a switching element, are not sufficient.

Therefore, the inventors conducted further studies and determined that the operation stability and speed of the FET, which is a switching element, would be sufficient without impairing the reliability, cost reduction, and suppression of output leakage of the photoelectric conversion element array. This led to the development of a useful semiconductor material that can be used as a light receiving section in a certain switching device.

That is, in order to achieve the above object, a first invention provides a semiconductor device that serves as a light receiving section of a switching device, in which at least a first photoelectric conversion element array is inserted between the gate and source of a field effect transistor. It also includes a normally on transistor connected in parallel with the first photoelectric conversion element array, and a second photoelectric conversion element array inserted between the gate and source of this normally on transistor. The normally-on transistor is formed on the same semiconductor substrate as the field effect transistor, and the first and second photoelectric conversion element arrays are formed on an insulating layer formed on the semiconductor substrate. The gist is a semiconductor device characterized by
In the second invention, the first photoelectric conversion element array and the normally-on transistor are connected in parallel, and the second photoelectric conversion element array is connected between the gate and source of the normally-on transistor. and a resistive element for discharging the accumulated charge of the normally-on transistor are connected in parallel, and the semiconductor device is inserted between the gate and source of the field effect transistor and serves as a light receiving section of the switching device. The present invention provides a semiconductor device, wherein the first and second photoelectric conversion element arrays are formed on a semiconductor substrate on which at least the normally-on transistors are formed, with an insulating layer interposed therebetween. shall be.

Hereinafter, these inventions will be described in detail with reference to drawings showing embodiments thereof.

First, the embodiment of the first invention is shown in FIGS. 3 and 4.
This will be explained based on the diagram. In FIG. 4, the actual portion represents the equivalent circuit of this embodiment.

That is, this example has two FETT ₂ , T ₂
A first photoelectric conversion element array DA ₁ is inserted between the common gate and source of the first photoelectric conversion element array DA 1.
normally connected in parallel with the photoelectric conversion element array DA ₁ .
An on transistor _T3 is connected, and a second photoelectric conversion element array _DA2 is inserted between the gate and source of this normally on transistor _T3 . In such a circuit, the normally-on transistor T ₃ is in an open state when light is irradiated and is in a short-circuited state when light is interrupted, so that the charge remaining in the first photoelectric conversion element array DA ₁ is quickly discharged even after light is interrupted. This makes it possible to quickly shut off the two FETT ₂ and T ₂ after the light is shut off. Furthermore, it is also possible to prevent FETT ₂ and T ₂ from being neither on nor off when light irradiation is insufficient. The normally-on transistor allows the FET, which is a switching element, to operate quickly and stably.

The specific structure of this embodiment is as shown in FIG. That is, on the surface of a P-type (first conductivity type) semiconductor substrate 21, three N ⁺ layers 22, 23, 23, which are N-type (second conductivity type) impurity regions, are formed spaced apart from each other. . two N ⁺ layers 23,
23 is located to sandwich the N ⁺ layer 22,
On top of that, two electrodes 25, 2 made of polySi or the like are placed at a position connecting the two N ⁺ layers 23, 23 and the N ⁺ layer 22, with insulating films 24, 24 interposed therebetween.
5 is provided. Note that these two electrodes 2
5 and 25 are connected to each other at positions not shown in the figure, as shown by broken lines in the figure. Then, the N ⁺ layer 22 is a common source, and the two N ⁺ layers 2
3 and 23 as independent drains, and the two electrodes 25 and 25 as gates, the two electrodes mentioned above are connected.
FETT ₂ and T ₂ are formed as normal MOS type. In the figure, O ₁ and O ₂ each have an output terminal connected to the drain, and by doing so, signals of different polarities can be processed simultaneously.

An insulating tank 26 that also serves as a protective film is further formed over the entire surface of the semiconductor substrate 21 above the two FET ₂ and T ₂ . And this insulation tank 26
A first photoelectric conversion element array DA ₁ is formed thereon, and a normally-on transistor is further formed on the first photoelectric conversion element array DA 1.
T ₃ is formed on the same substrate as the two FETT ₂ and T ₂ , and the second photoelectric conversion element array DA ₂ is also formed on the insulating layer 26 . By doing this, the first photoelectric conversion element array
Since it is possible to eliminate leakage current flowing from not only DA ₁ but also the second photoelectric conversion element array DA ₂ to the semiconductor substrate, it is possible to obtain a switching device with more reliable operation and higher reliability. It is.

The normally-on transistor _T3 mentioned above
is constructed as follows. That is, on the surface of the semiconductor substrate 21, two N ⁺ layers 27, 28 are formed at a position slightly apart from the N ⁺ layers ₂₂ , 23, 23 that constitute the previous two FETT 2, T ₂ . It is formed. On the surface of the semiconductor substrate 21,
An electrode 30 made of polySi or the like is formed at a position connecting the two N ⁺ layers 27 and 28 with an insulating film 29 interposed therebetween. Then, this electrode 30 is used as a gate, the N ⁺ layer 27 is used as a source, and the N ⁺ layer 28 is used as a gate.
A MOS type FET is formed with N ⁺ layer 2 as the drain, as shown in the figure.
An N channel 31 is formed between 7 and the N ⁺ layer 28, thereby making this FET an N channel,
It becomes a depletion MOSFET, that is, a normally-on transistor _T3 . And this normally on transistor _T3
Needless to say, an insulating layer 26 which also serves as a protective film is formed on top of the insulating layer 26.

The N ⁺ layer 27 which is the source of the normally-on transistor T ₃ formed in this way is the N ⁺ layer 2 which is the common source of the previous two FETT ₂ and T ₂ .
2 and the N ⁺ layer 28 which is the drain are
They are connected to electrodes 25, which are the gates of FETT ₂ and T ₂ , respectively, as shown by broken lines in the figure.

first and second photoelectric conversion element arrays DA ₁ ,
Each of the photoelectric conversion elements D ₂ and D ₃ constituting DA ₂ is configured as follows. On the surface of the insulation layer 26, as many photoelectric conversion elements D ₂ and D ₃ (in this case two each) as necessary to constitute the first and second photoelectric conversion element arrays DA ₁ and DA ₂ are placed. P-type (first conductivity type) Si single crystal thin film 32, 33, 3
3 is formed. In this way, Si
The method for forming the single crystal thin films 32 and 33 is as follows:
For example, there is the so-called laser melting crystallization method, in which a polycrystalline or amorphous thin film of Si is formed in advance, irradiated with a laser to melt it, and cooled to form a single crystal. It is also possible to use a method. Each P-type Si single crystal thin film 32 formed as described above,
N layers 32a, 32a are formed on the surface of the Si single crystal thin films 32, 32 by diffusing N type (second conductivity) impurities, and the P layer 32, which is the remaining portion of the Si single crystal thin films 32, 32, is
PN between b, 32b and this N layer 32a, 32a
Photoelectric conversion elements D ₂ and D ₂ are formed by bonding. Between the two photoelectric conversion elements D ₂ , D ₂ , a conductive film 34 a is formed that connects the N layer 32 a of the left photoelectric conversion element D ₂ and the P layer 32 b of the right photoelectric conversion element D ₂ . As a result, the two photoelectric conversion elements D ₂ and D ₂ are connected in series to form the first photoelectric conversion element array DA ₁ .
The P layer 32b of the left photoelectric conversion element _D2 , which is one end of the first photoelectric conversion element array _DA1 , is connected to the electrode 25, which is the gate of the FETT ₂ , by a conductive thin film 34b. The N layer 32a of the photoelectric conversion element D ₂ on the right side, which is the other end, is connected to the N layer 32a of the photoelectric conversion element D 2 on the right side through the conductive thin film 34c.
It is connected to the N ⁺ layer 22 which becomes the source of FETTT ₂ and T ₂ . As a result, the first photoelectric conversion element array DA ₁ is inserted between the gates and sources of the two FETTs ₂ and T ₂ in parallel with the normally-on transistor T ₃ . .
In addition, in the figure, 36 and 36 are insulating protective films.

On the other hand, also on the surface of each Si single crystal thin film 33, 33,
Similarly, by diffusing N-type impurities, N layers 33a, 33
a is formed, and the remaining part is the P layer 3.
3b, 33b and this N layer 33a, 33a.
Photoelectric conversion elements D ₃ and D ₃ are formed by PN junction. In addition, in the figure, 37 and 37 are insulating protective films similar to the previous 36. These two photoelectric conversion elements D ₃ , D ₃ are also connected in series by the conductive thin film 35a, similar to the previous photoelectric conversion elements D ₂ , D ₂ , and thereby the second photoelectric conversion element array
DA ₂ is formed. The N layer 33a of the left photoelectric conversion element _D3 , which is one end of the second photoelectric conversion element array _DA2 , is connected to the electrode 30, which is the gate of the normally-on transistor _T3 , via the conductive thin film 35b. The P layer 33b of the photoelectric conversion element D ₂ on the right side, which is the other end, is connected to _the ^N It is connected to layer 28. As a result, the second photoelectric conversion element array DA ₂
is inserted between the gate and source of the normally-on transistor _T3 , and with the above configuration,
The equivalent circuit shown in FIG. 4 is thus formed. In this embodiment as well, if the conductivity type of the substrate is reversed, the P-type and N-type layers are reversed, as in the case of other devices.

Next, the second invention will be explained based on examples.

This second invention is a portion surrounded by a dashed line in FIG. 5a, and is used by being inserted between the gate and source of the FETT ₄ as shown in the figure. As the resistive element R, in this example, as shown in the figure, the channel resistance (pinch-off resistance) of FET is used, but this is a thin film using diffused resistance, polycrystalline silicon, amorphous silicon, etc. It may be a resistor or other resistive element (high resistance) normally used in semiconductor devices, such as a pinch resistor. In this embodiment, a junction FET (hereinafter referred to as "JFET") is used as the resistive element R and the normally-on transistor _T5 . It is also less susceptible to damage during formation of the conversion element array.

In the above circuit, when the light shielding is cut off, the charges remaining on the normally-on transistor _T5 and the second photoelectric conversion element array _DA4 can be quickly discharged by the resistive element R. ,
Since the normally-on transistor T ₅ can be quickly shorted, FETT ₄ can be shorted even more quickly than in the embodiment shown in FIG.
This makes it possible to block out

The specific structure of the embodiment shown in FIG. 5a is as shown in FIG. That is, on the surface of a P-type (first conductivity type) semiconductor substrate 51, N layers 52 and 53, which are N-type (second conductivity type) impurity regions, are formed spaced apart from each other. On the surface of the N layer 52,
A P ⁺ layer 54 is formed, sandwiching this P ⁺ layer 54 and not contacting this P ⁺ layer 54.
Two N ⁺ layers 55 and 56 are formed. The P ⁺ layer 54 is formed on the semiconductor substrate 51 as shown by the broken line in the figure.
This connects the semiconductor substrate 51 to
and the P ⁺ layer 54 are at the same potential. and,
The P ⁺ layer 54 and the semiconductor substrate 51, which are at the same potential, are used as a gate, the N layer 52 sandwiched between them is used as a channel, the N ⁺ layer 55 is used as a drain, and the N ⁺ layer 56 is used as a source to form a JFET. - An on transistor _T5 is formed.
On the other hand, the surface of the N layer 53 also has one P ⁺ layer 57 and two N ⁺ layers 58 and 59, similar to the previous N layer 52.
is formed. Then, as with the normally-on transistor _T5 , P ⁺ 57 and the semiconductor substrate 51 are used as the gate, and N is sandwiched between the two.
A JFET is formed by using the layer 53 as a channel, the N ⁺ layer 58 as a drain, and the N ⁺ layer 59 as a source. The resistive element R mentioned above is formed by being connected as shown in FIG.

In this way, on the surface of the semiconductor substrate 51 on which the normally-on transistor T ₅ and the resistance element R are formed, an insulating layer 61 is further formed over the entire surface of the semiconductor substrate 51 . Then, on this insulating layer 61, a second and a second
This embodiment is configured by forming two photoelectric conversion element arrays DA ₃ and DA ₄ . In this embodiment, the photoelectric conversion elements used to construct the two photoelectric conversion element arrays DA ₃ and DA ₄ are of the PIN type, as shown in the figure.
That is, as many conductive thin films 6 as the number of photoelectric conversion elements necessary for the photoelectric conversion element array are provided on the insulating layer 61.
2... are formed, and furthermore, an N layer 63 and an I layer are formed thereon.
A layer 64 and a P layer 65 are laminated, and finally a transparent conductive film 66 is provided thereon, and one end of this transparent conductive film 66 is in contact with the conductive thin film 62 of the adjacent photoelectric conversion element, Due to this, each photoelectric conversion element is connected in series. Each layer forming such a photoelectric conversion element may be made of amorphous silicon as in the case of FIG. 1, or may be made of Si single crystal formed by a laser melting crystal method as in the previous embodiment It doesn't matter if it is. Further, in this embodiment, the insulating layer 6 which is underground
As mentioned earlier, the normally-on FETT ₅ and the resistive element R, which are formed further below 1,
Since the photoelectric conversion element is not susceptible to damage, it is also possible to form the photoelectric conversion element by other methods instead of the above two methods.

Of the two photoelectric conversion element arrays as described above, in the second photoelectric conversion element array DA ₄ , the transparent conductive film 66 of the leftmost photoelectric conversion element at one end is as shown in the figure. It is connected to an N ⁺ layer 56, which is the source of the normally-on transistor _T5 , and an N ⁺ layer 58, which is the drain of the resistive element R. As shown in the figure, the conductive thin film 62 of the photoelectric conversion element on the right side, which is the other end, is connected to the P ⁺ layer 54, which is the gate of the normally-on transistor _T5 , and the gate and source of the resistive element R. The second photoelectric conversion element array DA ₄ , the normally-on transistor T ₅ and the resistive Element R
It consists of parts. And after this,
By connecting the above parts to the first photoelectric conversion element array DA ₃ and FETT ₄ , the circuit shown in FIG. 5a is completed. As described above, the surface of the semiconductor substrate on which the normally-on transistor T ₅ , the first and second photoelectric conversion element arrays DA ₃ and DA ₄ , and the resistive element R are integrated is further coated as necessary. Then, as shown in the figure, the insulating protective film 6
8 can also be formed.

In the above example, since the substrate was P type,
The first conductivity type was P type and the second conductivity type was N type, but if the substrate is N type, the first conductivity type is N type and the second conductivity type is P type. Not even.
In that case, normally on transistor
_T5 and resistive element R are N-
P-channel instead of JFET channel
Becomes JFET. And, such a P channel
When using a JFET, the circuit shown in Figure 5a when using an N-channel JFET can be obtained by connecting each element so that the equivalent circuit is as shown in Figure 5b. That is, it can function similarly to this embodiment.

Next, the embodiment shown in FIG. 7 will be described. The basic configuration of this embodiment is almost the same as that of the previous embodiment shown in FIG. That is, two JFETs, which are a normally-on transistor _T5 and a resistive element R, are formed on a semiconductor substrate.
Two photoelectric conversion element arrays DA ₃ and DA ₄ are integrated thereon via an insulating layer 61, and each element is connected. Therefore, if this embodiment is expressed as an equivalent circuit, it will be the circuit shown in FIG. 5a. This embodiment differs from the embodiment shown in FIG. 6 in the structure of the normally-on transistor _T5 and the JFET serving as the resistive element R.

That is, in the embodiment shown in FIG. 6, such a JFET has an N layer 5 on a P type semiconductor substrate 51.
In this embodiment, the JFET ^channel region is epitaxially It is formed by growth. The reason why the channel region is formed by epitaxial growth is that the impurity concentration, which is difficult to control by double diffusion, can be easily controlled by epitaxial growth.
This is because it becomes possible to set the pinch-off voltage of the JFET to a desired value. Formation of the channel region by such epitaxial growth is performed, for example, as follows.

First, a P-type (first conductivity type) semiconductor layer 51' is prepared. Next, on this semiconductor layer 51',
N type (second conductivity type) by epitaxial growth
forming an epitaxial growth layer. Then, a P-type impurity is diffused into this epitaxial growth layer.
By forming the P ⁺ layer 69..., the epitaxial growth layer becomes a plurality of N layers 52', 53'...
It is separated into two parts.

In this way, the dispersed N layer 52',
As mentioned above, the parts other than 53' are
This is almost the same as the embodiment shown in the figure. That is, N layer 5
One P ⁺ layer 54 and two N ⁺ layers 55, 56 are formed at a distance from each other on the surface of T 2', thereby forming a normally-on transistor T _{5 .}
is being formed. Similarly, on the surface of the N layer 53',
One P ⁺ layer 57 and two N ⁺ layers 58 and 59 are formed spaced apart from each other, and the P ⁺ layer 57 and
A resistive element R using channel resistance is formed by connecting the N ⁺ layer 59 with an electrode 60. Then, first and second photoelectric conversion related element arrays DA ₃ and DA ₄ are formed thereon via an insulator 61, and on each of these elements and another semiconductor substrate not shown in the figure. Been formed
FETT ₄ is connected to form the circuit shown in FIG. 5a.

In this embodiment as well, an insulating protective film 68 may be provided on the surface of the semiconductor substrate as in the embodiment shown in FIG. Also in this embodiment, if the conductivity type of the substrate is reversed, the P-type and N-type layers are reversed, as in the embodiment shown in FIG. In that case, as in the previous embodiment, each element may be connected so as to be equivalent to the circuit shown in FIG. 5b.

Next, the embodiment shown in FIG. 8 will be explained. In this example, since the normally-on transistor _T5 and the JFET acting as the resistive element R are of P-channel type, the circuit enclosed by the chain line in FIG. 5b is used instead of the circuit in FIG. 5a. This circuit is equivalent to that of the above circuit, but the other configurations are almost the same as those of the previous two embodiments. That is, first and second photoelectric conversion element arrays DA ₃ and DA ₄ are formed on a semiconductor substrate on which a normally-on transistor T ₅ and a resistive element R are formed, with an insulating layer 61 interposed therebetween. It is what it is. Therefore, only the differences from the previous two embodiments will be explained below.

An N-type (second conductivity type) epitaxial growth layer is formed on the P-type (first conductivity type) semiconductor layer 51', which forms a P ⁺ layer 69 which is a P-type impurity region...
A plurality of N layers 52' separated into islands by
53',... P on the surface of the N layer 52'
A layer 70 is formed, and on the surface of this P layer 70, one N ⁺ layer 71 and two P ⁺ layers 7 are further formed.
2 and 73 are formed spaced apart from each other. An N ⁺ layer 74 is formed on the surface of the N layer 52' outside the P layer 70 so as not to come into contact with the P layer 70.
Then, as shown by the broken line in the figure, this N ⁺ layer 7
4 and the N ⁺ layer 71 in the P layer 70 are connected, thereby connecting the N ⁺ layer 71 and the N layer 52' as a gate, and the P layer 70 sandwiched between them as a channel, P A JFET, that is, a normally-on transistor T ₅ is formed with the ⁺ layer 72 as the drain and the P ⁺ layer 73 as the source. On the other hand, there is also a P layer 75 on the surface of the N layer 53' and an N ⁺ layer 7 spaced apart from it.
4 is formed. On the surface of the P layer 75,
Additionally, one N ⁺ layer 76 and two P ⁺ layers 77,7
8 are arranged in the same manner as in the case of the P layer 70 described above. Then, similar to the previously mentioned normally-on transistor _T5 , the N ⁺ layer 76 and the N layer 5
3' is the gate, the P layer 75 sandwiched between them is the channel, the P ⁺ layer 77 is the drain, and the P ⁺ layer 78 is the source. are connected by one electrode 60 as shown in FIG. 5b, and are used as a resistive element R.

As described above, in this embodiment, in the N layers 52' and 53' formed separately on the semiconductor substrate in the form of islands,
Furthermore, a normally-on transistor _T5 and a JFET serving as a resistive element R are formed by double diffusion, and each JFET is constructed only within the N layers 52' and 53'. ing. Therefore, in this embodiment, as in the previous two embodiments (that is, in which the substrate itself is also used as part of the element), the potential of the substrate itself changes with the operation of the JFET. The substrate itself, that is, the semiconductor layer 51', the P ⁺ layer 69, etc., can always maintain a constant potential state without being stored. Therefore, in the previous two embodiments, other elements and
For example, whereas it was not possible to form FETT ₄ , etc., in this embodiment, FETT ₄ , etc. can be formed on the same substrate. As described above, in this embodiment, other elements such as FETT ₄ can be formed on the same substrate as the normally-on FETT ₅ and the resistive element R, so that the number of elements is the same as that of the first and second elements. Although the number of parts is larger than that of the second embodiment, the number of parts and steps do not increase significantly, and the operation is similar to that of FIGS. 6 and 7.

Up to now, the semiconductor devices of these two inventions have been described based on the above four embodiments, but the configurations of these inventions are not limited to the above embodiments. For example, the photoelectric conversion element array does not need to be provided directly above the FET or normally-on transistor as in the above embodiments, but rather on an insulating layer at a position away from the FET or normally-on transistor. I don't care if it seems like it's going to happen. Further, as the photoelectric conversion element array, two photoelectric conversion elements are used in the embodiment of the first invention, and three photoelectric conversion elements are used in the three embodiments of the second invention, each connected in series. The number of photoelectric conversion elements may be any number as long as it is at least two. The reason why photoelectric conversion elements must be used as a photoelectric conversion element array in which at least two or more photoelectric conversion elements are connected in series is as follows.

(1) In order to lower the resistance of the FET (T ₁ , T ₂ and T ₄ ) to a certain level, that is, to make it conductive, a gate voltage that is about 1V higher than the gate threshold electrode of the FET is required. do.

(2) Normally-on transistors (T ₃ , T ₅
etc.), a subthreshold current generally flows even at an electrode lower than the gate threshold electrode, so in order to reduce this to the level of leakage current, that is, to almost completely cut it off, a voltage of 600 mV or more is required. Requires gate voltage.

(3) A single PIN junction or PN junction of an impurity semiconductor thin film cannot provide sufficient voltage to satisfy the above (1) and (2).

For the above reasons, in these inventions, two or more photoelectric conversion elements are connected in series and the outputs of one unit of photoelectric conversion elements are added to generate an output sufficient to fully operate a FET or normally-on transistor. It is essential to form a photoelectric conversion element array that can produce In addition, when connecting these photoelectric conversion elements in series, the output electrodes of each photoelectric conversion element may be connected to each other as in the above embodiments, or one electrode may be used for both purposes. As a further method, for example, in PIN joining as in the previous embodiment, this PIN
Units can also be stacked repeatedly to form one element. In the above embodiments, a conductive thin film such as a metal thin film or a transparent conductive film was used to connect the end of the photoelectric conversion element array configured in this way to the FET or normally-on transistor. However, depending on the party to be connected, the P layer or N layer may be extended and connected as is. Furthermore, in the above embodiments, as described above, a thin film of amorphous silicon or Si single crystal formed by the laser melting crystallization method was used as the photoelectric conversion element formed on the insulating layer. , to avoid damaging the underlying FET, etc.
Alternatively, if the damage can be recovered even if it is damaged, a photoelectric conversion element using other materials such as Se or CdS can be used.

In the device shown in FIG. 1, a double-diffused MOSFET is used as the FET, and in the embodiment of the first invention, a normal MOSFET is used as the FET or normally-on transistor. Although embodiments of the invention use JFETs as normally-on transistors and low transistors, it is possible to use different types of FETs. This also applies to photoelectric conversion elements, and in the embodiment of the second invention.
It is also possible to use a PN junction type photoelectric conversion element, or to use a PIN junction type photoelectric conversion element in the embodiment of the first invention. Further, in these inventions, elements not used in the above embodiments can also be formed on the same substrate. The circuit configuration can also include those elements.

In short, the first invention is a semiconductor device in which at least a first photoelectric conversion element array is inserted between the gate and source of a field effect transistor, and which serves as a light receiving section of a switching device. The photoelectric conversion element array also includes a normally-on transistor connected in parallel with the conversion element array, and a second photoelectric conversion element array inserted between the gate and source of the normally-on transistor. A transistor is formed on the same semiconductor substrate as the field effect transistor, and first and second photoelectric conversion element arrays are formed on an insulating layer formed on the semiconductor substrate, and a second photoelectric conversion element array is formed on an insulating layer formed on the semiconductor substrate. In the invention, the first photoelectric conversion element array and the normally-on transistor are connected in parallel, and
The gate of this normally on transistor
A second photoelectric conversion element array and a resistive element for discharging the accumulated charge of the normally-on transistor are connected in parallel between the sources, and are inserted between the gate and source of the field effect transistor. The first and second photoelectric conversion element arrays are arranged on a semiconductor substrate on which at least the normally-on transistor is formed, the semiconductor device serving as a light receiving part of a switching device.
Other configurations are not particularly limited as long as they are formed via an insulating layer.

〔Effect of the invention〕

The first invention described above has the following effects.

A. The switching operation of FET, which is a switching element, is fast and stable.

When light is cut off, the normally-on transistor becomes conductive and the gate and source of the FET are shorted, resulting in the residual charge being quickly discharged and the FET operating quickly.
This prevents malfunctions caused by transient noise and signals input to the drain or source of the FET, and prevents both transistors from being neither on nor off when the amount of light is insufficient during light irradiation, ensuring stable FET operation. Become.

B. Even if the degree of integration is high, the manufacturing process does not become complicated and can be manufactured easily.

This is because the normally-on transistor and the FET can be manufactured through a common process to a large extent, and the first and second photoelectric conversion element arrays can also be manufactured through a common process.

C Even if the number of elements is large, the number of assembly steps and parts is small, resulting in lower costs and higher reliability.

The first and second photoelectric conversion element arrays are provided on a semiconductor substrate on which FETs and normally-on transistors are formed, and assembling costs are low because many processes and parts are not required. . Of course, there is no need to use an expensive DI board.

Since the sum of the individual defective rates of the number of parts is the defective rate of a normal device, the smaller the number of parts, the lower the defective rate, and the sum of the individual damage rates of each assembly process is the defective rate of a normal device. Therefore, the fewer the assembly steps, the lower the defective rate.

D Since both the first and second photoelectric conversion element arrays are prevented from decreasing the output voltage, it can be said that this is a practical device.

The first and second photoelectric conversion element arrays are provided on a semiconductor substrate on which FETs and normally-on transistors are formed, with an insulating layer interposed therebetween, so that output leakage from the photoelectric conversion element arrays is difficult to occur.

E: Electrostatic damage to FET, which is a switching element, will definitely prevent damage.

When cutting out the semiconductor substrate after manufacturing the device, there is already a normal wire between the gate and source of the FET.
It is no exaggeration to say that since the transistor is on and in a short-circuited state, the insulated gate will never be destroyed by static electricity.

The second invention has the following effects.

a The switching element FET operates quickly and stably.

When light is cut off, the normally-on transistor becomes conductive, shorting the gate and source of the FET, and as a result, the residual charge is quickly discharged, allowing the FET to operate quickly.
This prevents malfunctions due to transient noise and signals input to the drain or source of the FET, and also prevents both transistors from being neither on nor off when the amount of light is insufficient during light irradiation, resulting in stable FET operation. .

b. Even if the degree of integration is high, the manufacturing process does not become complicated and can be manufactured easily.

This is because both the first and second photoelectric conversion element arrays can be fabricated in a common process on a semiconductor substrate in which normally-on transistors are fabricated.

c Even if the number of elements is large, the number of assembly steps and parts is small, resulting in lower costs and higher reliability.

The first and second photoelectric conversion element arrays are provided on a semiconductor substrate on which normally-on transistors are formed, and many steps and parts are not required. Of course, there is no need to use an expensive DI board.

Since the sum of the individual failure rates of the number of parts is the failure rate of the device, the smaller the number of parts, the lower the failure rate, and the sum of the individual damage rates of each assembly process is the failure rate of the device. , the fewer the assembly steps, the lower the defective rate.

d Both the first and second photoelectric conversion element arrays can be said to be practical devices because a drop in output voltage is prevented.

Both the first and second photoelectric conversion element arrays are provided on the semiconductor substrate on which the normally-on transistors are formed, with an insulating layer interposed therebetween, making it difficult for output leakage of the photoelectric conversion element arrays to occur.

e Operation when light is interrupted is extremely fast.

This is because when light is interrupted, the accumulated charge in the normally-on transistor is quickly discharged by the resistive element, and the normally-on transistor immediately becomes conductive.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a specific structure of a semiconductor device that is the basis of this invention, FIG. 2 is a circuit diagram showing a general configuration of a switching device, and FIG. 3 is a semiconductor device of the first invention. FIG. 4 is an equivalent circuit diagram of this embodiment, FIGS. 5 a and b are equivalent circuit diagrams of the embodiment of the second invention, and FIG. FIGS. 7 and 8 are explanatory diagrams showing the structure of the main part of the embodiment, and FIGS. 7 and 8 are explanatory diagrams showing the main part of still another embodiment, respectively. T ₁ , T ₂ , T ₄ ... electric field expensive transistors,
DA ₁ , DA ₂ , DA ₃ , DA ₄ ... Photoelectric conversion element array, 1, 21, 51 ... Semiconductor substrate, 7, 26,
61...Insulating layer.

Claims (1)

[Scope of Claims] 1. A semiconductor device comprising at least a first photoelectric conversion element array inserted between the gate and source of a field effect transistor and serving as a light receiving section of a switching device, wherein the first photoelectric conversion element array is inserted between the gate and source of a field effect transistor. It also includes a normally-on transistor connected in parallel with the element array, and a second photoelectric conversion element array inserted between the gate and source of the normally-on transistor, and the normally-on transistor is formed on the same semiconductor substrate as the field effect transistor, and the first and second photoelectric conversion element arrays are formed on an insulating layer formed on the semiconductor substrate. Semiconductor equipment. 2 A first photoelectric conversion element array and a normally on transistor are connected in parallel, and a second photoelectric conversion element array and a normally on transistor are connected between the gate and source of this normally on transistor. A semiconductor device, which is connected in parallel with a resistive element for discharging accumulated charge of an on-state transistor, and is inserted between the gate and source of a field effect transistor to serve as a light receiving section of a switching device, 1. A semiconductor device, wherein first and second photoelectric conversion element arrays are formed on a semiconductor substrate on which at least the normally-on transistor is formed, with an insulating layer interposed therebetween.