JPH0556879B2 - - Google Patents
Info
- Publication number
- JPH0556879B2 JPH0556879B2 JP10831087A JP10831087A JPH0556879B2 JP H0556879 B2 JPH0556879 B2 JP H0556879B2 JP 10831087 A JP10831087 A JP 10831087A JP 10831087 A JP10831087 A JP 10831087A JP H0556879 B2 JPH0556879 B2 JP H0556879B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- circuit pattern
- forming
- printed wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004020 conductor Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 26
- 238000000034 method Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板の製造方法に関し、特
に、ブラインド・バイア・ホール(Blind via
hole)を有する多層印刷配線板の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer printed wiring board, and in particular, to a method for manufacturing a multilayer printed wiring board, and in particular to a method for manufacturing a multilayer printed wiring board.
The present invention relates to a method for manufacturing a multilayer printed wiring board having holes.
近年、電子機器の性能上および経済上のニーズ
から実装の高密化が進められてきている。
In recent years, the performance and economic needs of electronic devices have led to an increase in the density of packaging.
このために、IC、LSI等の電子デバイスの高集
積化、高速化が図られていることは勿論、これら
を実装する印刷配線板についても高密度化が進め
られている。 For this reason, not only are electronic devices such as ICs and LSIs becoming more highly integrated and faster, but printed wiring boards on which these devices are mounted are also becoming more dense.
従来の印刷配線板は部品挿入用の孔は勿論、バ
イアホールも貫通されて、めつき等により孔内壁
に導体層を形成させるのが一般的である。 In conventional printed wiring boards, not only holes for inserting components but also via holes are penetrated, and a conductive layer is generally formed on the inner wall of the hole by plating or the like.
また、多層印刷配線板(以下多層化基板と称
す)は、その高多層化に伴ない一部の内層にイン
ナーレイヤー・バイア・ホール(Inner layer
via hole)を設ける設計が採用されている。一つ
の試みとして、例えば特願昭58−049858号公報に
導体回路を接続するブラインド・バイア・ホール
の穴内空間を樹脂で充填する多層印刷配線板の製
造方法がある。 In addition, as multilayer printed wiring boards (hereinafter referred to as multilayer boards) become highly multilayered, some inner layers have inner layer via holes (inner layer via holes).
A design with a via hole is adopted. As one attempt, for example, Japanese Patent Application No. 58-049858 discloses a method for manufacturing a multilayer printed wiring board in which the space inside a blind via hole for connecting a conductive circuit is filled with resin.
これは第2図に示すように、スルーホール10
を有し、一方の面に導体層がそして他方の面に導
体回路パターンが形成された2枚の積層板1A,
1C間の導体回路パターンが形成された積層板1
bとこの積層板1bをはさむプリプレグ層5A,
5Bとを配置したのち、加熱・加圧し多層化基板
を形成するものである。 This is the through hole 10 as shown in Figure 2.
two laminated plates 1A having a conductive layer on one side and a conductive circuit pattern on the other side,
Laminated board 1 on which a conductor circuit pattern between 1C is formed
b and a prepreg layer 5A sandwiching this laminate 1b,
5B and then heated and pressurized to form a multilayered substrate.
上述した多層化基板の製造上の問題として、絶
縁板にスルホール4を有し、かつ予め一面のみに
導体回路パターンを形成した2枚の絶縁板1A,
1Cを最外層として配置し、その内側に予め導体
回路パターンを形成した1つ以上の絶縁板1Bと
プリプレグ層5A,5Bとを介し積み重ねた後
に、加熱・加圧して多層化基板を形成する時、最
外層にあるスルホール10よりプリプレグのしみ
出しが生じ、その後工程で多層化基板表面の導体
層に所望の導体回路パターンを形成するのにエツ
チング不良を起し、製造歩留り及び信頼性を低下
させるという問題点がある。
As a problem in manufacturing the above-mentioned multilayer board, two insulating plates 1A, each having a through hole 4 in the insulating plate and having a conductor circuit pattern formed on only one surface in advance,
1C is placed as the outermost layer, and after stacking the prepreg layers 5A and 5B with one or more insulating plates 1B on the inner side of which a conductor circuit pattern has been formed in advance, a multilayered board is formed by heating and pressurizing. , prepreg seeps out from the through holes 10 in the outermost layer, causing etching defects when forming the desired conductor circuit pattern on the conductor layer on the surface of the multilayer substrate in the subsequent process, reducing manufacturing yield and reliability. There is a problem.
本発明の目的は、製造葉留り及び信頼性の向上
した多層印刷配線板の製造方法を提供することに
ある。 An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board with improved manufacturing yield and reliability.
本発明の多層印刷配線板の製造方法は、スルー
ホールを有する第1の絶縁板の一方の面に導体回
路パターンを形成し、他方の面にホトレジスト膜
を形成する工程と、2枚の前記第1の絶縁板の導
体回路パターンを向い合せてそれぞれ最外層とし
て配置し、その内側に導体回路パターンが形成さ
れた少くとも1枚の第2の絶縁板と該第2の絶縁
板をはさむプリプレグ層とを積み重ねたのち加
熱・加圧して多層化基板を形成する工程と、前記
多層化基板表面の前記ホトレジスト膜を除去した
のち多層化基板の所定部分にスルーホールを形成
する工程と、前記スルーホールの内壁を含む前記
多層化基板の表面に導体層を形成したのちパター
ニングして導体回路パターンを形成する工程とを
含んで構成される。
The method for manufacturing a multilayer printed wiring board of the present invention includes the steps of forming a conductive circuit pattern on one side of a first insulating plate having through holes and forming a photoresist film on the other side; The conductor circuit patterns of the first insulating plates are arranged as the outermost layer, facing each other, and at least one second insulating plate having the conductor circuit pattern formed inside the second insulating plate, and a prepreg layer sandwiching the second insulating plate. forming a multilayered substrate by stacking them and then heating and pressurizing them; forming a through hole in a predetermined portion of the multilayered substrate after removing the photoresist film on the surface of the multilayered substrate; and forming a through hole in a predetermined portion of the multilayered substrate The method includes the steps of forming a conductor layer on the surface of the multilayer substrate including the inner wall of the substrate, and then patterning the conductor layer to form a conductor circuit pattern.
以下、本発明の実施例を図面を用いて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.
第1図a〜fは本発明の一実施例を説明するた
めの断面図である。 FIGS. 1a to 1f are cross-sectional views for explaining one embodiment of the present invention.
まず第1図aに示すように、両面に銅箔2A,
2Bが形成された積層板1Aにドリルによりスル
ーホール4Aを形成する。 First, as shown in Figure 1a, copper foil 2A is placed on both sides.
A through hole 4A is formed by a drill in the laminated plate 1A on which the hole 2B is formed.
次に第1図bにし示すように、公知の無電界め
つきと電気めつき手段によりスルーホール4Aを
含む全面に導体層6を形成する。 Next, as shown in FIG. 1b, a conductor layer 6 is formed on the entire surface including the through holes 4A by known electroless plating and electroplating means.
次に第1図cに示すように、公知のテンテイン
グ法を用いて、上面には全面に下面には所望する
回路パターン部を光感光性のドライフイルムレジ
スト膜7で被覆した後、上面のドライフイルムレ
ジスト膜7のカバーフイルムを剥がさないで、下
面のみ、現像、エツチング、剥離工程を行ない、
下面にのみ回路パターン11を形成する。 Next, as shown in FIG. 1c, using a well-known tenting method, the entire upper surface and the lower surface are coated with a photosensitive dry film resist film 7 covering the desired circuit pattern portion, and then the upper surface is coated with a dry film resist film 7. The cover film of the film resist film 7 is not removed, and only the lower surface is subjected to development, etching, and peeling steps.
The circuit pattern 11 is formed only on the lower surface.
次に第1図dに示すように、ドライフイルムレ
ジスト膜7と回路パターン11とが形成された積
層板1Aと、積層板1Aと同様に処理された積層
板1Cとを回路パターン11を向い合わせて配置
し、その内側に回路パターンが形成された積層板
1Bと、この積層板1Bをはさむプリプレグ層5
A,5Bとを積み重ねたのち、加熱・加圧して一
体化形成し、多層化基板1を形成する。この際ス
ルーホール4Aは、いわゆる非貫通のブライン
ド・バイア・ホール4Bとして形成され、加湿・
加圧されたプリプレグ層5A,5Bは、ドライフ
イルムレジスト膜7によりさえぎられ、外部に流
れることはなくなる。 Next, as shown in FIG. 1d, the laminate 1A on which the dry film resist film 7 and the circuit pattern 11 have been formed and the laminate 1C treated in the same manner as the laminate 1A are placed so that the circuit pattern 11 faces each other. A laminate 1B with a circuit pattern formed on the inside thereof, and a prepreg layer 5 sandwiching this laminate 1B.
After stacking A and 5B, they are heated and pressurized to form an integrated structure, thereby forming the multilayer substrate 1. At this time, the through hole 4A is formed as a so-called non-penetrating blind via hole 4B, and the humidification and
The pressurized prepreg layers 5A and 5B are blocked by the dry film resist film 7 and do not flow to the outside.
尚、ドライフイルムレジスト膜7は露光してお
いた方が強度が大きくなるため好ましい。 Incidentally, it is preferable that the dry film resist film 7 is exposed to light because the strength thereof becomes greater.
次に第1図eに示すように、ドライフイルムレ
ジスト膜7を除去したのち、部品挿入用の孔また
は内層パターンに接続する孔をドリルにより穿孔
し、貫通孔3を設ける。次に公知の無電界めつき
と電気めつき手段により、貫通孔3の内壁を含む
全面に導体層6Aを形成する。 Next, as shown in FIG. 1e, after removing the dry film resist film 7, a through hole 3 is formed by drilling a hole for inserting a component or a hole connecting to the inner layer pattern. Next, a conductor layer 6A is formed on the entire surface including the inner wall of the through hole 3 by known electroless plating and electroplating means.
次に第1図fに示すように、公知のテンテイン
グ法を用いて、貫通孔3および所望する回路パタ
ーン部をドライフイルムレジストで被覆した後、
不要な導体層6Aその下層の導体層6および銅箔
2A,2Fをエツチング除去して、所棒のブライ
ンド・バイア・ホール4Bを有する多層印刷配線
板を完成させる。 Next, as shown in FIG. 1f, after covering the through hole 3 and the desired circuit pattern portion with a dry film resist using a known tenting method,
Unnecessary conductor layer 6A, underlying conductor layer 6, and copper foils 2A, 2F are etched away to complete a multilayer printed wiring board having blind via holes 4B.
このようにして得られたブラインド・バイア・
ホールを有する多層印刷配線板は従来のものと比
較して、次のような効果が得られる。 The blind bias obtained in this way
The multilayer printed wiring board with holes has the following effects compared to conventional ones.
(1) 最外層に所望する回路パターン部を形成する
時、プリプレグのスルーホールからのしみ出し
がないため、エツチングのこり等の不良がなく
なり、歩留りが向上する。(1) When forming the desired circuit pattern on the outermost layer, there is no seepage from the prepreg through-holes, eliminating defects such as etching lumps and improving yield.
(2) プリプレグのスルーホールからのしみ出しが
ないため、均一な積層圧力により配線板が形成
できる。(2) Since there is no seepage from prepreg through holes, wiring boards can be formed with uniform lamination pressure.
(3) 最外層の光感光性ドライフイルムレジスト層
が、積層時における圧力媒体である鏡板との間
でクツシヨンの役割を果たし、積層仕上り不良
である打痕不良が減少し歩留りが向上する。(3) The outermost photosensitive dry film resist layer plays the role of a cushion between the end plate, which is the pressure medium during lamination, and reduces dent defects, which are poor lamination finishes, and improves yield.
尚、上記実施例においては両面に銅箔が形成さ
れた積層板1Aを用いた場合について説明した
が、ドライフイルムレジスト膜7を被覆する面に
銅箔のない積層板を用いてもよい。この場合はド
ライフイルムレジスト膜を形成する面が粗い積層
板を用い、無電界めつきが施しやすいようにす
る。そして第1図bの工程で積層板1Aのスルー
ホール4Aを含む全面に無電界めつきと電気めつ
きの手段により導体層を形成する。 In the above embodiment, a case has been described in which a laminate 1A having copper foil formed on both sides is used, but a laminate without copper foil on the surface covering the dry film resist film 7 may also be used. In this case, a laminated plate with a rough surface on which the dry film resist film is formed is used to facilitate electroless plating. Then, in the step shown in FIG. 1B, a conductor layer is formed on the entire surface of the laminate 1A, including the through holes 4A, by means of electroless plating and electroplating.
以上説明したように本発明は、スルーホールを
有する第1の絶縁板の表面にホトレジスト膜を形
成し、この第1の絶縁膜を最外層として配置し、
この内側に回路パターンを有する第2の絶縁板と
プリプレグ層とを重ね、加熱・加圧して多層印刷
配線板を形成することにより、製造歩留り及び信
頼性の向上した多層印刷配線板が得られる。
As explained above, the present invention forms a photoresist film on the surface of a first insulating plate having through holes, arranges this first insulating film as the outermost layer,
A multilayer printed wiring board with improved manufacturing yield and reliability can be obtained by stacking a prepreg layer and a second insulating plate having a circuit pattern on the inside and heating and pressurizing the prepreg layer to form a multilayer printed wiring board.
第1図a〜fは本発明の一実施例を説明するた
めの製造工程順に示した断面図、第2図は従来の
多層印刷配線板の製造方法を説明するための断面
図である。
1……多層化基板、1A〜1C……積層板、2
A〜2F……銅箔、3……貫通孔、4A……スル
ーホール、4B……ブラインドバイアスホール、
5A,5B……プリプレグ層、6,6A……導体
層、7……ドライフイルムレジスト膜、10……
スルーホール、11……回路パターン。
1A to 1F are cross-sectional views showing the order of manufacturing steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional method for manufacturing a multilayer printed wiring board. 1...Multilayer substrate, 1A to 1C...Laminated board, 2
A to 2F...Copper foil, 3...Through hole, 4A...Through hole, 4B...Blind bias hole,
5A, 5B... prepreg layer, 6, 6A... conductor layer, 7... dry film resist film, 10...
Through hole, 11...Circuit pattern.
Claims (1)
面に導体回路パターンを形成し、他方の面にホト
レジスト膜を形成する工程と、2枚の前記第1の
絶縁板の導体回路パターンを向い合せてそれぞれ
最外層として配置し、その内側に導体回路パター
ンが形成された少くとも1枚の第2の絶縁板と該
第2の絶縁板をはさむプリプレグ層とを積み重ね
たのち加熱・加圧して多層化基板を形成する工程
と、前記多層化基板表面の前記ホトレジスト膜を
除去したのち多層化基板の所定部分にスルーホー
ルを形成する工程と、前記スルーホールの内壁を
含む前記多層化基板の表面に導体層を形成したの
ちパターニングして導体回路パターンを形成する
工程とを含むことを特徴とする多層印刷配線板の
製造方法。1. Forming a conductive circuit pattern on one side of a first insulating plate having through holes and forming a photoresist film on the other side, and aligning the conductive circuit patterns of the two first insulating plates At least one second insulating board with a conductor circuit pattern formed inside the second insulating board and a prepreg layer sandwiching the second insulating board are stacked, and heated and pressurized to form a multilayer. a step of forming a through hole in a predetermined portion of the multilayer substrate after removing the photoresist film on the surface of the multilayer substrate, and a step of forming a through hole on the surface of the multilayer substrate including the inner wall of the through hole A method for producing a multilayer printed wiring board, comprising the steps of forming a conductor layer and then patterning it to form a conductor circuit pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10831087A JPS63273399A (en) | 1987-04-30 | 1987-04-30 | Manufacture of multilayered printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10831087A JPS63273399A (en) | 1987-04-30 | 1987-04-30 | Manufacture of multilayered printed interconnection board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63273399A JPS63273399A (en) | 1988-11-10 |
| JPH0556879B2 true JPH0556879B2 (en) | 1993-08-20 |
Family
ID=14481466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10831087A Granted JPS63273399A (en) | 1987-04-30 | 1987-04-30 | Manufacture of multilayered printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63273399A (en) |
-
1987
- 1987-04-30 JP JP10831087A patent/JPS63273399A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63273399A (en) | 1988-11-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |