JPH0557615B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic processing device that improves processing efficiency.

[Technical background of the invention and its problems] In image processing, measured image data is compared with threshold data and binarized, but this processing is performed using a microprogram control method, and conventionally, This is performed by an arithmetic processing device as shown in FIG. In FIG. 3, microprograms are stored in advance in an instruction memory 1, and are sequentially read out from the instruction memory 1 according to addresses from a sequencer 3 and set in an instruction register 25. The instruction register 25 usually consists of several tens of bits, and includes a jump control section 25a, an arithmetic logic function specification section, that is, an ALU function specification section 25b, an R selection section 25c, an S selection section 25d, and other instructions for reading the image memory. , image memory address control (increment, decrement, etc.). The ALU function specification section 25b of the instruction register 25 is an arithmetic logic unit, that is,
Connected to ALU9, the arithmetic logic functions of ALU9, namely + (addition), - (subtraction), AND (logical product), OR
(logical sum), HI (high level: hexadecimal FF), LO
(Low level: O) etc. Specify one of the arithmetic logic functions. The ALU 9 executes the arithmetic logic function specified by the ALU function specifying section 25b as described above with respect to the two inputs supplied from the S input and the R input. When the selector 17 is gated by the S select section 25b of the instruction register 25, the data designated by the S select section 25d is input to the S input of the ALU 9 via the input bus 17a.
Similarly, the R input of the ALU9 is supplied with the R select 25c of the instruction register 25.
When the selector 17 is gated, the data specified by the R select section 25c is transferred to the input bus 19.
It is designed to be supplied from a. The result processed by the ALU 9 is output from the output Y of the ALU 9 to the output bus 9a, but a carry, that is, a carry, that occurs in the processed result, a zero indicating that the content of the calculation result is zero, or Status display information such as overflow etc. is held in the status register 11 from the ALU 9. The output of the status register 11 is connected to the selector 15,
Further, the jump control section 25a of the instruction register 25 is connected to the selector 15 and also to the sequencer 3.

Figure 4 shows the binarization process of image data using this conventional arithmetic processing device, that is, comparing the image data with the threshold data and outputting HI (high level = FF in hexadecimal) if it is larger. and if it is small
This shows an example of a microprogram that performs processing to output LO (low level=O) to an image memory. The operation will be briefly explained with reference to FIGS. 3 and 4.

In step 1 in FIG. 4, image data in the image memory VRAM is set to R select, and S
Threshold information is set to select, and ALU9 calculates Y=RS, that is, image memory
A threshold value is subtracted from the VRAM data, and in step 2, HI (high level = hexadecimal FF) is written to the image memory. At this time, if the carry is "0" as a result of the calculation in step 1, that is, if the data threshold value of the image memory VRAM is ≧0, the next step 3 is skipped and the process jumps to step 4. However, as a result of the calculation in step 1, if the carry is not "0", that is, if the data threshold of the image memory VRAM is <0, the process proceeds to the next step 3, and the LO (low level = 0) is stored in the image memory. Write it in and proceed to step 4. In step 4, the address of the image memory is incremented,
As in step 1, a threshold value is subtracted from the data in the image memory VRAM, and then the process jumps to step 2, after which steps 2-4 are repeated for all image memories. In addition,
Binarization processing of image data is performed when the data in the image memory is
In the case of 256×256, process step 2-4 above.
Repeat 256 x 256 times.

In the conventional image processing arithmetic processing unit configured and operated as described above, two steps, steps 2 and 3, are performed to write HI or LO to the image memory depending on whether the carry is "0" or not. In addition, if the carry is "0", step 3 is skipped and jumps to step 4, but if the carry is not "0", step 3 is executed.
, and then proceeds to step 4, so the number of steps to be executed differs depending on whether the carry is "0" or not. In this way, in conventional processing steps, when the next process is determined by the result of a certain operation, instructions are issued for each branch so that each process can be performed using a jump instruction. At least 2
Since more than one instruction step is required, the program step becomes long and high speed cannot be achieved, and since the number of execution steps differs depending on the data, other processing functions (for example, spatial filtering There is a problem in that it is difficult to perform synchronous parallel processing with other systems (eg.

[Object of the Invention] The present invention has been made in view of the above, and its purpose is to provide an arithmetic processing device that achieves high speed and facilitates synchronous parallel processing with other processing functions. It's about doing.

[Summary of the Invention] In order to achieve the above object, the present invention provides an instruction register in which an instruction having a plurality of arithmetic logic instructions and a condition setting code for selecting an arithmetic logic instruction is set, and A status register that holds status information of the arithmetic and logic results as a result of executing an instruction, and a condition setting code for selecting the arithmetic and logic instruction of the instruction that is set in the instruction register. a selector that selects held state information and selects any one of a plurality of arithmetic and logic instructions set in the instruction register according to the state information; and an arithmetic and logic instruction selected by the selector. The gist is to have an arithmetic and logic unit that executes.

[Embodiments of the Invention] Examples of the invention will be described below with reference to the drawings.

FIG. 1 is a block diagram when an arithmetic processing device according to an embodiment of the present invention is applied to image processing. The arithmetic processing unit shown in the figure binarizes measured image data by comparing it with threshold data, and is controlled by a microprogram control method stored in the instruction memory 1. ing. Each instruction stored in the instruction memory 1 is sequentially read out according to the address from the sequencer 3 and set in the instruction register 5. The instruction register 5 includes a jump control section 5a, a condition setting code section for arithmetic and logic instruction selection, that is, an ALU condition section 5b, and two arithmetic and logic function specification sections, a first and a second arithmetic and logic function specification section, that is, a first ALU function specification section 5c. , second ALU function specification section 5d, R selection section 5e, S selection section 5f, output selection section 5
g, and other image memory read instructions,
It consists of image memory address control (increment, decrement, etc.). The first ALU function specifying section 5c and the second ALU function specifying section 5d of the instruction register 5 are connected to the first and second inputs D1 and D2 of the function selection selector 7, respectively. The output DY of the condition selection selector 13 is connected to the selection input S of the function selection selector 7, and this output signal causes the first or second input D1 or D2 of the function selection selector 7 to be connected. Either the ALU function specification section 5c or the second ALU function specification section 5d is selected, and the arithmetic logic function specification signal from the selected ALU function specification section is sent from the output DY of the function selection selector 7 to the function of the ALU 9. It is adapted to be supplied to the selection input. ALU9 is
The arithmetic logic functions executed by the ALU 9, which execute the arithmetic logic function according to the arithmetic logic function designation signal supplied via the function selection selector 7, include + (addition), - (subtraction), AND (logical AND), OR
(logical sum), HI (high level: FF in hexadecimal), LO (low level: 0), etc. The ALU 9 executes the specified arithmetic logic function supplied via the function selection selector 7 as described above with respect to the two inputs supplied from the S input and the R input. The S select section 5f of the instruction register 5 gates the selector 17 to the S input of the ALU9, so that the data specified by the S select section 5f is supplied from the input bus 17a, and similarly, the R input of the ALU9 is supplied with the data specified by the S select section 5f. When the selector 17 is gated by the R select section 5e of the instruction register 5, data specified by the R select section 5e is supplied from the input bus 19a. ALU
The result of the calculation in step 9 is output from the output Y of the ALU 9 to the output bus 9a, but the carry signal generated from the ALU 9 as a result of the calculation, that is, the carry signal, indicates that the content of the calculation result is zero. A status indicating signal such as a zero signal or an overflow signal is held from the ALU 9 in the status register 11. The status display signal held in the status register 11 is supplied to the sequencer selector 15 and also to the condition selection selector 13, where it selects the ALU condition of the next instruction set in the instruction register 5. One of the status display signals is selected by the section 5b, and the selected status display signal, such as a carry signal, a zero signal, or an overflow signal, is supplied to the function selection selector 7, and the content of the status display signal is Accordingly, the first ALU function specification section 5c or the second ALU function specification section 5d of the next instruction is selected by the function selection selector 7, and as a result, the arithmetic logic function of the next instruction to be executed by the ALU 9 is selected. is now being determined. Further, the jump control section 5a of the instruction register 5 is supplied to the sequencer 3 and the sequencer selector 15 to perform jump control.

Next, the operation of the image processing arithmetic processing device shown in FIG. 1 will be explained with reference to a program example shown in FIG.

FIG. 2 shows an example of a program for binarizing image data by comparing it with threshold data, and these programs are stored in the instruction memory 1. When the step 1 instruction is first set in the instruction register 5 from the instruction memory 1 by addressing from the sequencer 3, the R select section 5e of the instruction register 5 is set.
The image data set in the image memory VRAM is supplied to the S input of the ALU 9 via the selector 17, and the threshold data set in the S select section 5f is supplied via the selector 19 to the S input of the ALU 9.
Supplied to the R input of ALU9. ALU function specification section 5 of instruction register 5
c, 5d specify Y=RS as the arithmetic logic function executed by the ALU9, so in step 1, an operation is performed to subtract the threshold data from the image data from the image memory VRAM, and in this operation Status information such as carry status is held in the status register 11.

In the next step 2, the instruction set in the instruction register 5 is
Since a condition setting code to select a carry signal is set in the ALU condition section 5b, the condition selection selector 13 selects the carry signal held in the status register 11 in the previous step, and selects this carry signal. The selection input is supplied to the function selection selector 7. As a result, the function selection selector 7 selects the first ALU function designation section 5c when the carry signal is "0", and as a result, in the ALU 9, Y=HI
(FF in hexadecimal) and outputs a high level signal, and if the carry signal is "1", the second
The ALU function specifying section 5d is selected, whereby the ALU 9 executes Y=LO and outputs a low level signal. This execution result is stored in the image memory VRAM selected by the output select 5g.

Next, the process proceeds to step 3, where the address of the image memory is incremented, and the same process as in step 1, that is, the calculation of subtracting the threshold value data from the image data from the image memory VRAM, is executed. It jumps and is controlled in a loop. Thereafter, the operations of steps 2 and 3 are repeated, for example, 256×256 times for the image data in the image memory VRAM. The number of repeated steps in this case is 2 x 256 x 256 steps, which is constant regardless of the content of the data in the image memory, and the number of steps may increase if the carry signal is not "0" as in the conventional case. It is now faster.

[Effects of the Invention] As explained above, according to the present invention, an instruction having a plurality of arithmetic logic instructions and a condition setting code for arithmetic logic instruction selection is set in the instruction register, and is executed in the previous step. The content of the status register that holds the status of the arithmetic logic result of the instruction that has been executed is selected by the arithmetic logic instruction selection condition setting code, and the selected status information is used to select the contents of the status register that holds the state of the arithmetic logic result of the instruction. One of them is selected and the selected arithmetic and logic instruction is executed. As a result, when executing different processes depending on the contents of the state information, for example, when the state information is in the first state, the first instruction of the multiple arithmetic and logic instructions is executed without jumping to another state. However, in the case of the second state, there is no need to jump to another location such as executing the second instruction, so the number of steps is shortened by jumping and executing the instruction at another location, increasing speed. In addition, since the number of steps does not differ depending on the content of the state information, it is easy to synchronize with other parallel processors, such as those for spatial filter multiplication, and as a result, processing It is possible to improve efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic processing device showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a program for binarizing image data executed by the device shown in FIG. 1, and FIG. FIG. 4, a block diagram of a conventional arithmetic processing device, is a diagram showing an example of a conventional program for binarizing image data, which is executed by the device shown in FIG. 1...Instruction memory, 3...Sequencer, 5...Instruction register, 7
...Function selection selector, 9...ALU, 11...
...Status register, 13...Selector for condition selection.

Claims (1)

[Claims] 1. An instruction register in which instructions having multiple arithmetic logic instructions and condition setting codes for arithmetic logic instruction selection are set, and status information of the arithmetic logic result as a result of the execution of the instruction of the previous step. Select the state information held in the state register according to the state register to be held and the condition setting code for selecting the arithmetic logic instruction of the instruction set in the instruction register, and select the state information held in the state register. Arithmetic processing characterized by having a selector for selecting one of a plurality of arithmetic and logic instructions set in the instruction register, and an arithmetic and logic unit that executes the arithmetic and logic instruction selected by the selector. Device.