JPH0557616B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device that can correctly output a target instruction sequence from a branch destination buffer storage device even when branching to one of a plurality of target instructions. be.

[Background of the Invention] Pipeline computers break down instruction processing into partial processes, prepare independent units dedicated to executing each partial process, and overlap multiple consecutive instructions like a factory assembly line. By doing so, high-speed processing is achieved. However, when a branch instruction appears, the flow of the pipeline is disturbed, resulting in a decrease in processing performance. Therefore, in order to improve the processing performance of a computer that performs high-speed processing, high-speed processing of branch instructions is essential.

The reason why the flow of the pipeline is disrupted by the appearance of a branch instruction is that when a branch is taken, it takes time to obtain the target instruction (branch destination instruction), and until this is obtained, the decoding of the target instruction is difficult. is unable to start. Therefore, in order to process branch instructions at high speed, it is necessary to speed up the target fetch.

Conventionally, a route memory has been proposed as a device for realizing high-speed target fetch (see Japanese Patent Publication No. 54-9456, ``Information Processing Apparatus'').
As shown in FIG. 1, the root memory 1 uses the instruction address (IA) as a key when decoding an instruction.
It is an associative memory that outputs the following two things.

That is, (i) predicting whether the instruction pointed to by the instruction address is a branch instruction that will take effect (BA?), and (ii) if it is a branch instruction that will take effect, the target instruction word (TI). . However, the route memory 1 has the following problems.

In other words, since root memory 1 is referenced using only the instruction address (IA) as a key, it is not possible to handle cases where one branch instruction branches to any one of multiple target instructions. . In other words, as shown in FIG. 2, the program branches from point A of main routine 3 to the earlier application address of the subroutine (SUBRT), returns to target address 4 after completing this, and then returns to the same subroutine (SUBRT) at point B. SUBRT) and return after completing this, the instruction word at target address 4 is stored in root memory 1, so it is not possible to return to the correct instruction word at target address 5.

[Purpose of the invention]

A first object of the present invention is to make it possible to register a branch destination instruction in an associative memory means and to reuse it even when the address of the branch destination instruction specified by the same branch instruction may change each time the branch instruction is executed. The purpose of this invention is to provide an information processing device that makes it possible.

A second object of the present invention is to provide information that allows the branch destination instruction of a branch instruction to be read out at high speed when the branch instruction is re-executed after the branch destination instruction of the branch instruction is registered in an associative storage means. The purpose of this invention is to provide a processing device.

[Summary of the invention]

The feature of the first invention of the present application is that when a branch is successfully executed when a branch instruction is executed (for example, a branch at point A in FIG. 2, or at the end of a subroutine (RTN)
), branch instruction address information (e.g.,
The first associative key consists of the point A address in Figure 2, or the end (RTN) address of the subroutine), and the address of the branch destination instruction (for example, the start address of the subroutine in Figure 2, or the address of point A). Means for storing a pair with a second associative key consisting of information for generating address 4 to address 5) of point B as an associative key in the associative storage means 102 together with the branch destination instruction (IC, IR, etc.) ), and when a certain branch destination instruction is executed, a first association key consisting of the address information of the branch instruction and a second association consisting of information for generating the address of the branch destination instruction specified by that instruction. A means (IC, IR, etc. and 14) for supplying a pair with a key to the associative memory means 102 as an associative key, and a branch destination instruction having an associative key that matches the supplied associative key is read from the associative memory means 102. and means 22 for predicting that the branch of the branch instruction will be successful when the branch instruction is executed, and for executing the branch instruction.

A more desirable embodiment of the first invention is a means (14, IC, etc.) for supplying the first associative key to the associative memory means 102 at a first timing.
and means (GRB, GRX, etc.) for supplying the second associative key to the associative memory means 102 at a second timing subsequent to the first timing, and the associative memory means 102 is configured to supply the second associative key to the associative memory means 102 at a second timing after the first timing. When a first associative key consisting of address information is supplied, means (248, 250 in FIG. 5) for detecting a branch destination instruction having a first associative key that matches the first associative key; When a second associative key consisting of information for generating an address is subsequently supplied, the second associative key that matches the supplied second associative key is selected among the detected plurality of branch destination instructions.
It consists of means (32, 34 in FIG. 4) for selecting and supplying one branch destination instruction having an associative key.

Here, the first timing is, for example, before the start of execution of the branch instruction, and the second timing is, for example, after the start of execution of the branch instruction. Or the first
The timing is before the branch instruction is decoded, and the second
The timing can be said to be after the branch instruction is decoded. Alternatively, the first timing may be at the latest when the branch instruction is read, and the second timing may be after the branch instruction is read.

A feature of the second invention of the present application is that the address information specified by the branch destination instruction is stored as an associative key in the associative storage means 102 that stores the branch destination instruction. When this branch instruction is re-executed, the address information specified by the branch instruction, which is used to calculate the address of the branch destination instruction, is used as an associative key for reading the branch destination instruction from the content addressable memory means 102. is to use.

Note that this second invention does not mention whether address information of a branch instruction is used as an associative key. In that sense, this invention is independent from the first invention. However, in both inventions, when information related to the address of a branch destination instruction is used as an associative key, and the branch destination instruction is registered in the associative storage means 102, the branch instruction is executed assuming that the branch is successful. There are common characteristics.

[Embodiments of the invention]

FIG. 3 is a diagram showing an interface between a branch destination buffer storage device and an instruction processing device according to the present invention.

The instruction processing device 100 and the branch destination buffer storage device 102 are connected to an IC signal line 104 and a DISP signal line 10.
6, BRN signal line 108, GRB signal line 110,
GRX signal line 112, TKNP signal line 114, PTI
They are coupled by a total of nine signal lines: a signal line 118, a TI signal line 120, and a TKN signal line 122.

The branch destination buffer storage device 102 of the present invention stores parameters that determine the instruction address of a branch instruction, displacement information, and target address of a branch instruction word, that is, a register value indicated by register specification information in a branch instruction using an associative key (e.g. , the information on the address RTN at the end of the subroutine in FIG. It outputs an instruction word including the target instruction word of the branch instruction.

Note that certain computers (for example, IBM
System/370), the target address is determined by the base register value, index register value, and displacement information specified by the branch instruction.This example supports this case, and the base register value is used as the above parameter. -Uses register value and index register value.

Also, for a branch instruction whose target instruction address is the value of a general-purpose register specified by the branch instruction, rather than the sum of the base register value, index register value, and displacement information in the branch instruction word,
When this embodiment is applied, one value of the base register or index register which becomes the associative key (second associative key) is set to zero, and the other value is set as the value of the general-purpose register and the branch destination buffer is set to zero. Access the storage device 102.

The branch destination buffer storage device 102 uses the values of the base register and index register pointed to by the branch instruction (the value of the general register for a branch instruction whose target address is the value of a general register) as an associative key (i.e., the value of the general register). This is used as the first associative key (first associative key), so even when one branch instruction branches to one of multiple target instructions, such as a subroutine return, this associative key is different. can be handled.

By using the branch destination buffer storage device 102, the target fetch speed can be increased.
Branch instructions can be processed quickly. Then, the branch destination instruction can be executed assuming that the branch of the branch instruction is successful, that is, without waiting for the result of the branch determination of the branch instruction.

The branch destination buffer recording device 102 stores information when a branch is successful when a certain branch instruction is executed.
For example, in the case of Figure 2, 4 at point A in RTN,
Or, when the branch to point B, 5, is successful, the first associative key consisting of the information of the end address (RTN) of the subroutine SUBRT, which is the branch instruction address, is stored, and then the address 4 of the branch destination instruction is generated. A second associative key consisting of information for executing the branch instruction or a second associative key consisting of information for generating the address 5 of the branch destination instruction is stored.

Then, when the branch instruction is executed again, the pair of the first associative key and the second associative key is supplied to the branch destination buffer storage device 102 as an associative key, and an associative key that matches the supplied associative key is supplied. When a branch destination instruction having . is read, the branch instruction is predicted to be successful and the read branch instruction is executed. FIG. 4 is a detailed block diagram of the instruction processing device in FIG. 3.

FIG. 4 shows an instruction processing device including a branch destination buffer 102. The instruction processing device includes a branch destination buffer storage device 102, an instruction prefetch circuit 10, a memory 12, an instruction buffer 14 for buffering a group of prefetched instructions, an instruction register 15, selectors 11 and 13, and instructions in the instruction register 15 that are branch instructions. Branch instruction detection circuit 30 to check whether there is a branch instruction, selector switching circuit 32, decode switching circuit 34, general-purpose register 17, selectors 18, 19, address adder 20, memory 2
1, an execution unit (operating unit) 22, etc.

Next, the overall operation will be explained.

The instruction prefetch address for reading out a group of instructions is stored in advance in the instruction fetch address unit 10, and the selector 11 uses the output of the address adder 20 or the above instruction of the instruction fetch address unit 10 to perform the prefetch address.
One of the address outputs is selected to access the memory 12, and one instruction group is read out and stored in the instruction buffer 14. One instruction at a time is read out from the instruction buffer 14 to the instruction register 15, and displacement information within the instruction is transferred for use as one input of the address adder 20. The address of the instruction read from the instruction buffer 14 to the instruction register 15 is transferred to the branch destination buffer storage device 102 via the IC signal line 104.
will be sent to. At the same time, the displacement information in the branch instruction word is sent to the branch destination buffer storage device 102 via the DISP signal line 106. In addition, TI, IR,
BRN, GRN, GRX, GRB, and TKN are circuits that transfer information from the instruction processing device to the branch destination buffer storage device 102, as shown in FIG. The branch instruction detection circuit 30 decodes the instruction, and when it is a branch instruction, outputs '1' to the BRN signal line 108 to activate the branch destination buffer storage device 102.
In addition, the values of the base register and index register of the general-purpose register 17 are stored in the instruction register 1.
Selected by selectors 18 and 19 by the base field and index field in 5,
Further, it is added together with the displacement information in the address adder 20, and the result is transferred to the instruction fetch address unit 10 and selector 11, and becomes the address of the next target instruction. The address of this target instruction transferred to selector 11 is input to instruction storage unit 12 for fetching the instruction group containing the target instruction word.

The values of the base register and index register are output to the GRB signal line 110 and GRX signal line 112, respectively, and are sent to the branch destination buffer storage device 10.
2 is sent out. In the case of a normal instruction that is not a branch, the operand storage 21 is accessed by the output of the address adder 20, the operand is read out, and it is given to the execution unit 22 for execution.

The branch destination buffer storage device 102 is connected to the signal line 10
4, 106, 110, 112 as an associative key, a group of instructions including the corresponding target instruction word is transferred to the branch destination buffer storage device 10.
Check whether it is registered in 2. When registered, the branch destination buffer storage device 102
outputs '1' to the TKNP signal line 114, and also outputs a group of instructions including the target instruction word to the RTI signal line 11.
Output to 8. When the selector switching circuit 32 receives '1' from the signal line 114, it causes the selector 13 to select the right input via the control line indicated by a dotted line, and stores a group of instructions including the target instruction word in the instruction buffer 14.

Note that when the instruction group including the target instruction word is not registered in the branch destination buffer storage device 102, the branch destination buffer storage device 102
Output '0' to the TKNPS signal line 114.

When '0' is transferred via the signal line 114, the decode switching circuit 34 predicts that the branch instruction will not be taken and sets the signal line 40 to '0', so that the branch instruction next to the branch instruction in the instruction buffer 14 is The instruction is extracted to the instruction register 15 and its decoding is started.

On the other hand, when a '1' is transferred via the signal line 114, the signal line 40 is set to '1', the branch instruction is predicted to be taken, and the branch instruction is stored in the instruction buffer 14 via the signal line 118. The target instruction word in the instruction group containing the specified target instruction is extracted into the instruction register 15 and its decoding is started.

The execution unit 22 executes the branch instruction in parallel with the above decoding. Execution of the branch instruction is completed after a certain period of time from the start of decoding of the branch instruction, and a determination result of the branch instruction is obtained. Also, at the same time,
Based on the target address input from the address adder 20 to the instruction storage unit 12 via the selector 11, a group of instructions including the target instruction word is fetched.

When the branch is not taken, the execution unit 22
Output '0' to the TKN signal line 122. Furthermore, when a branch is established, '1' is output to the TKN signal line 122 and transferred to the branch destination buffer storage device 102.

Then, the instruction group including the target instruction word read from the instruction storage unit 12 is transferred to the branch destination buffer storage device 102 via the signal line 120.
Send to.

The branch destination buffer storage device 102 is connected to the signal line 12
A write cycle operation is performed based on the data transferred via 0 and 122.

The first important feature of the present invention is that even if the address of the branch destination instruction of the same branch instruction changes each time the branch instruction is executed, the branch destination instruction can be registered in the content addressable memory means. . And to make it reusable. That is, by using a second associative key consisting of information for generating the address of the branch destination instruction as part of the associative key and registering the branch destination instruction in the associative storage means, the branch destination of the same branch instruction Even if there may be multiple instructions, the currently required branch destination instruction can be read correctly from the associative memory device. Furthermore, if the branch of a branch instruction is successful, the branch destination instruction is registered, and when the branch instruction is executed again, if the branch destination instruction is registered in the associative memory means, the branch of that branch instruction is In other words, by executing this branch instruction, without waiting for the result of determining whether the branch was successful or not,
Starts execution of the branch destination instruction. Thereby, execution of the branch destination instruction can be started at high speed. In this way, in order to predict that the branch will be successful and execute the branch destination instruction, it is necessary to distinguish which branch instruction the branch destination instruction was for which the branch was successful. For this reason, in the implementation example, the first associative key consisting of the address information of the branch instruction is also registered in the associative memory means. By simply using the second associative key consisting of information for generating the address of a branch instruction, it is not possible to determine which branch instruction is the branch destination instruction to be executed if successful.

The present invention uses two associative keys in this way to avoid the above problems.

Furthermore, in this embodiment, since a plurality of branch destination instructions can be read out in advance at the first timing, the associative memory means can be accessed earlier, and as a result, the timing at which the branch destination instruction is finally read out can be adjusted. This makes it possible to start execution of the branch destination instruction earlier.

Next, the second most important function in the present invention will be explained.

When registering the branch destination instruction of a certain branch instruction in an associative memory means, if the address of the branch destination instruction is registered as an associative key, when the branch instruction is re-executed, the information specified by the branch instruction will be executed based on the information specified by the branch instruction. After calculating the branch destination instruction, it is necessary to supply the calculated branch instruction address to the associative storage means as an associative key.

In the case of the present invention, since the information on which address calculation is based need only be supplied as an associative key, the associative memory means can be accessed more quickly.

Furthermore, in the present invention, when the branch destination instruction of the re-executed branch instruction is registered in the associative memory means, the branch destination instruction is executed with the prediction that the branch of the branch instruction is successful. The earlier the branch destination instruction is read, the earlier the branch destination instruction can be executed.

FIG. 5 is a configuration diagram of a branch destination buffer storage device showing an embodiment of the present invention.

The branch destination buffer storage device 102 stores a group of instruction words of branch destination instructions that have taken a branch in the past, including the address of the branch instruction word that is an associative key, displacement information in the branch instruction word, and information on the base register and index register. It is memorized along with the value. The branch destination buffer storage device 102 predicts that each branch instruction will make the same determination as the previous execution of the branch instruction, and if the previous execution resulted in a determination of establishment, the branch destination buffer storage device 102 predicts that each branch instruction will make the same determination as the previous execution. Expect the same to run. Therefore, when a group of instructions including a target instruction word corresponding to an associative key of a certain branch instruction is stored in the branch destination buffer storage device, the branch instruction on which that associative key is based is predicted to be taken, and it is predicted that the associative key is not. Sometimes it is predicted that it will fail.

When a branch destination buffer storage device predicts that a certain branch instruction will not be taken, and the branch instruction actually becomes a branch failure, the contents of the branch destination buffer storage device do not change. In addition, if the branch destination buffer storage device predicts that the branch instruction will not be taken, but the branch instruction actually takes place, the instruction containing the target instruction word of the branch instruction The group and associative key are newly stored in the corresponding branch destination buffer storage device. If the branch destination buffer storage device predicts that a branch instruction will be taken, but the branch instruction actually becomes not taken, the instruction group including the target instruction word of the branch instruction and the corresponding The associated key is deleted from the branch destination buffer storage device. Furthermore, if the branch destination buffer storage device predicts that a branch instruction will be taken, and the branch instruction actually takes place, the instruction group containing the target instruction word of that branch instruction will be It is overwritten on the instruction group containing the used target instruction word.

As shown in FIG. 5, the branch destination buffer storage device includes RAMs 412, 236, selectors 208, 2
54,400,442,438, register 20
2,216,218,220,222,238,
262, 264, a control circuit 414, and other combinational logic circuits.

The RAM 412 stores a group of instructions including the upper 16 bits of the instruction address of a branch instruction that took a branch in the past, displacement information of the branch instruction word, values of the base register and index register, and the target instruction word. There is. RAM412 is TI
field, GRB field, GRX field, IR field, ICU field, and Valid field. The TI field contains the instruction group containing the above target instruction word, and the GRB field contains the value of the above base register.
The value of the index register is stored in the GRX field, the displacement information in the branch instruction word is stored in the IR field, and the upper 16 bits of the instruction address are stored in the ICU field.

Each field of RAM412 has 2 rows.
It has a column configuration of 65536 (2 to the 16th power).

When reading the RAM 412, the signal line 21
All rows in the column designated by 0 are read out at the same time, and when writing is started, writing is performed on the row designated by the signal line 212 in the column designated by the signal line 210.

In this embodiment, the configuration is 2 rows and 65536 columns, but it goes without saying that the configuration can be configured with any number of rows and any number of columns. In addition, in this embodiment, the lower 16 bits of the branch instruction address are
Any combination of the branch instruction address, displacement information in the branch instruction word, and bits in the base register value is used to determine the address.
It is clear that it can be used to determine column addresses.

Next, details of the operation of the branch destination buffer storage device will be explained.

The operation of the branch destination buffer storage device consists of read cycles and write cycles.

(a) Read Cycle The read cycle operation of the branch destination buffer storage device starts from the time when '1' is transferred to the control circuit 414 via the BRN signal line 108. The control circuit 414 includes RAMs 412, 236
, and outputs a left selection signal to the selector 208. In addition, registers 202, 216,
218, 220, and 222 are activated.

ICLI register 202 with write initiated
The IC signal line 104 is connected to the IC signal line 104 via the signal line 200.
The lower 16 bits of the branch instruction address on the IC signal line 104 are written to the ICUI register 222. Also,
Register 216, Register 218, Register 2
20, the value of the base register on the GRB signal line 110, the value of the index register on the GRX signal line 112, and the IR signal line 1, respectively.
The instruction word above 06 is written.

Also, data transmitted from the RAM 412 via the signal line 204, the selector 208, and the signal line 210
The data in the column specified by the lower 16 bits of the instruction address on IC signal line 104 is transferred to signal line 2.
40,268,270,272,274,27
6,278,280,282,284,28
6,292,294.

On the left side of the comparators 248 and 250, the signal line 1
Data numbers 10, 112, 106, 426, and 434 are input. Also, on the right side of the comparator 248, signal lines 284, 280, 276, 272,
268 data is input. On the right side of the comparator 520, signal lines 286, 282, 278, 27
4,270 data are input. Comparator 24
8,250 outputs '1' to the row 0 match signal line 306 and the row 1 match signal 308 when the right side input data and the left side data are equal, and outputs '0' when they are not equal. That is,
The upper 16-bit base register and index register values of the decoded branch instruction address, the branch instruction word, and the ICU field and GRB field read from row 0/row 1.
If the data in the GRX field and the IR field are equal, and the value in the Valid field is equal to '1', the comparator 248/250
Outputs 1', otherwise outputs '0'.

If the data in either row 0 or row 1 are equal as described above, that is, if a group of instructions including the target instruction word corresponding to the associative key is registered in the branch destination buffer storage device, row 0
Match signal line 306 or row 1 match signal line 30
8 becomes '1', the OR circuit 256 outputs '1' to the TKNP signal line 114, and the general-purpose copier 10
Transfer to 0.

Further, the encoder 258 sends the binary number of the row number in which the instruction group including the target instruction word corresponding to the associative key is registered to the row number signal line 35.
Output to 8. For example, if the target instruction word corresponding to the associative key is registered in row 1, the comparators 248 and 250 output '1' only to the row 1 match signal 308, and the encoder 2
58 outputs '1' to the row number signal line 358. The data of the row number signal line is the selector 254
The data on the signal line coming out from the registered row among the signal lines 292 and 294 is output to the PTI signal line 118. For example, if '1' is output on the signal line 358, data on the signal line 294 is output on the RTI signal line 118.

If no instruction group including the target instruction word corresponding to the associative key is registered in either row 0 or row 1, the signal lines 306 and 30
8 are both '0', and the OR circuit 256 is '0'.
0' is output to the TKNP signal line 114 and transferred to the general-purpose computer 100.

After '1' is input to the control circuit 414 via the BRN signal line 108, the read cycle operation is performed in this manner, and the signal lines 240, 4
22,424,114, row number signal line 358
control circuit 414 at the time when data is output to
starts writing to the RPLO register 262 and ROW#SV register 264. Write activated RPLO register 238, register 418,
420, HITSV register 262, ROW#SV
The data on the signal line 114 and the row 0 number signal line 358 are written into the register 264, respectively. The data written to each of the above registers is used in the write cycle described below.

(b) Write Cycle The relocation control data stored in the RPLO register 238 is input to the write row selection circuit 224 via the signal line 242. The write row selection circuit 224 is configured using a well-known relocation method such as a FIFO method or an LRU method, and selects a row to be written and sends the row number to the selector 400 via a signal line 402. Enter.

The data stored in register 418 is
It is input to the selector 400 via a signal line 408.

Data in register 420 is input to selector 400 via signal line 410. signal line 4
When '1' is input through signal line 10, selector 400 transfers the data on signal line 402 to signal line 4.
Output to 36. When '0' is input through the signal line 410, the selector 400 outputs the data on the signal line 408 to the signal line 436.

The data on the signal line 436 includes a group of instructions including the target instruction word in the branch destination buffer storage device and associative keys (first associative key and second associative key).
is the number of the row to be newly stored, and is input to the selector 438.

Data in the ROW#SV register 264 is input to the selector 438 via the signal line 356.

Data in the HITSV register 262 is input to the selector 348 via a signal line 354.

When '1' is input via the signal line 354, the selector 438 outputs the data on the signal line 356 to the signal line 212. When '0' is input via the signal line 354, the selector 43
8 outputs the data on the signal line 436 to the signal line 212. Data on signal line 212 is input to relocation control data update logic circuit 246 and RAM 412. The data on signal line 212 is the row number written to RAM 412 in a write cycle. Data from the RPLO register 238 is further input to the relocation control data update logic circuit 246 via a signal line 242. The relocation control data update logic circuit 246 is a FIFO
The relocation control data on the signal line 242 is updated based on the write row number on the signal line 212. The updated relocation control data is sent to the RAM 2 via the signal line 234.
36.

Furthermore, the value of the base register on the GRBI signal line 224, the value of the index register on the GRXI signal line 226, the instruction word on the IRI signal line 228, and the upper 16 bits of the branch instruction address on the ICUI signal line 230 are respectively RAM412
Input to GRB field, GRX field, IRI field, ICUI field.

In the arithmetic unit 22, a branch instruction is determined in the final cycle, the determination result is transferred to the branch destination buffer storage device via the TKN signal line 122, and when the branch is taken, the target instruction word is further transferred via the TI signal line 120. be transferred.

In synchronization with the above event, HITSV register 26
6 is '1' or the TKN signal line 122 is '1', a right selection signal is output to the selector 208, and writing to the RAM 412 is activated. Furthermore, when the signal line 122 is '1', the selector 4
A right selection signal is output to 42, and the TKN signal line 12
When 2 is '0', a left selection signal is issued.

Lower order of the instruction address on ICLI signal line 206
The 16 bits are input to RAM 412 via selector 208 and signal line 210.

GRB field, GRX field, IR field of RAM412 where writing was started,
The ICU field contains the base register value on the GRBI signal line, the instruction word on the IR signal line, and
and upper branch instruction address on the ICU signal line
When 16 bits are '1' in register 262,
It is written to the row of the row number indicated by register 264. When register 262 is '0',
The selected rows are written to using one of the known relocation methods such as LRU or FIFO. Since this relocation method has no direct relation to the present invention, further explanation will be omitted.

HITSV register 262 is '1', and
When TKN signal line 122'1', further
TI signal line 120 to TI field of RAM412
data is written. As a result, the instruction group including the target instruction word transferred via the TI signal line 120 is overwritten on the instruction group including the target instruction word read in the read cycle.

In addition, the HITSV register 262 is '1',
And when the TKN signal line 122 is '0', '0' is further written in the Valid field.
As a result, the instruction group including the target instruction word read in the read cycle and the corresponding associative keys (first associative key and second associative key) are deleted from the branch destination buffer storage device.

In addition, the HITSV register 262 is '0',
When the TKN signal line 122 is '1', the data of the TI signal line 120 is further written into the TI field, and '1' is written into the Valid field. As a result, the target instruction word and the corresponding associative key (the first associative key and the subsequent second associative key) are newly stored in the branch destination buffer storage device.

HITSV register 262 and TKN signal line 12
2 are both '0', nothing is done.

As described above, in the first invention of the present application, when a branch is successfully executed when a branch instruction is executed, a first associative key consisting of address information of the branch instruction and the address of the branch destination instruction are generated. A pair with a second associative key consisting of the information of A set of one associative key and a second associative key consisting of information for generating the address of the branch destination instruction specified by the instruction is supplied to the associative storage means as an associative key. Then, when a branch destination instruction having an associative key that matches the supplied associative key is read from the associative storage means, the branching of that branch instruction is predicted to be successful, and the branch destination instruction is executed.

Further, in the embodiment of the first invention, the first associative key is supplied to the associative memory means at the first timing, and the second associative key is supplied to the associative memory means at the second timing after the first timing. supply to storage means; When a first associative key consisting of address information of a branch instruction is supplied, the associative memory means stores a plurality of branch destination instructions having a first associative key that matches the first associative key. Detect. Further, when a second associative key consisting of information is subsequently supplied to generate the address of a branch destination instruction to be read, the supplied second associative key among the plurality of branch destination instructions detected One branch destination instruction having a second associative key matching is selected and supplied. Note that the first timing for supplying the first associative key to the associative memory means is before starting execution of a branch instruction, before decoding a branch instruction, or when reading a branch instruction; The second timing for supplying the key to the associative memory means is after starting execution of the branch instruction, after decoding the branch instruction, or after reading the branch instruction.

Further, in the second invention of the present application, information used to calculate the address of the branch destination instruction, that is, address information specified by the branch instruction, is used as an associative key for the associative memory means for storing the branch destination instruction. Then, when this branch instruction is re-executed, the information used to calculate the address of the branch destination instruction, that is, the address information specified by the branch instruction, is used as an associative key to read the branch destination instruction from the content addressable memory means. use.

Both the first and second inventions use an associative key consisting of information for generating the address of the branch destination instruction, and when the branch destination instruction is registered in the associative storage means, the branch instruction is branched. What they have in common is that they predict success and execute it.

〔Effect of the invention〕

As explained above, according to the present invention, even if the address of the branch destination instruction specified by the same branch instruction changes every time the branch instruction is executed, the branch destination instruction can be registered in the associative storage means. and can be reused. Furthermore, after registering the branch destination instruction of a branch instruction in the associative storage means, when the branch instruction is re-executed, the branch destination instruction of the branch instruction can be read out and executed at high speed.

[Brief explanation of the drawing]

1 and 2 are diagrams explaining the functions of a conventional root memory, FIG. 3 is a diagram of an interface between a branch destination buffer storage device and an instruction processing device showing an embodiment of the present invention, and FIG. This figure is a detailed block diagram of FIG. 3, and FIG. 5 is a block diagram of a branch destination buffer storage device showing one embodiment of the present invention. 10: Instruction fetch address unit, 1
1, 13: Selector, 12: Instruction storage, 1
4: Instruction buffer, 15: Instruction register, 17:
General-purpose register, 18, 19: Selector, 20: Address adder, 21: Operand storage,
22: Execution unit, 30: Branch instruction detection circuit,
32: Selector switching circuit, 34: Decode switching circuit, 100: Instruction processing device, 102: Branch destination buffer storage device, 104: IC signal line, 106:
DISP signal line, 108: BRN signal line, 110:
GRB signal line, 112: GRX signal line, 114:
TKNP signal line, 116: PTI signal line, 120:
TI signal line: 122: TKN signal line, 412, 23
6: RAM, 414: Control circuit, 248, 25
0: Comparator, 208, 254, 400, 442,
438: Selector.

Claims (1)

[Scope of Claims] 1. an associative memory means, a first associative key consisting of address information of a certain branch instruction, and an address for generating the address of the branch destination instruction when a branch is successful during the execution of a certain branch instruction. means for storing a pair with a second associative key consisting of information as an associative key together with the branch destination instruction in the associative storage means; and address information of the branch instruction when the branch instruction is executed again. means for supplying a set of a first associative key and a second associative key consisting of information for generating an address of a branch destination instruction specified by the branch instruction to the associative memory means as an associative key; When a branch destination instruction having an associative key that matches the associative key is read from the associative storage means, means for predicting that the branch of the branch instruction will be successful and executing the read branch destination instruction. An information processing device characterized by: 2. A first supply means, wherein the supply means supplies a part of an instruction address for reading the re-executed branch instruction from a memory in which the instruction is stored as a first associative key of the branch instruction; It is characterized by having a second supply means for supplying a plurality of operands read from the operand storage device as a second associative key of the branch instruction based on address information of a branch destination instruction specified by the branch instruction. An information processing device according to claim 1. 3. The address information of the branch destination instruction specified by the branch instruction includes the base register number, index register number, and displacement, and the plurality of pieces of address information are stored in the plurality of address information provided in the information processing device as an operand storage device. Among the registers, the contents of the first register having the number of the base register, and the contents of the second register having the number of the index register.
and the second supplying means comprises means for supplying the contents of the first and second registers as a second associative key. The information processing device described. 4. The means for supplying the set of associative keys includes means for supplying the first associative key to the associative memory means at a first timing, and means for supplying the second associative key to the associative memory means at a first timing after the first timing. and means for supplying the first associative key to the associative memory means at a timing of 2, and the associative memory means supplies a first associative key that matches the first associative key when the first associative key is supplied. When a plurality of branch destination instructions having a plurality of branch destination instructions are stored, a means for detecting the plurality of branch destination instructions, and a means for detecting the plurality of branch destination instructions when the second associative key is subsequently supplied. 2. The information processing apparatus according to claim 1, further comprising means for selecting and supplying one branch destination instruction having a second associative key that matches the second associative key. 5. Claim 4, wherein the first timing is before the start of execution of the re-executed branch instruction, and the second timing is after the start of execution of the branch instruction. information processing equipment. 6. The first timing is before the re-executed branch instruction is decoded, and the second timing is before the decoding of the re-executed branch instruction.
5. The information processing device according to claim 4, wherein the information processing device is processed after the branch instruction is decoded. 7. Claim 4, wherein the first timing is at the latest when the re-executed branch instruction is read from the instruction storage device, and the second timing is after the reading. The information processing device described. 8 The second supplying means stores the contents of the first register having the number of the base register specified by the branch instruction among the plurality of registers provided in the information processing device as operand storage devices, and also the contents of the index register. means for supplying the contents of a second register having a number and a displacement included in the branch instruction; the means for calculating the address of the branch destination instruction based on the supplied operand; , the means for adding the contents of the second register and the displacement, and the means for storing in the associative memory means at least one of the contents of the first and second registers supplied by the second supply means. as an associative key, and the means for supplying an associative key with respect to a re-executed branch instruction stores the associative key supplied from the second supply means for the re-executed branch instruction. 4. The information processing apparatus according to claim 2, further comprising means for supplying at least one of the contents of the first and second registers to the associative memory means.