JPH0557730B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device by forming a two-layer resist pattern consisting of an upper layer and a lower layer.

[Conventional technology]

Conventional examples of manufacturing semiconductor devices using resist include, for example, implantation of channel stop ions in a C-MOS manufacturing process and formation of contact holes and/or through holes in an interlayer insulating film.

Among these, in the C-MOS manufacturing process, channel strike ions are implanted after forming an element region on a substrate. That is, by implanting p-type impurity ions around the n-type transistor formation area, and by implanting n-type impurity ions around the p-type transistor formation area,
This prevents leakage between each transistor.

FIG. 2 shows an example of the steps performed in the conventional C-MOS manufacturing process, from the formation of an element region to the implantation of channel stop ions.

First, as shown in FIG. 2, an oxide film 2 and a nitride film 3, which will serve as a mask during selective oxidation, are sequentially deposited on a substrate 1, and then a resist layer is applied to the surface and patterned. A first resist pattern 20 composed of a resist mask on the upper part of the region
form.

Next, as shown in FIG. 2, the portions of the nitride film 3 where the first resist pattern 20 is not provided are removed by etching, and then the first resist pattern 20 is removed.

Next, as shown in Figure 3, using a resist,
A second resist pattern 21A for p-type channel stop ion implantation is formed, and p-type channel stop ions are implanted from above the pattern 21A using the n-type pure dopant 5a.

Subsequently, as shown in FIG. 4, after removing the second resist pattern 21A by etching, the resist is used to form a second resist pattern for implanting n-type channel resist ions.
A resist pattern 21B is formed, and the pattern 21
From above B, p-type channel stop ions are implanted using p-type impurity 5b.

Finally, resist pattern 21B and nitride film 3
is removed to complete the series of steps.

Next, a conventional example for forming a contact hole in an interlayer insulating film will be described.

In recent years, multilayer wiring has been used to improve the functionality of semiconductor devices. In this multilayer wiring structure, an insulating film is interposed between the conductive layers, and this insulating film is called an interlayer insulating film.

In the process of forming a contact hole in the manufacturing process of a semiconductor device, as shown in the cross-sectional view of the process in FIG. An insulating film 31 is formed as an insulator. Next, as shown in FIG. 2, a resist layer is applied on the interlayer insulating film 31 and patterned to form a resist pattern 32. This resist pattern is then used as a mask to form a resist layer on the interlayer insulating film 31.
1 is etched to form a contact hole 33.

[Problem to be solved by the invention]

In the conventional C-MOS manufacturing method shown in FIG. 2, the insulating film consisting of the oxide film 2 and the nitride film 3 on the element region serves as a mask during channel stop ion implantation. As shown in the figure, the nitride film 3 (Si ₃ N ₄ )/
A two-layer film of oxide film 2 (SiO ₂ ) has been used.

However, in the case of a two-layer film of Si ₃ N ₄ /SiO ₂ ,
If SiO ₂ is made thicker, _the bird's peak will become larger when selective oxidation (LOCOS) is performed, making it unsuitable for device miniaturization and even _higher device performance.
When the film is formed thickly, the stress of the film causes the Si substrate 1 to
There has been a problem of deterioration of semiconductor device performance, such as the occurrence of defects in semiconductor devices. Therefore, in this conventional example, in order to realize a high-performance semiconductor device, the Si ₃ N ₄ /SiO ₂
A great deal of effort has been spent on determining and controlling the thickness of the layer.

Alternatively, a three-layer multilayer film of PSG/Si ₃ N ₄ /SiO ₂ can be used as a mask for channel stop ion implantation, but this increases the number of steps such as PSG film formation and etching, resulting in higher costs and lower yields. was.

Further, the conventional example shown in FIG. 3 for forming a contact hole in an interlayer insulating film has the following problems.

In recent years, as large-scale integrated circuits have become more highly integrated and faster, the dimensions of through holes and contact holes have become smaller, and interlayer insulating films have become thicker. The contact hole created using the conventional method has a large depth, and due to the small size of the contact hole, the adhesion of the wiring metal to the side wall of the hole is poor (poor coverage of the wiring layer), and the wiring layer There was a problem with the wire breaking.

Therefore, in order to solve this problem of wire breakage, there is a conventional example in which the etching is divided into two stages, isotropic and anisotropic, and a tapered wine glass-shaped contact hole is formed to prevent the wire breakage. do. However, this conventional example requires a special etching device, and the operation for forming the hole is complicated.

Another conventional method for tapering a contact hole is to taper the resist and then etch the interlayer insulating film, but it is difficult to accurately control the taper of the resist during etching. .

The various conventional examples described above have a problem in that it is difficult to provide high performance semiconductor devices with simple operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a high-performance semiconductor device with simple operations by using a plurality of resists.

[Means to solve the problem]

In order to achieve the above object, the invention according to claim 1 includes a step of forming an insulating film on a substrate, a step of forming a lower resist pattern on the insulating film, and a polymerization treatment on the lower resist pattern. A method of manufacturing a semiconductor device is characterized in that it comprises a step of forming an upper resist pattern on a lower resist pattern.

Further, the invention according to claim 2 which achieves the above object includes a step of forming an insulating film on a substrate, a step of forming a lower resist pattern on the insulating film, and a step of performing a polymerization treatment on the lower resist pattern. , a step of forming an upper resist pattern on the lower resist pattern, a step of ion implantation using the upper resist pattern and the lower resist pattern as masks, and a step of removing only the upper resist pattern and forming an upper resist pattern again on the lower resist pattern. A method of manufacturing a semiconductor device, which also achieves the above object, comprises the steps of: forming an insulating film on a substrate; and forming an insulating film on a substrate. forming a lower resist pattern having holes thereon;
a step of subjecting the lower resist pattern to polymerization treatment;
forming an upper resist pattern on the lower resist pattern, which has a hole that is continuous with the hole formed in the lower resist pattern and has a diameter different from that of the hole; This method of manufacturing a semiconductor device is characterized by comprising the step of transferring the shape of the step-like hole formed on the insulating film to the etched shape of the insulating film and opening the insulating film.

[Effect]

According to the manufacturing method according to claim 1, since the lower resist pattern is subjected to polymerization treatment,
For example, the lower resist pattern has the property of being insoluble in a solvent that is soluble in resist that has not been subjected to polymerization treatment, or the coating, exposure, and exposure of the upper resist pattern formed on the lower resist pattern.
It becomes possible to obtain various properties such as the property that the underlying resist pattern does not deform even when the phenomenon is performed. Therefore, if these characteristics are utilized in the manufacture of semiconductor devices, high performance semiconductor devices can be manufactured with simple operations.

That is, the invention according to claim 2 utilizes the property that the polymerized lower resist pattern is insoluble in a solvent in which the unpolymerized upper resist pattern is soluble. Therefore, during etching, only the upper resist pattern can be removed while the lower resist pattern remains as it is without being etched, and then the upper resist pattern can be recoated. Since the lower resist pattern serves as a mask during ion implantation, it is possible to form a thin insulating film consisting of two layers, an oxide film and a nitrogen film. As a result, it is possible to miniaturize the device, eliminate the risk of deterioration in the performance of the semiconductor device such as defects on the substrate, and simply provide a lower and upper layer resist pattern and then polymerize the lower layer resist pattern. High performance semiconductor devices can be manufactured by this operation.

Further, the invention as claimed in claim 3 utilizes the property that the polymerized lower resist pattern does not deform even when the upper resist pattern is coated, exposed, and developed. Therefore, there is no deformation in the diameter of the hole formed in the lower resist pattern, and as a result, step-like holes can be formed with good shape accuracy from the lower resist pattern to the upper resist pattern. A stepped contact hole and/or a through hole can be formed in the insulating film by simply transferring the stepped hole to the insulating film. Therefore, the operation for forming step-like holes is easy, and the formed holes have good shape accuracy, so that the simple operation of forming lower and upper layer resist patterns and polymerizing the lower layer resist pattern is possible. Accordingly, it is possible to manufacture a high-performance semiconductor device having step-like holes with good shape accuracy while preventing disconnection of the wiring pattern.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Figure 1 shows the steps in manufacturing a C-MOS integrated circuit.
FIG. 3 is a cross-sectional view showing a process from forming an element region to implanting a channel stop ion.

First, the process shown in FIG. 1(1) will be explained.

A silicon oxide film 2 and a silicon nitride film 3, which are insulating films, are formed on a silicon substrate 1.

Next, a resist is applied onto the nitride film 3 by a spin coating method, and exposed and developed using a predetermined mask. In this way, the lower resist pattern (element region) 4a is formed.

In this embodiment, this lower resist pattern 4a
A photopolymerizable novolak resist (manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR8600 (trade name)) was used.
Next, the lower resist pattern 4a was irradiated with ultraviolet light of 3200 nm or less, preferably 220 to 320 nm, to cause photopolymerization of the lower resist pattern 4a.

Next, as shown in FIG. 2, the nitride film 3 is removed by etching using the polymerized lower resist as a mask.

Subsequently, the process moves to the step shown in FIG. By applying the same resist as the lower layer resist to the surface by a spin coating method, and performing development and exposure using a predetermined mask, the upper layer resist pattern 4b for p-type channel strike ion implantation is changed to the lower layer resist pattern 4a. Form on top. After this, n
A p-type channel stop ion is implanted using the type impurity 5a. At this time, the upper resist pattern 4b and the lower resist pattern 4a act as a mask for the p-type channel strike ion implantation, so that the upper resist pattern 4b and the lower resist pattern 4a are not formed on the part of the substrate 1 where the upper resist pattern 4b and the lower resist pattern 4a are not formed. An implantation of the type channel stupion is performed. Next, the upper resist pattern 4b is removed using an organic solvent such as acetone. At this time, since the lower resist pattern 4a has been subjected to the polymerization treatment in step (2), it remains as it is without being removed. On the other hand, the upper resist pattern 4b, which has not been subjected to such polymerization treatment, is soluble in organic solvents.
Only the upper resist pattern 4b is removed.

Next, proceeding to the step shown in FIG. 4, an upper resist pattern 4c for implanting n-type channel stop ions is formed by the same method as explained in step (3) above. Next, n-type channel stop ion implantation is performed using p-type impurity 5b. In this case, (3) above
Similarly to the process described in (2), the lower resist pattern 4a and the upper resist pattern 4c act as a mask for the n-type channel stop ion implantation.

Next, after the n-type channel resist ion injection is completed, the resist patterns 4a and 4c are removed in the same manner using an asher or a chemical such as sulfuric acid that can also dissolve the polymerized lower resist pattern 4a, and the series of steps is repeated. finish.

Through the steps (3) to (4) in FIG. 1, the upper resist pattern 4b is removed, and the upper resist pattern 4
When forming c, the lower resist pattern 4a is
Because it is polymerized, it remains as it is without being etched, and acts as a mask when implanting channel stop ions. In this way, by performing a polymerization treatment after forming the lower resist pattern, the etching resistance is improved compared to the subsequently formed upper resist pattern, making it possible to apply and remove only the upper resist pattern multiple times. It made it possible.

On the other hand, according to the conventional semiconductor device manufacturing method explained in FIG. removed. Therefore, since the oxide film 2 and/or the nitride film 3 serve as a mask during channel stop ion implantation, the oxide film and/or the nitride film 3 must be formed thick. On the other hand, according to the method of this embodiment, since the lower resist mask 4a is insoluble in the etching solution, it is possible to form the oxide film 2 and the nitride film 3 thinly, which facilitates miniaturization of the device. This can be achieved, and defects may occur on the substrate 1, etc.
The problem of performance deterioration of semiconductor devices can be avoided. Furthermore, since there is no need to use a multilayer film of three or more layers as an insulating film, it is possible to manufacture semiconductor devices without increasing manufacturing costs or decreasing yield.

In the embodiment shown in FIG. 1, the polymerization treatment of the lower resist pattern 4a was performed immediately after the formation of the lower resist pattern in the process shown in FIG. It is also possible to do this later.

Next, a second embodiment will be described.

FIG. 4 is a cross-sectional view showing the step of forming a step-like contact hole in an interlayer insulating film that is unlikely to cause disconnection of the wiring pattern.

First, to explain step (1), an electrode pattern 30 is formed on the surface of the silicon substrate 1 using a normal patterning technique. This electrode pattern can be formed by aluminum wiring or other crystalline silicon wiring. Next, using these electrode patterns and the silicon substrate 1 as a base layer, an insulating film made of, for example, a silicon oxide film is formed on top of the base layer, and this insulating film becomes an interlayer insulating film 31 between the upper wiring and the upper wiring.

Next, the process moves to step (2), and a resist similar to that described in FIG.
OFPR8600 (trade name)) is applied by spin coating, exposed and developed to form a lower resist pattern 4a that determines the lower end dimension of the contact hole 50. A first hole 40 for forming a contact hole in the interlayer insulating film 31 is formed in the lower resist pattern 4a. and,
This lower resist pattern 4a was irradiated with ultraviolet light of 320 nm or less to polymerize the lower resist.

In step (3), the same resist as the lower layer resist is applied, and exposure and development are performed using the same mask as the lower layer resist pattern to form the upper layer resist pattern 4b. Then, in this upper layer resist pattern, a second hole 41 for forming a contact hole is formed in succession to the first hole 42 . When forming the upper resist pattern 4b, if overexposure is used to increase the exposure intensity,
Since a hole 41 having a larger diameter than the previously formed hole 40 can be formed, the first hole 40 and the second hole 41 are combined into a stepped shape from the lower resist pattern 4a to the upper resist pattern 4b. A contact hole forming hole 43 is formed.

When forming the upper resist pattern 4b on the lower resist pattern 4a, since the lower resist pattern has been subjected to a polymerization treatment, it is important to avoid deformation of the lower resist pattern even when the upper resist pattern is coated, exposed, and developed. It can be avoided. As a result, the first hole 40 formed in the lower resist pattern is not deformed, and the contact hole forming hole 43 can be formed in a stepped shape with high precision.

On the other hand, if the lower resist pattern 4a is not subjected to polymerization treatment, the lower resist pattern will be deformed due to the side effects of the solution and light during coating, exposure, and development of the upper resist pattern 4b, and as a result, the lower resist pattern will be formed. The shape of the hole 40 is also deformed. When such hole deformation occurs, the shape accuracy of the contact hole 50 transferred to the interlayer insulating film 31 decreases, making it difficult to form a stepped contact hole with good shape precision in order to prevent the wiring pattern from breaking. becomes.

Next, when moving to step (4), CHF ₃ or C ₂ F ₆
Dry etching (for example, reactive ion etching) is performed using an etching gas such as etching gas as a raw material. At this time, if the etching selectivity between the upper and lower resist layers and the interlayer insulating film is appropriately designed, the shape of the contact hole forming hole 43 will be transferred to the etched shape of the interlayer insulating film.

The selection ratio can be designed by adding O ₂ gas to the etching gas. _O2
Increasing the concentration increases the etching rate of the resist compared to the interlayer dielectric. If the etching rate of the resist is higher than the etching rate of the interlayer insulating film, or vice versa, the shape of the contact hole forming hole formed in the resist will not be accurately transferred to the etched shape of the interlayer insulating film.

In the step (4), the lower resist pattern 4a
The flange 44 formed at the upper end blocks the ions passing through the second hole 41 with a large diameter formed in the upper resist pattern 4b and irradiating the substrate 1 in the vertical direction. Then, a hole 51 having a small diameter corresponding to the diameter of the first hole 40 formed in the lower resist pattern 4a is formed in the interlayer insulating film 31. If etching is continued as it is, the lower resist pattern below the flange portion 44 will be etched until the hole 40 in the lower resist pattern has the same diameter as the hole 41 in the upper resist pattern. From the point at which the holes 40 in the lower resist pattern are etched until they become the same as the holes 41 in the upper resist pattern, etching is performed on the interlayer insulating film 31 to enlarge the diameter of the hole 51 in the small diameter portion;
A large diameter hole 52 is formed in this etched portion.

At this time, by measuring the etching rate of the interlayer insulating film 31 in advance, the formation depth of the hole in the large diameter portion is stopped at an appropriate point, and the shape of the contact hole formation hole 43 formed in a stepwise manner is A stepped contact hole 50 can be formed by transferring the interlayer insulating film into an etched shape.

The depth of the large diameter portion 52 of the contact hole 50 can be appropriately designed by controlling the etching time as described above. If the etching time exceeds a predetermined value, the formation depth of the large diameter portion 52 will reach the electrode pattern 40, making it impossible to form the contact hole 50 in a stepwise manner, making it difficult to manage the etching time. It becomes necessary.

Thereafter, in step (5), the upper and lower resist patterns are etched using a chemical that can also dissolve the asshered or polymerized lower resist pattern, similar to the step (4) in FIG. After this, inside the contact hole 50 and the interlayer insulating film 3
A desired wiring pattern is formed on 1. Since the contact hole has a step-like shape, the coverage of the wiring layer is good, and a high-performance semiconductor device without fear of disconnection of the wiring pattern can be manufactured by simple operations.

In each of the above examples, a novolac type resist was used as a resist for polymerization treatment, but not only a novolac type resist, but other resists may be used if the removability differs depending on the presence or absence of polymerization treatment. be able to.

Further, in each of the above examples, the lower resist mask was polymerized by irradiating it with ultraviolet rays, but the present invention is not limited to this, and polymerization can be performed by heat treatment, etc.
Other means of polymerization can also be used.

Furthermore, in the embodiment shown in FIG.
I explained the case of manufacturing MOS integrated circuits, but
Without being limited thereto, the present invention can also be applied to the manufacture of various semiconductor devices such as p-channel, n-channel MOS integrated circuits, and bipolar integrated circuits.

In addition, in the example shown in FIG. 4, the diameter of the hole in the upper resist pattern was formed larger than that in the lower resist pattern. can be formed smaller than the caliber of the

〔Effect of the invention〕

As explained above, according to the invention of claim 1, as a result of the polymerization treatment applied to the lower resist pattern, for example, the lower resist pattern has a property that it becomes insoluble in an etching solution, or the lower resist pattern does not deform. Characteristics etc. can be given.

According to the second aspect of the invention, a polymerization process is applied to the lower resist pattern to make the lower resist pattern insoluble in an etching solution, thereby forming a thin insulating film to serve as a mask during ion implantation. Accordingly, it is possible to provide a method for manufacturing a high-performance semiconductor device with simple operations.

Furthermore, the invention as claimed in claim 3 utilizes the property that the lower resist pattern is not deformed by performing a polymerization process on the lower resist pattern, and forms a stepped contact with good shape accuracy in preventing wiring patterns from being disconnected using a simple device. A method for manufacturing a high-performance semiconductor device having holes can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views showing the manufacturing process of a semiconductor device according to the prior art, and FIG. The figure is a cross-sectional view showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention. In the figure, 1 is a substrate, 2 is an oxide film, 3 is a nitride film, and 4
a is a lower resist mask, 4b and 4c are upper resist masks, 40 is a first hole (a hole formed in the lower resist pattern), 41 is a second hole (a hole formed in an upper resist pattern), and 43 is a A hole for forming a contact hole, 50 is a contact hole,
It is.

Claims (1)

[Claims] 1. A step of forming an insulating film on a substrate, a step of forming a lower resist pattern on the insulating film, a step of performing a polymerization treatment on the lower resist pattern, and a step of forming an upper resist pattern on the lower resist pattern. A method for manufacturing a semiconductor, comprising the steps of forming a resist pattern. 2. A step of forming an insulating film on a substrate, a step of forming a lower resist pattern on the insulating film, a step of performing polymerization treatment on the lower resist pattern, and a step of forming an upper resist pattern on the lower resist pattern. , a step of implanting ions using the upper resist pattern and the lower resist pattern as masks, and a step of removing only the upper resist pattern and forming an upper resist pattern again on the lower resist pattern. Method of manufacturing the device. 3. A step of forming an insulating film on a substrate, a step of forming a lower resist pattern having holes on the insulating film, a step of performing a polymerization treatment on the lower resist pattern, and a step of forming an insulating film on the hole formed in the lower resist pattern. A step of forming an upper resist pattern having a continuous hole having a diameter different from that of the hole on the lower resist pattern, and insulating the shape of the stepped hole formed from the lower resist pattern to the upper resist pattern. 1. A method of manufacturing a semiconductor device, comprising the steps of transferring the etched shape of the film and opening holes in the insulating film.