JPH0557735B2 - - Google Patents

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing semiconductor devices such as MOS FETs, and particularly relates to a method for manufacturing a semiconductor device such as a MOS FET, and in particular a method for selectively growing a high melting point metal layer on a diffusion layer. The present invention relates to a method of manufacturing a semiconductor device for forming a shallow diffusion layer with low sheet resistance.

(Prior Art) In recent years, in order to achieve higher integration and higher performance of LSIs due to miniaturization of semiconductor elements, it has been required to form a shallow diffusion layer with low sheet resistance. Conventionally, as a method for manufacturing a semiconductor device that satisfies these factors, a method has been used in which a high melting point metal layer is selectively grown on a diffusion layer. That is, even if the diffusion layer is formed shallowly, the sheet resistance of the diffusion layer can be reduced by the high melting point metal layer.Such a semiconductor device is, for example, shown in FIGS.
It is formed by the process shown in . Figure 2 a-f
takes a CMOS type MOS FET having an LDD structure as an example of this type of semiconductor device, and sequentially shows its manufacturing process. First, as shown in Fig. a, a p-type well region 2 is formed in the surface region of an n-type silicon substrate 1, and then an element isolation region 3 is formed by the LOCOS method. Then Hl or
Perform diluted oxidation using Ar, silicon substrate 1
A thin oxide film 4 that will serve as a gate insulating film is formed on top and well region 2. Next, as shown in figure b, the polycrystalline silicon layer 5 is deposited with a thickness of 4000 nm by the LPCVD method.
Deposits of about Å are formed. Next, the polycrystalline silicon layer 5 is patterned to form gate electrodes 5a and 5b, and using these gate electrodes 5a and 5b as masks, for example, a region where an n-channel type MOS FET is to be formed (n-channel region) Qn is patterned. phosphorus,
For example, boron ions are implanted into a region Qp where a p-channel type MOS FET is to be formed (p-channel region). As a result, low concentration diffusion layers 6, 6 and 7, 7 for alleviating electric field concentration in the vicinity of the drain region are formed as shown in Figure c. Next, as shown in Figure d, a silicon oxide film 8 having a thickness of, for example, 1500 Å is deposited over the entire surface using the CVD method. Subsequently, the silicon oxide film 8 is removed by anisotropic etching, and the gate electrodes 5a, 5 are etched.
The silicon oxide films 8a, 8 are formed only on the side wall portions b.
a, 8b, and 8b remain. Then, the gate electrode 5a, silicon oxide films 8a, 8a, and the gate electrode 5b, silicon oxide films 8b, 8b.
As a mask, phosphorus (p) is placed in the n-channel region Qn.
Alternatively, arsenic (As) is ion-implanted, and boron (B) or boron fluoride (BF ₂ ) is implanted in the p-channel region Qp.
After ion implantation, heat treatment is performed to form diffusion layers 9, 9, 1 as source and drain regions.
0 and 10 are formed (Fig. e). Thereafter, dilute hydrogen fluoride (dilute HF) treatment is applied to the gate electrodes 5a and 5b made of polycrystalline silicon and the source.
The oxide film remaining on drain regions 9, 9, 10, and 10 is removed. Then, by reacting tungsten hexafluoride (WF ₆ ) and silicon in an argon (Ar) atmosphere at 550°C,
Tungsten is selectively grown on the source and drain regions 9, 9, 10, 10 and on the gate electrodes 5a, 5b to form tungsten layers 11, 11,
... to form. Thereafter, although not shown, an interlayer insulating film is formed on the entire surface, and contact holes are formed on the source, drain regions and gate electrodes of each MOS FET, and then, for example, aluminum wiring is formed to connect the source, drain and gate electrodes. Derive
A CMOS type MOS is created by forming a passivation film.
Completes a semiconductor device with FET.

However, in the manufacturing method described above, the diffusion layers 9, 9, 10,
The high melting point metal layer 11 used to reduce the sheet resistance of No. 10 is manufactured during the manufacturing process (manufacturing conditions during selective growth).
The high melting point metal layer 1 grows along the interface between the element isolation region 3 and the silicon substrate 1 due to fluctuations in the
1 and the silicon substrate 1 or the p-well region 2, which has the drawback of lowering the manufacturing yield. This phenomenon is a problem not only in the manufacturing process of the CMOS type MOS FET mentioned above, but also in all semiconductor devices that have an element isolation region and in which a high melting point metal layer is formed by selective growth on a diffusion layer. , countermeasures are desired.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing method, a high melting point metal layer grows along the interface between the element isolation region and the silicon substrate or well region.
There is a drawback that the high melting point metal layer and the silicon substrate or well region are short-circuited, resulting in a decrease in manufacturing yield.

Therefore, an object of the present invention is to provide a semiconductor device that can prevent short-circuiting between the high-melting point metal layer and a silicon substrate or a well region even if the high-melting point metal layer is selectively grown on a diffusion layer, thereby improving manufacturing yield. An object of the present invention is to provide a manufacturing method.

[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in order to achieve the above object, in this invention, an element isolation region is formed on a semiconductor region of a first conductivity type; After forming a second conductivity type diffusion layer in contact with the element isolation region in the surface region of the semiconductor region, a refractory metal is deposited on the diffusion layer while masking the interface between the element isolation region and the diffusion layer. A second conductivity type silicon layer is formed by selectively growing silicon on the masked portion of the diffusion layer on the interface between the element isolation region and the diffusion layer.

In this manufacturing method, a high melting point metal layer is selectively grown on the interface between the element isolation region and the diffusion layer, which is a problem due to growth of the high melting point metal, while being masked.
After that, silicon is selectively grown in the offset region of the high melting point metal layer created by applying this mask to form a silicon layer, so the high melting point metal layer grows at the interface between the element isolation region and the diffusion layer. This prevents short-circuiting between the high melting point metal layer and the silicon substrate or well region.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1a and 1b show a part of the manufacturing process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
A CMOS type MOS FET with a structure is shown as an example. The steps up to FIG. 1a are the same as the conventional manufacturing steps shown in FIGS. 2a to 2e. Briefly, an n-type silicon substrate 1
p-type well region 2 and
After forming the element isolation region 3 using the LOCOS method,
A p-channel MOS is fabricated on a silicon substrate 1 through a self-alignment process using polycrystalline silicon.
FET, n-channel MOS on well region 2
The FETs are formed respectively to obtain a configuration as shown in FIG. 2e. Then, as shown in Figure 1a,
a diffusion layer 9 as a source or drain region;
Masks 12, 12 having a width of about 1 μm are formed on the interfaces with the element isolation regions 3 on the layers 9, 10, 10. As this mask material, for example, a silicon oxide film may be used. Next, by reacting tungsten hexafluoride (WF ₆ ) and silicon (Si) in an argon (Ar) atmosphere at about 550° C., the diffusion layers 9, 9, 10, 10 and the gate electrode 5a, Tungsten layer 11,1 on 5b
1,... are selectively grown to a thickness of about 200 Å. Thereafter, the masks 12, 12 are removed, and an offset region is formed between the element isolation region 3 and the high melting point metal layer 11. Next, as shown in FIG. 1b, silicon layers 13 and 14 are formed to a thickness of about 200 Å in the offset region between the element isolation region 3 and the high melting point metal layer 11 using, for example, selective vapor deposition. Selective growth to form. At this time, each silicon layer 13, 14
must be of the same conductivity type as the diffusion layers 9 and 10 below, so for example, reactant gases of SiH ₂ Cl ₂ and HCl are heated at a pressure of 100 torr in an H ₂ gas atmosphere.
The flow may be carried out at a temperature of 900° C., and PH ₃ gas may be used as the doping gas for the n-channel region Qn, and B ₂ H ₆ gas may be used for the p-channel region Qp. As a result, the silicon layer 13 on the n-type diffusion layer 9 becomes the silicon layer 13 on the n-type and p-type diffusion layers 9.
4 becomes p-type.

According to such a manufacturing method, the high melting point metal layer 1
1, 11... are source and drain regions 9, 9, 1
0 and 10 and on the gate electrodes 5a and 5b, the interface between the silicon substrate 1 or the well region 2 and the element isolation region 3 is masked, so there is some inconvenience in the manufacturing process. Even if fluctuations occur, the high melting point metal will not grow along the interface between the element isolation region 3 and the silicon substrate 1 or the well region 2. Therefore, the high melting point metal layer 1
1, 11, . . . and the silicon substrate 1 or the well region 2 can be prevented, and shallow diffusion layers 9, 9, 10, 10 with low sheet resistance can be formed. This makes it possible to improve manufacturing yields and to achieve higher integration and higher performance of LSIs due to miniaturization of semiconductor elements.

In addition, in the above example, it has an LDD structure.
Although the manufacturing process of a CMOS type MOS FET has been described as an example, the present invention is not limited to the above-mentioned embodiments, and has an element isolation region and selectively grows a high melting point metal layer on a diffusion layer. It can be applied to any semiconductor device that has a process. Further, although the case where tungsten is used as the high melting point metal has been described as an example, titanium (Ti), molybdenum (Mo), vanadium (V), etc. may also be used. Furthermore, in order to make the silicon layer formed on the diffusion layer the same conductivity type as the diffusion layer, impurities were mixed into the doping gas, but ion implantation was performed after the formation of the silicon layer (in which no impurities were introduced). It's okay. Also, simply forming a silicon layer can
In the subsequent heat treatment step, impurities in the diffusion layer seep out and are introduced into the silicon layer, so each silicon layer has the same conductivity type as the diffusion layer below it.

[Effects of the Invention] As explained above, according to the present invention, even if the high melting point metal layer is selectively grown on the diffusion layer, short circuit between the high melting point metal layer and the silicon substrate or well region can be prevented, and the manufacturing process can be improved. A method for manufacturing a semiconductor device that can improve yield can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon substrate, 2... Well region, 3...
...Element isolation region, 9,9,10,10...Diffusion layer (source, drain region), 11,11...High melting point metal layer, 12...Mask (silicon oxide film), 1
3, 14...Silicon layer.

Claims (1)

[Claims] 1. A step of forming an element isolation region on a semiconductor region of a first conductivity type, and a step of forming a diffusion layer of a second conductivity type in contact with the element isolation region in a surface region of this semiconductor region. and forming a high melting point metal layer for reducing the sheet resistance of the diffusion layer by selectively growing a high melting point metal on the diffusion layer while masking the interface between the element isolation region and the diffusion layer. and a step of selectively growing silicon on the masked portion of the diffusion layer on the interface between the element isolation region and the diffusion layer to form a silicon layer of a second conductivity type. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor region is a silicon substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor region is a well region formed in a silicon substrate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion layer is a source or drain region of a MOS FET. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal layer is made of tungsten, titanium, molybdenum, or vanadium. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the mask is made of a silicon oxide film. 7 The silicon layer of the second conductivity type is formed by selectively growing silicon on the interface between the diffusion layer and the element isolation region, and impurities in the diffusion layer are introduced in a subsequent heat treatment step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by: 8. The silicon layer of the second conductivity type is formed by mixing an impurity forming the second conductivity type into the reaction gas when selectively growing silicon on the diffusion layer. A method for manufacturing a semiconductor device according to claim 1. 9. The silicon layer of the second conductivity type is formed by selectively growing the silicon layer on the diffusion layer and then ion-implanting an impurity forming the second conductivity type. A method for manufacturing a semiconductor device according to claim 1.