JPH0558264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device composed of MOSFETs (insulated gate field effect transistors).

A substrate bias voltage generation circuit for supplying a bias voltage _VBB to the substrate of a MOS-IC chip generally includes an oscillation circuit, an amplifier for amplifying the output signal of this oscillation circuit, and a DC bias voltage generator from the output signal of this amplifier. It consists of a pump circuit for generating voltage, and these are mounted on an IC chip.

The substrate bias voltage generation circuit is provided to apply a bias voltage V _BB to the P-type substrate of a conventional N-channel MOS memory IC, and by applying this bias voltage V _BB , the N-channel
Efforts are being made to control MOSFET threshold voltage V _th and reduce junction capacitance to achieve faster operation.

Conventionally, the above-mentioned oscillation circuit uses a ring oscillator in which an odd number of stages of inverters are connected in series in a ring shape. And these inverters are N
An NMOS inverter composed of a channel load MOSFET and an N-channel drive MOSFET was used.

However, the load that makes up the NMOS inverter
Since a substrate bias voltage V _BB is applied to the substrates of the MOSFET and drive MOSFET, if the substrate bias voltage V _BB changes, the threshold voltage of the load MOSFET and drive MOSFET will change due to the substrate effect. V _th varies and due to this the load
Conductance gm of MOSFET and drive MOSFET
changes. As a result, the rise speed of the inverter output signal fluctuates due to fluctuations in the conductance gm of the load MOSFET.

On the other hand, the fall speed of the inverter output signal fluctuates due to fluctuations in the conductance gm of the drive MOSFET. In other words, as shown in Figure 1, in each inverter, as the conductance gm of the load MOSFET increases, the rise becomes faster as shown by the dotted line, and conversely, as the conductance gm of the load MOSFET increases,
As gm becomes smaller, the rise becomes slower as shown by the dashed line.

On the other hand, as the conductance gm of the drive MOSFET increases, the fall speed becomes faster as shown by the dotted line.
Conversely, when the conductance gm becomes smaller, the fall becomes slower as shown by the dashed line. Therefore, such fluctuations in the rise and fall speeds of the inverter output signal both lead to fluctuations in the oscillation frequency of the ring oscillator configured by these inverters, and the stabilization of the oscillation frequency and, ultimately, the substrate bias voltage are affected. This poses a problem in terms of stabilization.

An object of the present invention is to provide a semiconductor integrated circuit device in which the substrate bias voltage V _BB is stabilized.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

Figure 2 shows a negative bias voltage -V _BB on a P-type substrate.
FIG. 2 is a circuit diagram showing an embodiment of a substrate bias voltage generation circuit for supplying the voltage.

MOSFETQ ₁ to Q ₁₃ and MOS capacitance C ₁ to
_C3 is the well-known CMOS (complementary metal-insulator semiconductor)
With integrated circuit technology, it is mounted on a semiconductor integrated circuit device that requires a substrate bias voltage. In this example, in order to stabilize the substrate bias voltage,
A substrate bias voltage generation circuit is configured by a CMOS circuit.

Three CMOS inverters are configured by N-channel MOSFETs Q ₁ to Q ₃ and P-channel MOSFETs Q ₄ to Q ₆ . These inverters are connected in series in a ring to create a ring oscillator.
OSC is configured. Note that in this embodiment, although not particularly limited, the N-channel MOSFET is
Formed on a P-type substrate, P-channel MOSFET
is an N-type well separated from a P-type substrate.
formed within.

The above ring oscillator OSC uses a P channel as a resistance means to lower the oscillation frequency.
MOSFETQ ₇ and Q ₈ are inverters (Q ₁ ,
Q ₄ ) and (Q ₂ , Q ₅ ) and (Q ₂ , Q ₅ ) and (Q ₃ , Q ₆ )
It is inserted between. In addition, the inverter (Q ₂ ,
There are MOS capacitors at the input terminals of Q ₅ ) and (Q ₃ , Q ₆ ).
C ₁ and C ₂ are provided respectively.

In this embodiment, the ring oscillator OSC has an N channel on the ground potential side in order to limit the through current in each CMOS inverter.
A constant current source formed by MOSFETQ ₁₃ is provided in common to each of the above inverters. For this, the above
The gate of MOSFETQ ₁₃ has, for example, a power supply voltage
V _CC is applied.

The oscillation output signal of the ring oscillator OSC is generated by the P channel MOSFET Q ₁₀ and the N channel provided between the power supply voltage V _CC and the ground potential.
It is transmitted to the next pump circuit PUMP through an inverter consisting of MOSFETQ ₉ . The inverters Q ₉ and Q ₁₀ function as amplifiers AMP.

The pump circuit PUMP receives the oscillation output signal through the above AMP and sets the negative substrate bias voltage -V _BB
form. That is, the output terminal of the amplifier AMP is connected to one end of the MOS capacitor _C3 .
A MOS diode constituted by an N-channel MOSFET Q ₁₁ is provided between the other end of this MOS capacitor C ₃ and the ground potential.

Then, an N-channel MOSFET Q ₁₂ was constructed between the other end of the MOS capacitor C ₃ and the P-type substrate.
A MOS diode is provided. The gate of the MOS diode _Q11 is connected to the MOS capacitor _C3 side so that it is turned on when the output level of the amplifier AMP is at a high level such as the power supply voltage V _CC . Further, the gate of the MOS diode _Q12 is connected to the P substrate side so that it is turned on when the output level of the amplifier AMP is at a low level such as a ground potential.

The operation of this pump circuit PUMP will be explained next.

When the output signal of the amplifier AMP is high level,
MOS diode _Q11 is turned on and MOS capacitor _C3 is charged. Next, when the output signal of the amplifier AMP is at a low level, the other end of the MOS capacitor _C3 has a negative level of about V _CC -V _thQ11 , so the MOS diode _Q11 is turned off and the MOS diode _Q12 is turned on. Therefore, charge is distributed in the parasitic capacitance C _P between the connection potential of the substrate and the circuit.

Since these operations are repeated according to the oscillation frequency of the ring oscillator OSC, a negative bias voltage -V _BB can be supplied to the substrate.

In this embodiment, a ring oscillator is configured with a CMOS inverter. Therefore, the P-channel MOSFETs _Q4 to _Q6 are responsible for forming high-level rising output signals of each inverter. These P channels
MOSFETs Q ₄ to Q ₆ are formed in the N-type well region and are biased by the power supply voltage V _CC . Therefore, even if the above substrate bias voltage −V _BB fluctuates, the conductance
gm becomes constant. As a result, the rise of the output signal in each inverter to a high level is caused by the substrate bias voltage -V _BB as shown by the solid line in Figure 3.
It remains constant regardless of fluctuations in .

Note that since the low-level falling output signal of each inverter is formed by the N-channel MOSFETs _Q1 to _Q3 , it is similarly affected by the substrate bias voltage _-VBB , and as its conductance gm increases, As shown by the dotted line in the same figure, the falling speed is fast, and conversely, the above conductance
As gm becomes smaller, the falling speed becomes slower, as shown by the dashed line in the figure.

From the above, the rise speed of each inverter is constant regardless of fluctuations in the substrate bias voltage -V _BB , so the ring oscillator OSC
Stabilization of the frequency, and thus the substrate bias voltage -
V _BB can be stabilized. Note that variations in the substrate bias voltage -V _BB are caused by increases and decreases in leakage current to the substrate.

Furthermore, in this embodiment, a P channel is used as a resistance means for adjusting the oscillation frequency.
MOSFETQ ₇ and Q ₈ are used, and the above
Like _MOSFETQ4 to _Q6 , its gm is not affected by fluctuations in the substrate bias voltage _-VBB , which helps stabilize the oscillation frequency.

Furthermore, since this embodiment uses a CMOS inverter, no direct current is consumed when the input signal is stable at a high level or low level, so that power consumption can be reduced. Further, in this embodiment, a constant current MOSFETQ ₁₃ is provided in order to further reduce power consumption. Since the power supply voltage V _CC is applied to the gate of this MOSFET _{Q 13} , a current limiting operation is performed by the drain current flowing in the saturation region. That is, when the input signal of each inverter changes, the P channel
The above describes the relatively large through current flowing through MOSFETQ ₄ etc. and N-channel MOSFETQ ₁ etc.
Since it can be limited by providing MOSFETQ ₁₃ , it is possible to further reduce power consumption.

Furthermore, since a CMOS inverter is used as an amplifier, the amplitude of the pulse signal supplied to the pump circuit PUMP can be increased to the power supply voltage V _CC level. Moreover, N channel load
It also has the advantage that the output high level (V _CC −V _th ) is not affected by fluctuations in the substrate bias voltage −V _BB , unlike amplifiers using MOSFETs.

Therefore, large levels of substrate bias voltage can be applied without using a special putotstrap circuit.
V _BB can be formed.

In this way, since a stable and large substrate bias voltage -V _BB can be obtained, it is possible to stabilize the threshold voltage of the N-channel MOSFET of the semiconductor integrated circuit device equipped with the substrate bias voltage generation circuit according to this embodiment, and By reducing the junction capacitance, high-speed operation can be achieved, and stable operation that can withstand input waveform undershoot can be achieved.

FIG. 4 shows a circuit diagram of an embodiment of a substrate bias voltage generating circuit for supplying a positive bias voltage +V _BB higher than the power supply voltage V _CC to the N-type well region.

This example circuit has a P channel.
A substrate bias voltage +V _BB is applied to MOSFET Q ₄ ′ to Q ₆ ′ and Q ₁₀ ′, and the N-channel
A ground potential is applied to the substrates of MOSFETs _{Q 1} ′ to Q ₃ ′, etc.

Except for this point, the ring oscillator OSC and amplifier AMP of this embodiment circuit are similar to the circuit of FIG. 2.

The pump circuit _PUMP is _a MOS
A diode Q ₁₁ ' is provided on the power supply voltage V _CC side, and is turned on when the output level of the amplifier AMP is low level. Also MOS
The diode Q ₁₂ ′ is turned on when the output level of the amplifier AMP is at a high level.

The operation of this pump circuit PUPM is based on the amplifier AMP
When the output signal of is at low level, MOS diode Q ₁₁ ' is turned on and charges MOS capacitor C ₃ .

Then, when the output signal of the amplifier AMP is at a high level, a high level higher than the power supply voltage V _CC level is formed due to the putot strap effect of the MOS capacitor C ₃ , and the MOS diode Q ₁₂ which is turned on at this time is ' is transmitted to the parasitic capacitance C _W between the N-type well and the substrate (ground potential), so that a substrate bias voltage +V _BB can be formed.

In this embodiment, the conductance of the N-channel MOSFET is constant regardless of the positive substrate bias voltage +V _BB , so as above, the oscillation frequency of the ring oscillator OSC is stabilized, and in turn, the substrate bias voltage +V _BB is stabilized. be able to.

In addition, this embodiment uses a CMOS circuit to reduce power consumption, and a constant current _MOSFETQ13 ' to reduce power consumption.
Similarly to the above, power consumption can be reduced by limiting the through current of the inverter.

FIG. 5 shows a circuit diagram of a substrate bias voltage generation circuit showing another embodiment.

This embodiment circuit shows a modification of FIG. 2, and a constant current source formed by a P-channel MOSFET Q ₁₄ is provided on the power supply voltage V _CC side of the ring oscillator OSC. this
A ground potential is applied to the gate of MOSFETQ ₁₄ . In this way, the ground potential and power supply voltage V _CC
Since MOSFETs Q ₁₃ and Q ₁₄ as constant current sources are provided in both of the ring oscillators, the output amplitude of the ring oscillator can be further reduced, and power consumption can be reduced.

Further, as another modification, in the circuit shown in FIG. 4, a P-channel constant current MOSFET may be provided on the power supply voltage V _CC side.

In addition, MOSFETQ ₇ and Q ₈ as resistance means are
It is also possible to use an N-channel MOSFET or other resistance means. Further, these MOSFETs Q ₇ and Q ₈ and MOS capacitors C ₁ and C ₂ may be omitted.

However, when configuring a relatively low oscillation frequency with a small number of inverters, the above resistance means and
MOS capacity is required.

In addition, the pump circuit PUMP in the embodiments shown in FIGS. 2, 4, and 5 is an N channel.
The reason why MOS diodes with MOSFETs _{Q 11} and Q ₁₂ are used is that their responsiveness is higher than when using P-channel MOSFETs. If this responsiveness is not a problem, use the P channel.
The MOS diode may be configured using a MOSFET, or another unidirectional element may be used. Furthermore, the constant current MOSFET may be omitted, and in this case, the amplifier AMP may be omitted.

Although the substrate bias voltage generation circuit as shown in FIG. 2 and/or FIG. 4 is not particularly limited,
CMOS dynamic RAM as described below
(Random Access Memory)

Below, CMOS dynamic RAM is simply referred to as D-
Abbreviated as RAM.

[D-RAM configuration and operation]

The configuration of the D-RAM will be explained with reference to FIG.
A block surrounded by a dotted line indicates a D-RAM integrated circuit (hereinafter referred to as IC).

In the above IC, the block surrounded by the two-dot chain line is the timing pulse generation block, and D-
It consists of circuits that generate signals that control the operation of each circuit in the RAM.

Next, the operation of each circuit of the D-RAM will be explained according to the timing diagram of FIG.

When the row address signals A ₀ -A _i are taken into an address buffer (hereinafter referred to as ADB) and latched, the signals become low level with a delay from the row address signals A ₀ -A _i . Here, the reason why the signal is delayed from the row address signals A ₀ to _{A i} is to ensure that the row address signals A ₀ to A _i are taken in as the row address in the memory array.

Next, the signal φ _AR delayed from the signal is applied to ADB, and the levels a ₀ , a ₀ , ... a _i , a _i corresponding to the latched row address signal are applied to the row/column decoder (hereinafter referred to as RC-DCR). ). When the above-mentioned levels a ₀ , ₀ , a _i , and _i are applied to RC-DCR, only the selected RC-DCR remains at high level, and the unselected ones become low level.

Then, when the signal φ _X delayed from φ _AR is applied to RC-DCR, the selected signal is M-ARY
sent to. Here, the reason why _φX is delayed from _φAR is that the RC-DCR is operated after the ADB operation is completed. In this way, the row address in M-ARY is one of the 2 ^{i + 1} output signals of RC-DCR.
Since one line will be at a high level, the corresponding M
-Set by selecting one row address line in ARY.

Next, “1” of the memory cell connected to the selected one row address line in M-ARY
Alternatively, "0" information is amplified by sense up (hereinafter referred to as SA). This SA operation starts when φ _PA is applied.

After that, column address signals A _i+1 ~ _{A j} are ADB
Column address signal
The signal becomes low level with a delay from A _i+1 to A _j . Here, the signal is column address signal A _i+1
The reason why it is delayed from ~Aj is to ensure that the column address signal is taken in as the column address in the memory array.

Next, when the signal φ _AC delayed from the signal is applied to ADB, the levels a _i+1 , _i+1 , . . . a _j , _j corresponding to the column address signal are sent to the RC-DCR. Then, RC-DCR performs the same operation as above. The selected signal is sent to the column switch (hereinafter referred to as C-SW) when the signal φ _Y delayed from φ _AC is applied to RC-DCR.
Thus, the column address in M-ARY is AD
- Since one of the 2 ^Ji output signals of DCR becomes high level, one C-SW is selected, and the column address line, that is, the data line connected to this C-SW is selected. Set by.

In this way, one address within the M-ARY is set.

Next, read and write operations for the addresses set as described above will be explained.

In read mode, the signal is at high level. This signal is designed to go high before going low. This is because when the signal goes to low level, one address of M-ARY is set as a result, so the signal is set to high level before that to prepare for the read operation and shorten the read start time. .

Also, when the CAS system signal φ _OP is applied to the output amplifier, the output amplifier becomes active, the information at the address set above is amplified, and the data is output via the data output buffer (hereinafter referred to as DOB). ( _Dput ) terminal. Reading is performed in this manner, and the read operation is completed when the signal becomes high level.

Next, in the write mode, the signal becomes low level. The signal φ _RW created by this low level signal and the low level signal becomes high level and the data input buffer (hereinafter referred to as DIB
It is called. ), DIB becomes active and the write data from the input data (D _io ) terminal is sent to the address set in the M-ARY, thereby performing a write operation.

At this time, an inverted signal of the above-mentioned φ _RW , that is, a low level signal _RW is applied to DOB to control so that data is not read out during the write operation.

[Configuration and operation of D-RAM transistor circuit]

FIG. 8A shows an embodiment of the circuit configuration of a D-RAM in which the substrate bias voltage generation circuit of the present invention is used. The present invention will be explained below based on Examples.

1 Configuration of memory cell M-CEL A 1-bit M-CEL consists of a capacitor C _S for information storage and a P-MOS Q _M for address selection. Information of logic “1” and “0” is sent to the capacitor C _S. It is stored as having or not having a charge.

The gate of P-MOSQ _M is connected to the word line,
One of the source and drain is connected to the data line, and the other to the capacitor _CS .

2 Switching operation of memory cell M-CEL The gate voltage, that is, the word voltage of P-MOSQ _M changes from the power supply voltage V _CC to the threshold voltage V _thp (P-
When the threshold voltage of MOSQ _M decreases by
MOSQ _M is turned on and memory cell M-CEL can be selected.

In addition, when N-MOS is used for the memory cell (not shown), the word voltage can be changed from 0V to (V _CC −
V _tho ) (V _tho ; threshold voltage of N-MOSQ _M ), N-MOSQ _M is turned on and memory cells can be selected.

Therefore, the switching speed of P-MOSQ _M is
Since logical "1" and "0" information can be determined only between V _CC and |V _thp |, the switching speed is considerably faster than that of N-MOSQ _M. A detailed explanation of the switching operation of PMOSQ _M is omitted since it is described in Japanese Patent Application No. 54-119403.

3. Sense amplifier configuration Sense amplifiers SA ₁ and SA' ₁ convert the difference in potential changes that occur on the folded data lines DL _1-1 and _1-1 during address into a sensing period determined by timing signals φ _PA and _PA (sense amplifier control signal). The input/output node is connected to a pair of folded data lines DL _1-1 and DL _1-1 arranged in parallel.

Sense amplifiers SA ₁ and SA′ ₁ are connected in parallel and can be considered as one sense amplifier, but while SA′ ₁ is composed of N-MOS, SA ₁ is of opposite conductivity. The difference is that it is composed of a type of P-MOS. Each sense amplifier is connected to the source side of a pair of cross-connected FETs for positive feedback differential amplification operation.
It consists of a FET for controlling positive feedback differential amplification operation.

As mentioned above, sense amplifiers SA ₁ and SA′ ₁ can be considered as one complementary sense amplifier, so they may be placed next to each other, but the arrangement and shape of wiring, transistors, well regions, etc. should be taken into account. , and spaced apart from each other (for example, at both ends of M-ARY) as shown in Figure 8A, in order to accumulate them efficiently.
It can also be placed.

In other words, since the sense amplifier SA' ₁ made up of P-MOS, the sense amplifier SA' ₁ made up of memory array M-ARY and N-MOS, and the precharge circuit PC can be placed separately, The circuit layout can be separated into a P-MOS section and an N-MOS section, and can be efficiently integrated.

Folded data line DL _1-1 , _1-1 is Al, Au,
It is made of metals such as Mo, Ta, and W. Since the metal has a very low resistance value, the voltage drop of the data line during operation is small and no malfunction occurs.

4 Precharge circuit configuration The precharge circuit PC consists of a _{pair of} N-
N-MOSQ _S1 to eliminate imbalance of precharge voltage between MOSQ _S2 , Q _S3 and both data lines
These N-MOSs are designed to have a lower threshold voltage than other N-MOSs, as indicated by the symbol * in the figure.

The number of memory cells coupled to the folded data lines DL _1-1 and _{DL 1-1} is made equal to increase detection accuracy. Each memory cell is coupled between one word line WL and one of the folded data lines. Since each word line WL crosses a pair of data lines, even if the noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component appears equally on both data lines, and the differential Type sense amplifier SA ₁ ,
canceled by SA′ ₁ .

5 Circuit Operation The circuit operation of FIG. 8A will be explained with reference to the operation waveform diagram of FIG. 8B.

When the precharge control signal φ _PC is at a high level (higher than V _CC ) before reading the storage signal of the memory cell, N-MOSQ _S2 and Q _S3 become conductive, and the folded data lines DL _1-1 and _1-1 are turned on. Stray capacitance C ₀ , C ₀ is approximately 1/2V _CC
will be pre-charged. At this time, N-MOSQ _S1 is also conductive at the same time, so even if an imbalance occurs in the precharge voltages caused by N-MOSQ _S2 and Q _S3 , the folded data lines DL _1-1 and _{DL 1-1} are short-circuited and set to the same potential. The V _th of N-MOSQ _S1 to Q _S3 is set lower than that of transistors not marked with an * so that voltage loss does not occur between the respective sources and drains.

On the other hand, the capacitor C _S in the memory cell maintains a potential of approximately zero volts when the written information is a logic "0", and maintains a potential of approximately V _CC when the written information is a logic "1". The precharge voltage V _DP is set between both storage potentials.

_Therefore , when the read line control signal _φ
becomes higher than V _DP when information of “1” is read, and becomes lower than V _DP when information of “0” is read. By comparing the potential of the above data line with the potential of the other data line that maintains the V _DP potential, the information of the addressed memory cell is set to "1".
It can be determined whether the value is "0" or "0".

The positive feedback differential amplification operation of the sense amplifiers SA ₁ and SA ₂ starts when FETQ _S9 and Q _S4 start conducting by the timing signals (sense amplifier control signals) φ _PA and _PA , and Based on the potential difference, the higher data line potential (V _H ) and the lower one (V _L ) are V _CC and zero potential V _GND, respectively.
As the world changes towards the future, the gap widens. N-
The sense amplifier SA ₁ consisting of MOSQ _S7 , Q _S8 and Q _S9 contributes to lowering the potential of the data line to zero potential V _GND , and the sense amplifier SA ₁ consisting of P-MOSQ _S4 , Q _S5 and Q _S6 contributes to lowering the potential of the data line to zero potential V GND. contributes to raising the potential of the data line to V _CC . Each sense amplifier SA ₁ and SA′ ₁ operates in source common mode.

In this way, the potential of (V _L −V _GND ) changes to the sense amplifier.
When the threshold voltage V _tho of N-MOSQ _S7 and Q _S8 of SA' ₁ becomes equal, the positive feedback operation of the sense amplifier SA' ₁ ends. Further, when the potential of (V _CC -V _H ) becomes equal to the threshold voltage V _thp of P-MOSQ _S5 and Q _S6 of sense amplifier SA ₁ , the positive feedback operation of sense amplifier SA ₁ ends. Eventually, V _L reaches zero potential, V _H reaches V _CC , and they become stable in a low impedance state.

Note that it does not matter whether sense amplifiers SA ₁ and SA′ ₁ start operating at the same time, SA′ ₁ starts operating before SA ₁ , or SA ₁ starts operating before SA′ ₁ . good. In terms of read speed, it is faster to operate SA ₁ and SA′ ₁ at the same time, but power consumption increases due to the flow of through current. On the other hand, by making the operation start timings of SA ₁ or SA′ ₁ different, there is an advantage that there is no through current and power consumption is reduced, but the read speed is slightly inferior to the above.

FIG. 8C shows another embodiment of the circuit configuration of a D-RAM in which the substrate bias voltage generation circuit of the present invention is used. Portions corresponding to those in FIG. 8A are given the same reference numerals. The difference from FIG. 8A is that the positive feedback operation control means of _SA'1 is constituted by N-MOSQ _S9 and Q _S10 connected in parallel.

The operation of sense amplifiers _SA1 and _SA'1 will be explained with reference to FIG. 8D. The folded data line should be approximately 1/
Assume that it is charged to 2V _CC .

The positive feedback operation control means of sense amplifier SA′ ₁
When FETQ _S10 is made conductive by the sense amplifier control signal φ ₁ , only one of FETQ _S7 or FETQ _S8 is made conductive, and the potential of the lower data line (V _L )
Lower the zero potential V a little towards _GND . At this time,
The potential of the higher data line (V _H ) is set to FETQ _S7 or
One side of FETQ _S8 is non-conductive, so it does not change. Note that the conductance of FETQ _S10 is designed to be smaller than that of FETQ _S9 .

Next, by the sense amplifier control signal _φPA,
When the FETQ _S9 starts to conduct, the sense amplifier _SA'1 starts a positive feedback operation and changes the potential V _L toward the zero potential V _GND .

In other words, after slightly widening the potential difference between the folded data lines using the sense amplifier control signal _φ1 , the sense amplifier control signal _φPA is applied, and the sense amplifier
When SA′ ₁ is made to perform positive feedback operation,
Even if the potential difference between the folded data lines is small, it can be amplified by the sense amplifier _SA'1 . In other words, the sensitivity of the sense amplifier improves.

Next, the positive feedback differential amplification operation of sense amplifier SA ₁ is
It starts when FETQ _S4 starts conducting by sense amplifier control signal φ _PA or φ ₂ , and the potential of the higher data line (V _H ) rises towards V _CC .

The potential of the data line is finally _VL , which is zero potential.
V _H reaches V _CC and becomes stable in a low impedance state.

FIG. 8E shows another embodiment of the circuit configuration of a D-RAM in which the substrate bias voltage generation circuit of the present invention is used. Portions corresponding to those in FIG. 8A are given the same reference numerals. The difference from FIG. 8A is that a dummy cell D-CEL is connected to the folded data line.

The configuration of dummy cell D-CEL is P-MOSQ _D1 and P
- Consists of a series connection circuit of MOSQ _D2 , P-
The gate of MOSQ _D1 is connected to the dummy word line, and the source
One of the drains is connected to the data line, the other is connected to P-
It is connected to one of the source and drain of MOSQ _D2 , and the other is grounded.

The dummy cell D-CEL does not require a capacitor C _dS to store the reference potential. This is because the data line is precharged with the reference potential. Dummy cell D-CEL has the same manufacturing conditions as memory cell M-CEL,
Made with the same design constants.

The dummy cell D-CEL has the function of canceling out various noises generated on the folded data line during memory information writing and reading operations.

[Time-series operation of D-RAM transistor circuit]

The time-series operation of the D-RAM transistor circuit will be described with reference to FIG. 8A.

1 Read signal amount To read information, turn on P-MOSQ _M and turn on C _S
to the common column data line DL, and connect the data line to the common column data line DL.
This is done by sensing how the potential of DL changes depending on the amount of charge accumulated in _CS . If the potential previously charged in the stray capacitance _C0 of the data line DL is half of the power supply voltage, that is, 1/2V _CC , the information stored in C _S is "1" (of V _DL ). In this case, the potential of the data line DL (V _DL ) “1” at the time of address is V _CC・(C ₀ +
2C _S )/2(C ₀ +C _S ), which is “0” (0V)
In the case of heating, (V _DL ) “1” is V _CC・C ₀ /2 (C ₀ +
C _S ). Here, the difference between logic "1" and logic "0", that is, the detected signal amount △V _S is △V _S = (V _DL ) "1" - (V _DL ) "0" = V _CC・C _S ／
(C ₀ +C _S )=(C _S +C ₀ )・V _CC /{1+(C _S /C ₀ )}.

Since the memory cells are made small and many memory cells are connected to a common data line to create a highly integrated non-capacitance memory matrix, C _S ≪ C ₀ , that is, (C _S /C ₀ ) is The value is almost negligible. Therefore, the above formula is △V _S V _CC・
It is expressed as (C _S /C ₀ ), and ΔV _S is an extremely small signal.

2 Read operation Pre-charge period This is exactly the same as the precharge operation described above.

Row address period timing signal (address buffer control signal)
The row address signals A ₀ to A _j supplied from the address buffer ADB at the timing of φ _AR (see Figure 7) are decoded by the row/column decoder RC-DCR, and are synchronized with the rising edge of the word line control signal _φ At the same time, addressing of memory cell M-CEL is started.

As a result, a voltage difference of approximately ΔV _S occurs between the folded data lines DL _1-1 and _1-1 based on the stored contents of the memory cells, as described above.

Sensing timing signal (sense amplifier control signal) φ _PA
As a result, the sense amplifier _SA'1 starts a positive feedback operation at the same time as the N-MOSQ _S9 starts to conduct, and amplifies the detection signal of ΔV _S generated at the address time. At the same time as this amplification operation or after the start of the amplification operation, the sense amplifier SA ₁ starts a positive feedback operation by the timing signal φ _PA and restores the logic "1" level to V _CC .

Data output operation timing signal (address buffer control signal)
Column address signals A _i+1 to A _j sent from address buffer ADB in synchronization with φ _AC are low.
The information stored in the memory cell M-CEL at the column address selected by the timing signal (column switch control signal) φ _Y is decoded by the column decoder RC-DCR and then sent to the column switch C-DCR.
It is transmitted to the common input/output lines CDL ₁ , ₁ via SW ₁ .

Next, the timing signal (data output buffer and output amplifier control signal) φ _OP is used to
The data output buffer OA&DOB operates and the read memory information is sent to the chip's output terminal D _put . Note that this OA&DOB is a timing signal (data output buffer control signal) when writing _RW
is disabled by

3 Write Operation Row Addressing Period The precharge, addressing, and sensing operations are exactly the same as the read operation described above. Therefore, regardless of the logic value of the input write information D _io , the storage information of the memory cell to which writing is originally to be performed is read to the folded data lines DL _1-1 , _1-1 .
Since this read information is to be ignored in the write operation described later, the operation up to this point can be considered to be essentially row address selection.

Write period Similar to the read operation, the folded data lines DL _1-1 , _1-1 located in the selected column are connected to the common input via column switch C-SW ₁ in synchronization with the timing signal (column switch control signal) _φY . output line
Combined with CDL ₁ , ₁ .

Next, complementary write input signals d io _{and io} supplied from the data input buffer DIB in synchronization with the timing signal (data input buffer control signal) φ _RW are applied to the memory cell M- through the column switch C- _SW1 .
Written to CEL. At this time, the sense amplifier
SA is also working, but the output impedance of the data input buffer DIB is low, so the data line is folded back.
The information appearing in DL _1-1 and _1-1 is determined by the information in the input D _io .

4. Refresh operation Refresh reads the information that is being lost stored in the memory cell M-CEL onto the column common data line DL, and restores the read information to the restored level by the sense amplifiers SA ₁ and SA' ₁ . This is done by writing to the memory cell M-CEL again. Therefore, the refresh operation is similar to the row addressing or sensing period operation described in the read operation. However, in this case, the column switch C- _SW1 is made inactive and refresh is performed simultaneously for all columns and for each row in turn.

[2-mat type 64K-D-RAM circuit configuration] Figure 9A shows memory cells of about 64K bits each having a storage capacity of 128 columns (rows) x 256 rows (columns) = 32768 bits (32K bits). memory cell matrix (memory array M-ARY ₁ , M
_-ARY2 ) is shown. The main blocks in this figure are drawn according to their actual geometrical arrangement.

The row address selection line (word line WL) of each memory array M-ARY ₁ , M-ARY ₂ has 2 ^r = 128, which is obtained based on the row address signals A ₀ to _{A 6} .
The corresponding decode output signals are applied from each row decoder (and word driver) R-DCR ₁ and R-DCR ₂ .

The column decoder C-DCR provides 128 decoded output signals based on column address signals _A9 to _A15 . This column selection decode output signal is common to the left and right memory arrays and adjacent upper and lower columns in each memory array, that is, to a total of four columns.

Address signals A ₇ and A ₈ are assigned to select any one of these four columns. For example, A ₇ is assigned to left/right selection, and A ₈ is assigned to top/bottom selection.

The φ _yij signal generation circuit φ _yij -SG decodes four combinations based on the address signals A ₇ and A ₈ , and the columns are decoded based on the output signals φ _y00 , φ _y01 , φ _y10 , and φ _y11 . The column switch selectors CSW-S ₁ and CSW-S ₂ are used for switching.

In this way, the decoder for selecting a column of the memory array includes the column decoder C-DCR and the column switch selectors CSW-S ₁ and CSW-
It is divided into two stages of S ₂ . The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip. In other words, the vertical arrangement interval (bit) of the NOR gates, which have a relatively large area and carry the pair of left and right output signal lines of the column decoder C-DCR, is adjusted to the column arrangement pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced, and the area occupied by the NOR gate can be reduced.

The second aim of dividing the decoder into two stages is to
By reducing the number of NOR gates connected to one address signal line, the load on one address signal line is reduced and switching speed is improved.

The address buffer ADB receives eight multiplexed external address signals _A0 to _A7 ;
A ₈ to _{A 15} are respectively converted into eight types of complementary pair address signals (a ₀ , ₀ ) to (a ₇ , ₇ ): (a ₈ , ₈ ) to (a ₁₅ ,
_a15 ) and sent to the decoder circuit at timings φ _AR and φ _AC that match the operations within the IC chip.

[Two-mat type 64K-D-RAM circuit operation] The circuit operation in the address setting process in the two-mat type 64K-D-RAM will be explained with reference to FIGS. 9A and 9B.

First, when the row-related address buffer _control signal φ _AR rises to a high level, seven types _{of complementary pair row address signals (a 0 , 0 ) to} (a ₆ , ₆ ) are applied from the address buffer ADB to the row decoders R- _DCR1 and R- _DCR2 via the row address line R-ADL.

Next, the word line _control signal _φ
DCR ₂ becomes active and each memory array M-
One each of the word lines WL of ARY ₁ and M-ARY ₂ is selected and set to high level.

Next, the column system address buffer control signal φ _AC
By rising to high level, seven types of complementary column address signals ( _{a9 , 9} ) to ( _a15 , ₁₅ ) corresponding to column address signals A9 to _A15 are sent from address buffer ADB to the column. Address line C-
It is applied to the column decoder C-DCR via ADL.

As a result, one pair of the 128 pairs of output signal lines of the column decoder C-DCR becomes high level, and this high level signal is transmitted to the column switch selector CSW-
Applied to S ₁ and CSW−S ₂ .

Next, when the column switch control signal φ _Y rises to a high level, the φ _yij signal generating circuit φ _yij -SG becomes operational.

On the other hand, when the address buffer control signal φ _AR becomes high level, the complementary pair signal (a ₇ , ₇ ) corresponding to the address signal A ₇ becomes the complementary pair signal (a ₈ , 7 ) corresponding to the address signal A ₈ . , ₈ ) are respectively applied to the φ _yij signal generating circuit φ _yij −SG when the address buffer control signal φ _AC becomes high level. Therefore, when the column switch control signal φ _Y goes high, almost simultaneously φ _yij
Signal generation circuit φ _yij −SG is column switch selector
Sends signals to CSW-S ₁ and CSW-S ₂ .

In this way, the column switches C-SW ₁ , C
One pair out of a total of 512 transistor pairs in -SW ₂ is selected, and a pair of data lines DL in the memory array are connected to the common data line CDL.

[2-mat D-RAMIC layout pattern] A so-called 2-mat D-RAMIC where the memory array is divided into two parts within one IC chip.
The layout pattern will be explained according to FIG.

First, two
The two memory arrays M-ARY ₁ and M-ARY ₂ are arranged spaced apart from each other in the IC chip.

A common column decoder C-DCR is arranged in the center of the IC chip between M-ARY ₁ and M-ARY ₂ .

Column switch C-SW ₁ for M-ARY ₁ is located between M-ARY ₁ and C-DCR.

On the other hand, column switch C- for M-ARY ₂
SW ₂ is placed between M-ARY ₂ and C-DCR.

The sense amplifiers SA ₁ and SA ₂ are affected by noise, such as C-
They are placed at the left and right ends of the IC chip to prevent malfunctions caused by signals applied to the DCR and to facilitate wiring layout.

On the upper left side of the IC chip, there is a data input buffer DIB and a read/write signal generation circuit R/W-.
SG, RAS signal generation circuit RAS-SG, and RAS system signal generation circuit _SG1 are arranged. Then, a signal application pad P- is placed close to these circuits.
RAS, signal application pad P-, and data signal application pad P- _Dio are arranged.

On the other hand, on the upper right side of the IC chip, a data output buffer DOB, a CAS signal generation circuit CAS-SG, and a CAS system signal generation circuit _SG2 are arranged. A V _SS voltage supply pad P-V _SS , a signal application pad P-, a data signal output pad P-D _put , and an address signal A ₆ supply pad P-A ₆ are arranged adjacent to these circuits.

A main amplifier MA is arranged between the RAS signal generation circuit SG ₁ and the CAS signal generation circuit SG ₂ .

The V BB generation circuit V _{BB -G} is installed above circuits that occupy a large area such as the RAS signal generation circuit SG ₁ , the CAS signal generation circuit SG ₂ , or the main amplifier MA.
is located. This is because V _BB −G generates minority carriers, and M
There is a risk that the memory cells forming -ARY ₁ and M-ARY ₂ will undergo undesired information inversion. Therefore, to prevent this, the V _BB generation circuit V _BB −G
As mentioned above, is placed as far away from M-ARY ₁ and M-ARY ₂ as possible.

A row decoder R-DCR ₁ for M-ARY ₁ is arranged on the lower left side of the IC chip. and,
Address signal supply pads P-A ₀ , P-A ₁ , P-A ₂ and V _CC voltage supply pad P-V _CC are arranged adjacent to R-DCR ₁ .

On the other hand, a row decoder R-DCR ₂ for M-ARY ₂ is arranged on the lower right side of the IC chip. Address signal application pads P- _{A 3 ,} P-A ₄ ,
P-A ₅ and P-A ₇ are arranged.

An address buffer ADB is arranged between R-DCR ₁ and R-DCR ₂ .

[Layout pattern diagram of power supply line]

A layout pattern diagram of a portion of a 64K-bit D-RAM centering on the memory array M-ARY and sense amplifiers SA ₁ and SA' ₁ will be explained with reference to FIG. 11A. M-ARY and SA ₁ are formed in separate N-channel type well regions surrounded by dashed lines. In addition, column decoder C-
Since the M-ARY, SA ₁ , etc. have a line-symmetrical layout with the DCR as the center, the M-ARY, SA ₂ , SA' _2, etc. in the right well region are omitted.

Since the N-channel type well is supplied with the power supply voltage V _CC , a power supply line V _CC -L is formed as shown in FIG. 7A.

In FIG. 11A, assuming that M-ARY _1-1 is one row, power supply lines are formed for every 32 rows of M-ARY.

Since the well voltage becomes uneven as the distance between power supply lines increases,
-ARY can be formed every 1 row, but since the chip area becomes large, it is recommended to form each M-ARY at equal intervals, for example every 8th row, every 16th row, every 32nd row, or every 64th row. preferable.

In order to make the well voltage uniform, the power supply line is made of Al, Au,
It is made of metals such as MMo and Ta. When a power supply line made of the above-mentioned metal is formed in a well, it is preferably arranged in parallel with the data line made of Al so as not to be short-circuited to the data line.

The reason why the N-channel type well region is separated into the memory array M-ARY and the sense amplifier _SA1 is as follows.

A voltage drop occurs between the power supply line in the well region of the sense amplifier SA ₁ and the positive feedback operation control means (not shown) in the sense amplifier SA ₁ , and the voltage drop occurs in the sense amplifier SA ₁ farther away from the power supply line. The voltage drop becomes large, and this voltage drop becomes noise. If the memory array M-ARY and sense amplifier SA ₁ are formed in the N-type well region, the well potential will drop due to the voltage drop, and the threshold of the P-MOSQ _M (not shown) of the memory cell will decrease. This lowers the value voltage V _TH . In this case, the P-MOSQ _M is likely to turn on, causing malfunction.

By independently forming the N-channel type well regions forming the memory array M-ARY and the sense amplifier _SA1 , the sense amplifier
Prevent noise generated by SA ₁ from affecting memory operations.

Figure 11B shows 64K bits in D-RAM.
Memory array M-ARY and sense amplifier SA ₁ ,
Some layout pattern diagrams centering on SA′ ₁ are shown.

Portions corresponding to those in FIG. 11A are given the same reference numerals.
The difference from FIG. 11A is that the memory array M-ARY and sense amplifier SA ₁ are provided in the same well area.
This is the point that forms the .

There is an advantage that the chip area is smaller than that of the layout shown in FIG. 11A. However, as explained above, the disadvantage is that the noise generated in sense amplifier SA ₁ tends to affect memory operation.

[Memory cell element structure]

FIG. 12A is a perspective cross-sectional view showing the element structure of one memory cell M-CEL, in which 1 is a P-type semiconductor substrate, 2 is a relatively thick insulating film (hereinafter referred to as field insulating film), and 3 is a relatively thin insulating film. film (hereinafter referred to as gate insulating film), 4 and 5 are P ⁺ type semiconductor regions,
6 is a first polycrystalline silicon layer, 7 is an N-type surface inversion layer, 8 is a second polycrystalline silicon layer, 9 is a PSG (phosphorus silicate glass) layer, 10 is an aluminum layer, and 100 is an N-type well region. show.

MOSQ _M in one memory cell M-CEL has a substrate, a well region, a drain region, a source region, a gate insulating film, and a gate electrode as described above, the P-type semiconductor substrate 1, the N-type well region 100, and the P ⁺ -type semiconductor. They are each composed of a region 4, a P ⁺ type semiconductor region 5, a gate insulating film 3, and a second polycrystalline silicon layer 8. The second polycrystalline silicon layer 8 is used, for example, as the word line WL _1-2 shown in FIG. 4A. The aluminum layer 10 connected to the P ⁺ type semiconductor region 5 is, for example, a data line shown in FIG. 8A.
Used as DL _1-1 .

On the other hand, in the storage capacitor C _S in the memory cell M-CEL, one electrode, the dielectric layer, and the other electrode are connected to the first polycrystalline silicon layer 6 and the gate insulating film 3.
and P-type surface inversion layer 7, respectively. That is, since the ground voltage V _SS is applied to the first polycrystalline silicon layer 6, this ground voltage
V _SS induces a P-type surface inversion layer 7 on the surface of the N-type well region 100 due to the electric field effect via the gate insulating film 3 .

Although MOSQ _M in the above memory cell M-CEL is of P-channel type, if all the above conductivity types are changed to different conductivity types, it becomes N-channel type.
MOSQ _M can be formed.

[Dummy cell element structure]

FIG. 12B is a perspective cross-sectional view showing the element structure of one dummy cell D-CEL. In FIG. 12B, in particular, 11, 12, and 14 are P ⁺ type semiconductor regions;
17 and 18 are second polycrystalline silicon layers, and 19 is an aluminum layer.

MOSQ _D1 in one dummy cell D-CEL has a substrate, a well region, a source region, a drain region, a gate insulating film, and a gate electrode of a P type semiconductor substrate 1, an N type well region 100, a P ⁺ type semiconductor region 11, P ⁺ type semiconductor region 12, gate insulating film 3
and a second polycrystalline silicon layer 17, respectively. This second polycrystalline silicon layer 17 extends over the N-type well region 100 as, for example, a dummy word line DWL _1-2 shown in FIG. 8E. The aluminum layer 19 connected to the P ⁺ type semiconductor region extends on the P type semiconductor substrate 1 as, for example, a dummy data line DL _1-1 shown in FIG. 8E.

MOSQ _D2 in dummy cell D-CEL is its substrate,
The well region, source region, drain region, gate insulating film and gate electrode are P-type semiconductor region 1, N
type well region 100, P ⁺ type semiconductor region 12, P ⁺
The semiconductor region 14 is composed of a type semiconductor region 14, a gate insulating film 3, and a second polycrystalline silicon layer 18, respectively. Then, the discharge signal φ _dc shown in the dummy cell D-CEL in FIG. 8E, for example, is applied to this polycrystalline silicon layer 18.

Although MOSQ _D1 and Q _D2 in the above dummy cell D-CEL are shown as P channel type, if all the above conductivity types are changed to different conductivity types, N channel type MOSQ _D1 and Q _D2 can be formed. can.

[Memory array layout pattern]

The layout pattern of memory array M-ARY will be explained with reference to FIG. 13A.

The memory array M-ARY shown in FIG. 13A has a plurality of memory cells M-CEL shown in FIG. 13A arranged in an N-type well region 100.

First, the memory array M-ARY is configured as follows.

On the surface of the N-type well region 100, a field insulating film ₂ is formed based on the pattern shown in FIG. 13B in order to isolate a plurality of memory cells M-CEL each consisting of a MOSQ _M and a storage capacitor C S from each other. has been done.

A field insulating film 2a is exceptionally disposed below a contact hole CH ₀ for applying a ground voltage V _SS to the first polycrystalline silicon layer 6 . Therefore, the aluminum-silicon alloy formed based on the interaction between the aluminum layer and the polycrystalline silicon layer near this contact hole CH ₀ penetrates the insulating film directly under the contact hole CH ₀ and forms the N-type well region 100. Accidents of reaching surfaces undesirably can be prevented.

This field insulating film 2 and gate insulating film 3
A first polycrystalline silicon layer 6, which is used as one electrode of the storage capacitor C _S in the memory cell M-CEL, is formed thereon based on the pattern shown in FIG. 13C.

Furthermore, a thirteenth layer is formed on the first polycrystalline silicon layer 6.
Word lines WL _1-1 to WL _1-6 formed by the second polycrystalline silicon layer 8 in FIG. 12A extend along the vertical direction of FIG. 12A.

Furthermore, a power supply line V _SS-L for supplying the ground voltage V _SS to the polycrystalline silicon layer 6 as one electrode of the storage capacitor _CS through the contact hole CH ₀ is provided as shown in FIG. 9A. Extends laterally.

On the other hand, the data lines DL _1-1 , _1-1 formed by the aluminum layer 10 in FIG.
As shown in FIG. 13A, it extends substantially parallel to the power supply line V _SS-L . Data line DL _1-1 is connected to memory cell M-CEL through contact hole CH ₁ .
Connected to the source region of MOSQ _M , data line _1-
1 is connected to the source region of MOSQ _M in another memory cell M-CEL via a contact hole CH ₂ . Further, _the data lines DL _1-2 , _1-2 extend in the horizontal direction of FIG _. Connected to the source region of MOSQ _M.

In order to bias the N-type well region 100 to the power supply voltage V _CC , a power supply line V _CC-L extends in the lateral direction of FIG. 13A at the end of the memory array M-ARY substantially parallel to the data line.

[Memory array and dummy array layout pattern]

Memory array M-ARY and dummy array D
-ARY layout pattern is shown in Figure 13D. Portions corresponding to those in FIG. 13A are given the same reference numerals. The difference from FIG. 13A is that a dummy array D-ARY is added.

The dummy cell D-CEL shown in FIG. 13D is configured as follows.

A field insulating film 2 is formed on a part of the surface of the N-type well region 100.
A gate insulating film 3 is formed on the other part of the surface of 0.

The P ⁺ type semiconductor region 14 has a plurality of dummy cells D−
Used as a common ground line for CEL.

On the field insulating film 2, the second
A dummy word line DWL _1-1 formed by a polycrystalline silicon layer 17 extends.

Dummy word line DWL _1-1 is dummy cell D-CEL
It constitutes the gate electrode of MOSQ _D1 inside. On the other hand, in order to apply the discharge control signal φ _dc shown in FIG. 8E, the control signal line φ _dc-L1 formed by the second polycrystalline silicon layer 18 in FIG. 12B is connected to the dummy word line DWL. It is separated from _1-1 and extends parallel to it. The control signal line φ _dc-L1 constitutes the gate electrode of MOSQ _D2 in the dummy cell D-CEL. Similarly, dummy word line
Dummy word line DWL _1-2 and control signal line φ _dc-L2 extend in parallel with DWL _1-1 and control signal φ _dc-L1 .

And data lines DL _1-1 , DL _{1 -1} , DL _1-2 , _1
-2 is the memory array M-2 as shown in FIG. 13D.
Extends from ARY. _1-1 connects MOSQ _D1 in dummy cell D-CEL through contact hole _CH3
1-2 is also connected to the source region of other D-CEL through contact hole _CH4 .
Connected to the source region of MOSQ _D1 .

[C-MOS dynamic RAM manufacturing process]

The manufacturing process of a complementary type (hereinafter referred to as C-MOS) dynamic RAM having an N-MOS and a P-MOS will be described with reference to FIGS. 14A to 14W. In each figure _, X ₁ is a process cross-sectional view of the X _{1 -} It is a diagram.

(Oxide film forming step) As shown in FIG. 14A, an oxide film 102 is formed on the surface of the semiconductor substrate 101. Semiconductor substrate 101
As preferred specific materials for the oxide film 102, a P-type single crystal silicon (Si) substrate having a (100) crystal plane and a silicon dioxide (SiO ₂ ) film are used, respectively.

(Selective Oxide Film Removal Step) As shown in FIG. 14B, in order to form a well region of a conductivity type different from that of the semiconductor substrate, the SiO ₂ film 102 on the semiconductor substrate 101 in the well formation region is removed. To do this, first, a silicon nitride (Si ₃ N ₄ ) film 103 is selectively formed on the surface of the SiO ₂ film as an etching mask. In this state, the SiO ₂ film that is not covered by the Si ₃ N ₄ film 103 is removed using an etchant.

(Selective Substrate Removal Step) As shown in FIG. 14C, in order to form a well region of a conductivity type different from that of the semiconductor substrate in the semiconductor substrate 101, the semiconductor substrate is etched using the Si ₃ N ₄ film 103 as an etching mask. The substrate 101 is etched to a desired depth by wet etching or dry etching.

(N-type well region forming step) As shown in FIG. 14D, Si single crystal is epitaxially grown in the etched region in the semiconductor substrate 101. Also dope with arsenic at the same time.

In this way, an N-type well region with an impurity concentration of about 10 ¹⁵ cm ^-3 is formed on the semiconductor substrate 101 . After that, the SiO ₂ film 10 on the semiconductor substrate 101 is
2 and remove the Si ₃ N ₄ film.

Forming an N-type well region provides the following advantages.

(1) In order to prevent stored information from being inverted due to alpha rays being absorbed by the capacitor C _S of the memory cell, if the memory cell is configured within an N-type well region, the The holes generated are reflected by the barrier at the PN junction, eliminating the effect of the holes on the capacitor C _S. Furthermore, by forming the well region epitaxially, the following advantages can be raised compared to forming it by diffusion.

(1) Since the concentration in the well can be easily controlled, the concentration can be made uniform.

(2) The junction capacitance on the well surface can be reduced, increasing the speed of memory operation.

(3) Since the concentration on the well surface can be lowered, the withstand voltage can be increased.

(4) Threshold voltage can be easily controlled.

(5) The depth of the well can be adjusted with high precision.

Next, the process of forming an N-type well region by another method will be explained with reference to FIGS. 14a to 14c.

In FIG. 14a, a Si single crystal is grown epitaxially while doping the entire surface of a semiconductor substrate 101 with arsenic. The impurity concentration of arsenic is 10 ¹⁵ cm ^-3 . In this way, an N-type well region with a depth of about 3 μm is uniformly formed on the semiconductor substrate 101.

In FIG. 14b, a SiO ₂ film 102 and a photoresist film 104 are formed on the N-type well formation region in order to form a desired N-type well region. Thereafter, using the SiO ₂ film and the photoresist film 104 as a mask, boron having an impurity concentration of 2×10 ¹⁵ cm ^-3 is ion-implanted onto the surface of the N-type well, and thermal diffusion is performed to diffuse the boron into the semiconductor substrate 101. The same P-type region is formed.

In FIG. 14c, the SiO ₂ film 102 and photoresist film 104 are removed to form a desired N-type well region in the semiconductor substrate 101. As shown in FIG.

Note that the method for forming the N-type well region is not limited to the above two types of methods, and other methods may of course be used. Of course, the well region may also be formed by diffusion.

(Step of forming oxide film and oxidation-resistant film) As shown in FIG. 14E, an SiO ₂ film 102 and an oxygen-proof insulating film, that is, an oxidation-resistant film 103 are formed on the surfaces of the semiconductor substrate 101 and the N-type well 100.

A silicon nitride (Si ₃ N ₄ ) film is used as a preferred specific material for the oxidation-resistant film 103 .

The SiO ₂ film 102 is attached to the Si substrate 10 for the following reasons.
It is formed to a thickness of about 500 Å by surface oxidation of 1. That is, the Si ₃ N ₄ film 103 is directly attached to the Si substrate 10.
When formed on the surface of Si substrate 101 and Si ₃ N ₄
Due to the difference in thermal expansion coefficient with the film 103, the Si substrate 1
Apply thermal strain to the surface of 01. For this reason, Si substrate 1
Give crystal defects to the surface of 01. To prevent this, the SiO ₂ film 102 is formed before the Si ₃ N ₄ film 103 is formed.
It is formed on the surface of the Si substrate 101. On the other hand, Si ₃ N ₄
The film 103 is formed on the Si substrate 101 as will be described in detail later.
For use as a mask for selective oxidation, it is formed to a thickness of about 1400 Å by, for example, CVD (Chemical Vapor Deposition).

(Selective removal of oxidation-resistant film and ion implantation process) Si ₃ N ₄ film 10 on the surface of the Si substrate 101 on which a relatively thick insulating film, that is, a field insulating film is to be formed.
In order to selectively remove the Si ₃ N ₄ film 1, the photoresist film 104 is first used as an etching mask.
selectively formed on the surface of 03. In this state,
For example, the exposed portion of the Si ₃ N ₄ film 103 is removed by plasma etching, which allows for highly accurate etching.
remove.

Next, in order to prevent a layer of the opposite conductivity type from that of the substrate, so-called inversion layer, from being formed on the surface of the Si substrate 101 where the field insulating film is formed.
As shown in FIG. 14F, impurities of the same conductivity type as the substrate, that is, P-type impurities, are introduced into the Si substrate 101 through the exposed SiO ₂ film 102 with the photoresist film 104 remaining. Ion implantation is preferred as a method for introducing this P-type impurity. For example, boron ions, which are P-type impurities, are implanted into the Si substrate 101 with implantation energy of 75 KeV. The ion dose at this time was 3×10 ¹² atoms/cm ² .

(Field insulator formation process) Field insulator 105 is formed on the surface of Si substrate 101.
selectively formed. That is, as shown in FIG. 14G, after removing the photoresist film 104,
Using the Si ₃ N ₄ film 103 as a mask, the surface of the Si substrate 101 is selectively oxidized by thermal oxidation to a thickness of approximately 9500 mm.
A SiO ₂ film 105 (hereinafter referred to as a field SiO ₂ film) with a thickness of 100 Å is formed. This field SiO ₂ film 1
During the formation of 05, the ion-implanted boron is Si
A P-type anti-inversion layer (not shown) is stretched and diffused into the substrate 101 and has a predetermined depth.
It is formed directly under the SiO ₂ film 105.

(Oxidation-resistant film and oxide film removal process) In order to expose the surface of the Si substrate 101 where the field SiO ₂ film 105 is not formed,
The Si ₃ N ₄ film 103 is removed using, for example, hot phosphoric acid (H ₃ PO ₄ ) solution. Subsequently, the SiO ₂ film 102 is removed using, for example, a hydrofluoric acid (HF) solution, and the 14th H.
As shown in the figure, the surface of the Si substrate 101 is selectively exposed.

(First gate insulating film forming step) A first gate insulating film 106 is formed on the exposed surfaces of the Si substrate 101 and the N-type well 100 to obtain the dielectric layer of the capacitor C _S in the memory cell M-CEL. Form as shown. That is, by thermally oxidizing the exposed surfaces of the Si substrate 101 and the N-type well, a first gate insulating film 106 having a thickness of about 430 Å is formed on the surfaces. Therefore, the first
The gate insulating film 106 is made of SiO ₂ .

(First conductor layer deposition process) The first conductor layer 107 is attached to the Si substrate 10 to be used as one electrode of the capacitor C _S in the memory cell.
1 as shown in FIG. 14J. That is, as the first conductor layer 107, for example, a polycrystalline silicon layer is formed over the entire surface of the Si substrate 101 by CVD. The thickness of this polycrystalline silicon layer is approximately 4000
It is about Å. Subsequently, polycrystalline silicon layer 10
In order to reduce the resistance value of the polycrystalline silicon layer 107, an N-type impurity such as phosphorus is introduced into the polycrystalline silicon layer 107 by a diffusion method. As a result, polycrystalline silicon layer 1
The resistance value of 07 is 16Ω/□.

(Selective removal step of first conductor layer) First conductor layer, that is, first polycrystalline silicon layer 10
In order to form electrode 7 into a predetermined shape, first polycrystalline silicon layer 107 is selectively removed by photoetching, as shown in FIG. 14K, and electrode 108 is formed. Plasma etching is suitable for selectively removing the first polycrystalline silicon layer 107 because it allows for highly accurate etching. Subsequently, the exposed first gate SiO ₂ film 106 is also etched,
The surface of the N-type well 100 is partially exposed.

(Second gate insulating film formation step) Memory array M-CEL, dummy array D-
A second gate insulating film 109 is first deposited on the exposed surfaces of the Si substrate 101 and the N-type well 100 to obtain gate insulating films for the MOS in the CEL and peripheral circuit sections.
Form as shown in Figure 4L. That is, by thermally oxidizing the exposed surfaces of the Si substrate 101 and the N-type well 100, a second gate insulating film 109 having a thickness of about 530 Å is formed on the surfaces. Therefore, the second gate insulating film 109 is made of SiO ₂ .
Second gate insulating film, that is, second gate SiO ₂ film 1
At the same time as the formation of electrode 09, the surface of electrode 108 made of first polycrystalline silicon is also oxidized, and a thickness of approximately
A SiO ₂ film 110 of 2200 Å is formed. This _SiO2
The film 110 serves as interlayer insulation between the electrode 108 and a second electrode made of polycrystalline silicon, which will be described later.

(Threshold voltage control ion implantation step) As shown in FIG. 14M, in order to control the threshold voltage of the N-MOS, a photoresist film 104 is used as an ion implantation mask on the N-type well surface, -P-type impurities are introduced into the surface of the Si substrate 101 on which the MOS is to be formed by ion implantation. For example, boron is used as the P-type impurity. The implantation energy is 30KeV and the ion dose is
4.5×10 ¹¹ atoms/cm ² is preferred.

(Second conductor layer deposition process) The second conductor layer 113 is attached to the Si substrate 10 to be used as the gate electrode and wiring layer of all MOS.
1. Form on the entire surface. That is, as shown in FIG. 14N, for example, a polycrystalline silicon layer is formed as the second conductor layer 113 over the entire surface of the Si substrate 101 by the CVD method. The thickness of this polycrystalline silicon layer 113 is approximately 3500 Å. Subsequently, in order to reduce the resistance value, an N-type impurity such as phosphorus is introduced into this polycrystalline silicon layer 113 by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 113 is approximately
It becomes 10Ω/□.

(Selective removal process of second conductor layer) Second conductor layer, that is, second polycrystalline silicon layer 11
3 is selectively removed by photoetching in order to form a predetermined electrode or wiring shape. In other words, as shown in FIG. 14O, the silicon layer 113 after photoetching forms the word line shown in FIG. 13D.
WL _1-1 ~ WL _1-6 , dummy word line DWL _1-1 ,
DWL _1-2 and control signal lines φ _dc-L1 and φ _dc-L2 are formed.
Furthermore, the exposed second gate SiO ₂ film 109 is removed to expose the surfaces of the Si substrate 101 and the N-type well 100.

(Surface oxidation process) In order to avoid contamination of the surface where the source and drain regions of the MOS are to be formed, the first
As shown in Figure 4P, the exposed Si substrate 101 and N
A SiO ₂ film 115 with a thickness of 100 Å is formed on the surface of the mold well 100 by thermal oxidation of the surface. At the same time as the SiO ₂ film 115 is formed, word lines WL _1-1 to WL _1-6 and dummy word lines made of second polycrystalline silicon are formed.
DWL _1-1 , DWL _1-2 , control signal line φ _dc-L1 , φ _dc-L2 ,
The surfaces of the complementary MOS gate electrodes are also oxidized, resulting in a 300 Å thick SiO ₂ film 116 on their surfaces.
is formed as shown in FIG. 14P.

(Source/drain region formation process) First, the source/drain regions of the N-MOS are formed using Si.
14th Q for selectively forming in the substrate 101
As shown in the figure, an ion implantation mask, for example, a CVDSiO ₂ film 119, is formed on the N-type well 100.
An N-type impurity, for example, arsenic, is introduced into the Si substrate 101 through the SiO ₂ film 115 in a region where the CVDSiO ₂ film 119 is not present. Ion implantation is preferred as a method for introducing this N-type impurity. For example, arsenic ions are implanted into the Si substrate 101 with an implant energy of 80 KeV. The ion dose at this time was 1×10 ¹⁶ atoms/cm ² . Subsequently, heat treatment is performed, and the implanted arsenic impurities are stretched and diffused into N ⁺ type semiconductor regions 120, 12 having a predetermined depth.
1 is formed. These N ⁺ type semiconductor regions 120,
Reference numeral 121 represents the source and drain regions.

Next, in order to selectively form source/drain regions of P-MOS in the N-type well 100,
As shown in Figure R, an ion implantation mask, for example, is placed on the Si substrate 101 other than on the N-type well 100.
A CVDSiO ₂ film 119 is formed and the N-type well 10
A P-type impurity, for example, boron, is introduced into the N-type well through the SiO ₂ film 115 on the SiO 2 film 115 by ion implantation. For example, boron ions are implanted with energy
It is implanted into the N-type well at 80KeV. The ion dose at this time was 3×10 ¹⁵ atoms/cm ² .

Subsequently, heat treatment is performed, and the ion-implanted boron impurity is stretched and diffused, forming P ⁺ -type semiconductor regions 122 to 127 having a predetermined depth.

These P ⁺ type semiconductor regions 122 to 127 become source and drain regions.

Note that the source and drain of P-MOS are N type.
The reason why it is formed after the source and drain of the MISFET is to perform the above heat treatment process only once to prevent boron from diffusing more than necessary.

(Contact hole formation step (1)) First conductor layer, that is, first polycrystalline silicon layer 10
A contact hole for connecting 8 and a third conductor layer to be described later is formed in the SiO ₂ film 110. That is,
Contact hole CH ₁₀₁ as shown in Figure 14S
using a photoresist film (not shown) as a mask.
It is selectively formed in the SiO ₂ film 110. Note that this contact hole CH ₁₀₁ corresponds to the contact hole CH ₀ shown in FIG. 13A.

The reason why only the contact hole CH ₁₀₁ for connecting the first polycrystalline silicon layer 108 and the third conductor layer is formed is as follows. That is, as described above, the thickness of the SiO ₂ film 110 formed on the surface of the first polycrystalline silicon layer 108 is 300 Å. On the other hand, Si
The thickness of the SiO ₂ film 115 formed on the surfaces of the substrate 101 and the N-type well 100 is 100 Å. Therefore,
If these SiO ₂ films 110 and 115 are etched at the same time, there is a risk that the SiO ₂ film 115 will be overetched before the first polycrystalline silicon film 108 is completely exposed.

In order to prevent this, the contact hole CH ₁₀₁ is formed independently as described above.

(Contact hole forming step (2)) Contact holes for connecting the source/drain regions and the third conductor layer are formed in the SiO ₂ film 115.
That is, using a predetermined mask, the SiO ₂ film 115 is
By selective etching, contact holes CH ₁₀₂ to _{CH 107} are formed as shown in FIG. 14T.

Although the above mask also has an opening in a portion corresponding to the contact hole CH ₁₀₁ , overetching of the SiO ₂ film 110 in the contact hole CH ₁₀₁ does not actually pose a problem.

Note that contact hole CH ₁₀₂ corresponds to contact hole CH ₁ in FIG. 13A.

(Interlayer insulating film forming step) An interlayer insulating film is formed on the entire surface of the Si substrate 101.
That is, as shown in FIG. 14U, the interlayer insulating film 1
18. For example, phosphorus silicate with a thickness of about 8000 Å
A glass (PSG) film is formed on the entire surface of the Si substrate 101. This PSG film 118 also serves as a gator for sodium ions that affect the characteristics of the MOS.

(Contact hole formation step (3)) Contact holes are formed in the PSG film 118 to connect between the second polycrystalline silicon layer and the third conductor layer and between the source/drain region and the third conductor layer. .

That is, as shown in FIG. 14V, the PSG film 1
18 is selectively etched and the contact hole is
Forms CH ₁₀₁ to _{CH 107} . The mask used to form the contact holes CH ₁₀₁ to _{CH 107} is the same as the mask used to form the contact holes CH ₁₀₁ to _{CH 107} in the contact hole forming step (2). . Continuing,
In order to planarize the PSG film 118, the PSG film 118 is heat-treated at a temperature of about 1000°C.

By the way, the formation of contact holes in the SiO ₂ film 115 described in the above contact hole formation step (2) can be accomplished simultaneously with the formation of contact holes in the PSG film 118. However, while the contact hole for the SiO ₂ film 115 is being completed, the PSG film 118 is also etched. That is, overetching of the PSG film 118 occurs. Therefore, in order to prevent this overetching, the PSG film 118 is
contact hole formation and SiO ₂ film 115
It is preferable to form contact holes for the two separately.

(Third conductor layer forming step) In order to form the power supply line V _SS-L and data lines DL _1-1 , _1-1 , DL _1-2 , _1-2 shown in FIG. 13A, first a Si substrate is formed. A third conductor layer, for example, an aluminum layer with a thickness of 12000 Å, is formed on the entire surface of the substrate 101.
Next, this aluminum layer is selectively etched, and as shown in FIG. 14W, the power supply lines V _SS-L ,
A data line DL _1-1 and a wiring layer 127 are formed.

[Brief explanation of the drawing]

Fig. 1 is an output waveform diagram of an inverter in a conventional ring oscillator, Fig. 2 is a circuit diagram showing an embodiment of the substrate bias voltage generation circuit according to the present invention, and Fig. 3 is a diagram for explaining its operation. FIGS. 4 and 5 are circuit diagrams showing other embodiments of the substrate bias voltage generation circuit according to the present invention, FIG. 6 is a D-RAM block diagram, and FIG. 7 is an inverter output waveform diagram. D-RAM timing diagram; FIG. 8A is a D-RAM block diagram of an embodiment of the present invention; FIG. 8B is a D-RAM timing diagram of an embodiment of the present invention; FIG. 8C is a diagram of another embodiment of the present invention. Example D-
RAM block diagram; FIG. 8D is a D-RAM timing diagram of another embodiment of the present invention; FIG. 8E is a D-RAM timing diagram of another embodiment of the present invention.
Block diagram, Figure 9A shows two mat system
64KD-RAM circuit configuration diagram, Figure 9B is a 2-mat 64KD-RAM timing diagram,
Figure 10 is a two-mat type D-RAMIC layout pattern diagram, Figures 11A and 11B are partial diagrams of a two-mat type D-RAMIC layout pattern, Figure 12A is an element structure diagram of a memory cell, and Figure 12B is a diagram of a dummy cell. 13A is a layout pattern diagram of a memory array, FIG. 13B is a pattern diagram of a field insulating film, FIG. 13C is a diagram of an electrode pattern of a storage capacitor _CS , and FIG. 13D is a diagram of a memory array and a dummy array. Layout pattern diagrams, Figures 14A to 14W, Figures 14a to
FIG. 14c is a manufacturing process diagram of a C-MOS dynamic RAM. SA ₁ , SA′ ₁ , SA ₂ , SA′ ₂ ...Sense amplifier,
PC...Precharge circuit, CDL,...Common data line, M-CEL...Memory cell, D-
CEL...dummy cell, MA...main amplifier,
MS...Memory start signal, nk...nk bit integrated circuit, X ₁ ...Memory array forming section, X ₂ ...CMOS
Formation part, CH……Contact hole, V _CC-L ……
Well power supply line, V _SS-L ...Ground voltage supply line, DL,...Data line, WL...Word line,
REFGRNT...Refresh instruction signal,
REFREQ...Refresh request signal,...Write enable signal, _CS1 to _CSn ...Chip selection control signal, 100...N-type well region, 2,10
5... Field insulating film, 3... Gate insulating film,
6... First polycrystalline silicon layer, 7... P-type surface inversion layer, 8, 17, 18, 114... Second polycrystalline silicon layer, 9, 118... PSG layer, 10, 19,
127...Aluminum layer, 4, 5, 11, 1
2, 14...P ⁺ type semiconductor region, 116...SiO ₂
film.

Claims (1)

[Claims] 1. An oscillation circuit including a plurality of CMOS inverters;
In a dynamic RAM having a substrate bias voltage generation circuit including an amplifier receiving the output of the oscillation circuit and a pump circuit receiving the output of the amplifier, a MOSFET forming at least one CMOS inverter among the plurality of CMOS inverters described above; A dynamic RAM characterized by having a constant current MOSFET connected in series to limit the through current. 2 P channel of the above CMOS inverter
A first constant current MOSFET is connected between the source of the MOSFET and the first power supply voltage terminal, and the
A second constant current is connected between the source of the N-channel MOSFET of the CMOIS inverter and the second power supply voltage terminal.
A dynamic RAM according to claim 1, characterized in that a MOSFET is connected.