JPH0558319B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrated matrix switch for exchanging high-speed digital signals.

(Prior Art) Currently, construction of an integrated digital service network (ISDN) that centrally provides various communication services centered on voice and data is underway. However, with the progress of the information society in recent years, traditional voice
In addition to data, demand is increasing for broadband, high-speed services centered on video and high-definition video. When such a signal is digitally encoded, it is several 10 Mb/s compared to 64 Kb/s for conventional voice/data.
The bit rate is extremely high, up to about 800 Mb/s, and therefore space-division communication channels are mainly used in exchanges for exchanging the above-mentioned high-speed digital signals.

An example of an integrated matrix switch used in such a high-speed digital communication path is the International Switching Symposium 84
Conference Records (International
Switching Symposium ’84 Conference
Record) Session 24C Paper 1 “An Experimental Digital Video Switching Architecture”
Digital Video Switching Architecture)” day. Black H.R. Lehman (D.
Vlack, HR Lehman) is known.

FIG. 4 shows an example of an integrated matrix switch according to the prior art.

The integrated matrix switch shown in FIG.
07 and the outgoing lines 408 to 415, and connect the incoming lines 400 to 407 to the outgoing lines 408 to 4 as necessary.
It includes a plurality of NAND gate circuits connected to 15.

In Figure 4, one input terminal is connected to the input line 400.
NAND gate circuits 416 to 423 connected to
Only NAND gate circuits 423 to 430 whose output terminals are connected to the output line 415 are shown, and other NAND gate circuits are omitted.

In FIG. 4, NAND gate circuits 423 to 4
30 outputs are each wired on output line 415.
OR is taken, for example, NAND gate circuit 4
By applying a logic level "1" to input 431 of 25, the high speed digital signal applied to incoming line 402 is directed to outgoing line 415.

Figure 5 shows the NAND gate circuit 4 shown in Figure 4.
23, 424, and 430. FIG.

In the figure, the same numbers as in FIG. 4 indicate the same components as in FIG. 4.

According to FIG. 5, the NAND circuit 4 shown in FIG.
23, 424, 430 are each load resistance 500
Two normally-off MES FET50 that share
1,502,503,504,505,506.

In FIG. 5, for example, the sum V _SS of the power supply voltage V SS and the threshold voltage V _T is applied to the gate terminal 507 of the FET 504 _.
When a voltage equal to or higher than tV _T is applied, the FET 504 becomes conductive, and the polarity of the speech signal applied to the gate of the FET 503 on the incoming line 401 is reversed and sent to and from the collector of the FET 503, that is, the outgoing line 415. .

(Problems to be Solved by the Invention) However, as the bit rate of call signals becomes faster, for example, the input line 400 shown in FIG.
Ground wiring capacitance 432, 43 associated with outgoing line 430
3. Between incoming lines 400 and 401 and outgoing lines 414 and 4
The influence of the inter-wiring capacitance 434, 435 between 15 and 15 cannot be ignored, causing fluctuations in the duty ratio due to waveform distortion and bit errors due to crosstalk, which is one of the factors that limit the matrix size that can be integrated into one chip. was.

An object of the present invention is to provide an integrated matrix switch that can realize a large matrix size by reducing the influence of ground wiring capacitance and inter-wiring capacitance.

(Means for Solving Problems) According to the present invention, a plurality of incoming lines having a ground wiring capacitance and an inter-wiring capacitance, and a plurality of outgoing lines having a ground wiring capacitance and an inter-wiring capacitance that intersect the plurality of incoming lines and one gate circuit provided at each intersection of the plurality of incoming lines and the plurality of outgoing lines, wherein at least one of the plurality of incoming lines and the plurality of outgoing lines has a ground wiring. To divide the capacitance and inter-wiring capacitance,
An integrated matrix switch characterized in that a plurality of inverters are inserted at intervals is obtained.

(Function) The present invention divides the incoming line and the outgoing line into a plurality of parts by inserting a plurality of inverters into at least one of the incoming line and the outgoing line, and the wiring capacitance of the divided incoming line and the outgoing line is calculated by inserting a plurality of inverters into at least one of the incoming line and the outgoing line. By driving with an inverter, it is possible to prevent fluctuations in duty ratio due to waveform distortion and bit errors due to crosstalk.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

In FIG. 1, the same numbers as in FIG. 4 indicate the same components as in FIG.

In the embodiment of the present invention shown in FIG. 1, inverters 100 to 102 are inserted in the incoming line 400, and inverters 107 are inserted in the outgoing lines 410, 411, 414, and 415 to prevent polarity reversal in the outgoing lines. ~110 are provided.

Furthermore, the inverter 10 is connected to the output line 415 in FIG.
3 to 106 are inserted. Further, among the inverters, the outputs of inverters 104 and 106 are NAND gate circuits 426, 427, and 4, respectively.
28 and 429,430 outputs and wired
OR is taken.

Figure 2 shows the inverters 100 to 1 shown in Figure 1.
It is a figure which shows the specific example of 03,105,107-110.

According to FIG. 2, the inverter 10 shown in FIG.
0-103, 105, 107-110 are normally-off type MES FET20 with load resistance 200
1, and when the input voltage applied to the gate terminal 202 is higher than V _T +V _SS , the FET 2
01 is in a conductive state and the potential of the drain terminal 203 is approximately at V _SS , and when the input voltage is below V _T +V _SS , the FET 201 is in a non-conductive state and the drain terminal 203 is approximately at ground potential.

FIG. 3 also shows the inverter 106 shown in FIG.
4 is a diagram showing a specific example of NAND gate circuits 429 and 430. FIG.

In FIG. 3, the same numbers as in FIGS. 4 and 5 indicate the same components as in FIGS. 4 and 5.

According to FIG. 3, the inverter 10 shown in FIG.
6 and NAND gate circuits 429 and 430 share a load resistor 500, and are each normally-off type.
MES FET300, 301, 302, 505,
The output voltage of the inverter 105 shown in FIG. 1 is applied to the gate terminal 303 of the FET 300.

NAND gate circuits 423 to 4 shown in FIG.
When any of 28 is opened, the signal from the incoming line is
This signal is applied to the gate 303 of the FET 300 and is transmitted to the output line 415. On the other hand, for example
When a voltage equal to or higher than V _SS +V _T is applied to the gate terminal 304 of the FET 302, the FET 302 becomes conductive, and the polarity of the signal on the input line 406 is inverted by the FET 301 and applied to the input of the inverter 110.

The ground wiring capacitance 111 shown in FIG.
The ground wiring capacity 112 is one of the ground wiring capacitance of 0 divided into four by inverters 100 to 102, and the ground wiring capacity 112 is one of the ground wiring capacitance of output line 415 divided into three by inverters 103 to 106, 110. This is smaller than the ground wiring capacitances 432 and 433 shown in FIG. 4, and is driven by, for example, inverters 100 and 104, respectively. For example, an undistorted digital signal is output at the output end of the inverter 100;
The output impedance at the time of rising and falling of the output signal of the inverter 100 is R _r , R _f ,
Assuming that the value of the ground wiring capacitance 111 is C, a distorted digital signal whose rise and fall times are expressed as 0.7CR _r and 0.7CR _r is input to the input terminal of the inverter 101 . For this reason, suppose, for example, that digital signals are applied to the input line 400 shown in FIG. 4 by inverters (not shown) whose output impedances are R _r and R _f at the time of rising and falling, respectively. If the value of the ground wiring capacitance 432 is C _T , the digital signal will be 0.7C _T R _{r and} 0.7C _T R _f due to the influence of this ground wiring capacitance 432.
However, when the inverters 100 to 102 shown in FIG.
Assuming that they are inserted at equal intervals along the wiring _of
Rise time and fall time are also 1/4th
This improves waveform distortion, prevents fluctuations in duty ratio, and enables high-speed signal switching.

Further, the crosstalk components mixed into the incoming line 400 and the outgoing line 415 due to the inter-wiring capacitances 113 and 114 can be removed since the inverters 101 and 105 do not operate below the threshold.

(Effects of the Invention) As described above, the integrated matrix switch according to the present invention reduces fluctuations in duty ratio due to ground wiring capacitance and bit errors due to inter-wire capacitance, and realizes a large matrix size. You can get a switch.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows inverters 100 to 103, 10 shown in FIG.
5, 107 to 110, FIG. 3 is a diagram showing a concrete example of the inverter 106 and NAND circuits 429, 430 shown in FIG. 1, and FIG. 4 is an example of an integrated matrix switch according to the prior art. Figure 5 shows the inverter 42 shown in Figure 1.
3,424,430 is a diagram showing a specific example. In the figure, 100 to 110 are inverters, 41
6 to 430 are NAND gate circuits, 201, 30
0-302, 501-506 are normally off type
Each represents a MES FET.

Claims (1)

[Claims] 1. A plurality of incoming lines having ground wiring capacitance and inter-wiring capacitance, a plurality of outgoing lines having ground wiring capacitance and inter-wiring capacitance that intersect the plurality of incoming lines, and each of the plurality of incoming lines and the plurality of outgoing lines. In an integrated matrix switch consisting of one gate circuit provided at an intersection, inverters are spaced so as to divide ground wiring capacitance and inter-wiring capacitance into at least one of the plurality of incoming lines and the plurality of outgoing lines. An integrated matrix switch characterized in that a plurality of switches are inserted at the same time.