JPH0558511B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A monitor circuit configured as a ring oscillator in which an odd number of stages of pseudo adders are provided in the full adders of a required stage is mounted on an integrated circuit, and the DC/AC characteristics of the integrated circuit are evaluated.

[Industrial application field]

The present invention relates to a circuit for evaluating DC/AC characteristics of an integrated circuit, and particularly to a monitor circuit mounted on an integrated circuit.

[Conventional technology]

DC/AC testing of ICs that have been processed out involves checking the normal/abnormal operation, operating point, operating speed, etc. while changing conditions. The analysis of the test data obtained has become extremely complex, making it difficult and time-consuming to provide design and process feedback.

Therefore, it has been adopted to include some kind of evaluation circuit in the IC. There is one full adder ring oscillator.

Figure 6A shows the logic circuit configuration of a conventional full adder FA (IC evaluation circuit using the ECL series gate method). One of its input terminals A is used for signal transmission, and the other two are used for signal transmission. B and C are used as control terminals. Enter A and B respectively.
OR having an OR circuit 21 and an exclusive NOR circuit 22, and inputting the output of the exclusive NOR circuit 22 and signal C
A circuit 23 and an exclusive OR circuit 24 are provided. A carry CU is obtained as the output of an AND circuit 25 which receives the outputs of the OR circuit 21 and the OR circuit 23, and an added value SU is obtained as the output of the exclusive OR circuit 24.

FIG. 6B shows a conventional monitoring ring oscillator constructed using this full adder FA and an inverter. Connect the carry terminal CU of each FA to the A terminal of the next stage, and connect the carry terminal CU of one FA to the next FA terminal.
An inverter INV is interposed between the A terminals of the inverter. Output is taken from the SU terminal of one FA.

FIGS. 6C and 6D show equivalent circuit configuration diagrams of a conventional ring oscillator for monitoring.

In a conventional ring oscillator for monitoring, when the control signals (B, C) are (0, 1), the critical path is 1 and the fanout is 1 as shown in Figure 6C, with 4 gates and 1 inverter. Configure a ring oscillation circuit. When the control signals (B, C) are (1, 0), each stage of the full adder FA has two critical paths.
In addition, the fanout is 2 in each stage, but since inverters with a fanout of 1 are mixed, the gate delay time when the fanout is 1 and the gate delay time when the fanout is 2. difficult to separate.

[Problem that the invention seeks to solve]

In the conventional circuit, as described above, one of the input terminals of the full adder is used for signal transmission, and the other two are used as control terminals. However, if you change the level of the control terminal and change the FI (fan in)/FO (fan out) or critical path, the full adder may or may not work as an inverter. The configuration is such that an even number of devices are connected and an inverter is sandwiched between them.

However, this poses a problem in that the FI (fan-in)/FO (fan-out) conditions are disrupted at the inverter, making accurate evaluation impossible.

[Means for solving problems]

The present invention completely solves the above problems by configuring at least one stage of the pseudo adder according to the present invention to be sandwiched between full adders at appropriate stages.

That is, the present invention provides an integrated circuit evaluation circuit mounted on a semiconductor integrated circuit, which is composed of elements of the same design as the elements of the integrated circuit, one of the input terminals is used as an input terminal for signal transmission, and the remaining two a full adder of a required stage in which one input terminal is a control terminal and an input signal is transmitted to an output through a transmission path determined according to a control signal input to the control terminal; and a full adder having the same design as the elements of the integrated circuit. It has a similar configuration to the full adder, and one of the input terminals
One is an input terminal for signal transmission, the remaining two input terminals are control terminals, and the inverted signal of the input signal is transmitted to the output through a transmission path determined according to the control signal input to the control terminal. The adders of the same type are connected in series by connecting the carry output terminal and the input terminal for signal transmission, and the carry output terminal of the full adder and the pseudo adder are connected in series. A ring oscillator is configured by connecting an input terminal for signal transmission of an adder, a carry output terminal of the pseudo adder, and an input terminal for signal transmission of the full adder, respectively. An integrated circuit evaluation circuit is provided.

[Effect]

In the monitor circuit of the present invention, since the pseudo adder outputs an inverted output of the input signal, there is no need for an inverter as in the past, and during testing, the path is determined by the signal input to the control terminal, and the fanout 1
It becomes possible to monitor both the fan-out and the fan-out 2.

〔Example〕

FIG. 1A shows a pseudo adder used in an embodiment of the present invention.
A circuit diagram at the logic circuit level of PFA is shown. In the figure, one of the input terminals, A, is used for signal transmission, and the other two, B and C, are used as control terminals. 1 is an OR circuit with an inversion gate, 2
is an exclusive NOR circuit, and signals A and B are input to each input terminal. The output of the exclusive NOR circuit 2, the output of the OR circuit 3 which receives the signal C as input, and the output of the OR circuit 1 are input to an AND circuit 5, and a carry signal CU is outputted as its output. Also exclusive
The output of NOR circuit 2 and signal C are exclusive NOR circuit 4
and obtain the summed output SU(sum) as its output.

FIGS. 2A and 2B show the relationship between the signals of the control terminals B and C of the pseudo adder PEA and full adder FA used in this embodiment, the carry output CU, the critical path, and the fanout.
For both FA and PFA, when the critical pass is 1, the fan out is 1, and when the critical pass is 2, the fan out is 2 and 1.

Figure 1B shows the pseudo adder PEA and full adder FA.
A configuration diagram of this embodiment is shown. Control input signals C and B are applied to input terminals B and C of full adders 11, 13, and 14 in each stage, and signal C is commonly input to terminals B and C of 12 pseudo adders PEA. . And the carry output of each FA and PEA
A ring oscillator is configured by inputting the CU to the A terminal of the next stage, and the output signal is obtained from the SU output terminal of the PEA.

In the ring oscillation circuit according to the embodiment of the present invention, the first B
As shown in the figure, one stage of PEA is inserted into three stages of FA. When the control signals (B, C) are (0, 1), the FA has a critical path of 1 and the input signal A
The same phase is output, and the critical path of PFA is 1.
Since the inverted output of the input signal A is output, a ring oscillation circuit is constructed in which the phase of one round is shifted by 180 degrees. Then, the fanout of each stage is 1 and the 4-gate first
The equivalent circuit shown in Figure C is constructed. Therefore, by dividing the circuit delay time calculated from the oscillation frequency of the ring oscillation circuit by 4, the delay time of one gate can be calculated.

Next, when the control signals (B, C) are (1, 0), each FA has a critical path of 2 and a fanout of 2 and 1, outputs the same phase as the input signal A, and PEA outputs the same phase as the input signal A. The critical path is 2, the fan-out is 2 and 1, and the inverted output of the input signal of A is output, so the fan-out 2 in Figure 1 D
An equivalent circuit of 1 is formed. And in each row 2
Since the delay time calculated from the oscillation frequency of this ring oscillation circuit is divided by 4, it is 1
The delay time when passing through both two fan-out 2 gates and one fan-out 1 gate is calculated.

Figure 3 shows the full adder FA used in the embodiment of the present invention.
The circuit diagram of the transistor level is shown. Further, FIG. 4 shows a transistor level circuit diagram of the pseudo adder PEA used in the embodiment of the present invention. The circuits of this pseudo adder PEA and the full adder FA shown above are the same except for which transistor's collector the load resistor is connected to. Note that the reference voltage VR1 shown in the figure is for controlling the constant current of the emitter, and the voltage VR1 is for controlling the constant current of the emitter.
2 and VR3 determine the logic levels of the upper and lower stages, respectively, and the full adder and pseudo adder are similar in this respect. In this way, the pseudo adder of this embodiment
The power supply of PEA is connected in the same way as the full adder FA, and if a ring oscillator is configured with PEA and FA,
The power supply voltage dependence, voltage margin due to process pattern size, noise margin dependence, etc. are similar, and analysis is easier than in the case of a ring oscillator using a conventional PEA and an inverter.

FIG. 5 shows a planar configuration of a monitor circuit including a ring oscillator in which nine stages of full adders and one stage of pseudo adders are connected according to an embodiment of the present invention. The circuit of this example is mounted on an integrated circuit, and during testing, the path is determined by the signal input to the control terminal.
Two fan outs, fan out 1 and fan out 2, can be monitored. The significance of monitoring in this way is that in an actual device, fanout 1 and fanout 2 are connected in a complicated way, but for example, if you change the voltage, how will the data at the gate of fanout 1 be affected? There are cases where it is desired to separate how the data is affected by the gate, and in such a case, the circuit of this embodiment is particularly effective.

To operate the monitor circuit of this embodiment, it is easy to apply the power supply voltage, add an appropriate reference voltage, and observe the output waveform with an oscilloscope. It is possible to perform AC tests (for example, the relationship between power supply voltage and operating speed) at the same time. In addition, tests using this monitor circuit were performed before attaching the SPEC to the IC, and the reference voltages VR1 to VR3,
Testing time can be shortened by determining the power supply voltage, control signal level, etc. in advance and measuring the device using those values. That is, in the actual device, the circuit is the same as the monitor circuit, only the wiring is different, so the reference voltage VR1~
VR3, power supply voltage, control signals, etc. are the same, and if the operating margin of each gate is determined in advance by the monitor circuit, the actual test time can be significantly shortened.

〔Effect of the invention〕

As described above, according to the present invention, the integrated circuit
DC test and AC test can be done at the same time. In addition, a test using the circuit of the present invention is conducted before attaching the SPEC to the IC, and reference voltages VR1 to VR3, power supply voltage, control signal values, etc. are obtained in advance.
Measuring the device using these values has the advantage of shortening test time.

[Brief explanation of the drawing]

Figure 1A is a logic circuit diagram of a pseudo adder used in an embodiment of the present invention, Figure 1B is a configuration diagram of a monitor circuit using a ring oscillator in an embodiment of the present invention, and Figures 1C and 1D correspond to control signals. The equivalent circuit configuration diagram of the monitor circuit of the example shown in FIG. 2A is the full adder FA.
Figure 2 shows the carry output of the pseudo adder PEA.
Figure B is a diagram showing the relationship between the critical path and the number of fanouts, Figure 3 is a transistor level circuit diagram of the pseudo adder used in the embodiment of the present invention, and Figure 4 is the diagram used in the present invention and the conventional example. A transistor level circuit diagram of a full adder; FIG. 5 is a diagram showing an integrated circuit mounting pattern of a monitor circuit according to an embodiment of the present invention;
Figures 6A and 6B are configuration diagrams of a monitor circuit using a conventional full adder and a ring oscillator, and Figure 6C
1 and 6D are equivalent circuit configuration diagrams of a monitor circuit using a conventional ring oscillator. A...Input signal (terminal), B, C...Control input (terminal), CU...Carry output terminal, SU...Sum (addition result) output terminal, FA...Full adder, PFA
...Pseudo adder.

Claims (1)

[Claims] 1. In an integrated circuit evaluation circuit mounted on a semiconductor integrated circuit, the integrated circuit evaluation circuit is composed of elements of the same design as the elements of the integrated circuit, one of the input terminals is used as an input terminal for signal transmission, and the remaining a full adder of a required stage in which two input terminals are used as control terminals and an input signal is transmitted to an output via a transmission path determined according to a control signal input to the control terminals; It is composed of designed elements, has a similar configuration to the full adder, and has one of the input terminals.
One is an input terminal for signal transmission, the remaining two input terminals are control terminals, and the inverted signal of the input signal is transmitted to the output through a transmission path determined according to the control signal input to the control terminal. The adders of the same type are connected in series by connecting the carry output terminal and the input terminal for signal transmission, and the carry output terminal of the full adder and the pseudo adder are connected in series. A ring oscillator is configured by connecting an input terminal for signal transmission of an adder, a carry output terminal of the pseudo adder, and an input terminal for signal transmission of the full adder, respectively. Integrated circuit evaluation circuit.