JPH0559583B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with a stacked structure, and more particularly to a semiconductor device with improved packaging density and wiring characteristics.

A stacked semiconductor device is a device in which a plurality of semiconductor devices are vertically stacked, integrated, and connected to each other, so that it is possible to increase storage capacity without reducing packaging density. However, since the conventional semiconductor devices of this type are mainly aimed at increasing the capacity of the storage semiconductor device,
Since the amount of heat generated by these semiconductor devices is relatively small, there are no particular heat dissipation problems, but when logic semiconductor devices are added to these devices, the amount of heat generated is often large, so there are problems with heat dissipation. This has limited the ability to increase the packaging density of devices.

Furthermore, when a memory semiconductor device and a logic semiconductor device are combined, external wiring is required, which increases the length of the wiring, resulting in a problem of deterioration of signal transmission speed.

Therefore, an object of the present invention is to solve the problems of heat dissipation and signal transmission speed in a semiconductor device in which memory and logic semiconductor devices are configured in a stacked structure, thereby improving the packaging density and wiring characteristics. An object of the present invention is to provide a semiconductor device with improved performance.

In order to achieve this object, the present invention constructs a stacked structure by stacking a logic semiconductor device that generates a large amount of heat on a memory semiconductor device that generates a small amount of heat.

Hereinafter, the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a front view of the device of the present invention, and FIG. 2 is a partially cutaway perspective view. As shown in the figure, in the device of the present invention, external leads 1a, 2a, 3a are provided on the respective sides of a logic semiconductor device 1 and storage semiconductor devices 2, 3, and each external lead 1a, 2a, 3a has its lower end connected to the package body. It protrudes downward from the lower surfaces of 1b, 2b, and 3b. In addition, each package body 1
Continuous portions 1c, 2 connected to the respective external leads 1a, 2a, 3a are provided on the peripheral surfaces or upper surfaces of b, 2b, 3b.
c and 3c are formed by metallization or the like. In this case, since the number of external leads of the memory semiconductor devices 2 and 3 is generally small, idle leads 4 are provided at positions corresponding to the external leads of the logic semiconductor device, as shown in FIG.

As shown in FIG. 2, the package bodies 2b, 3
Similarly to the package body 1b, each of b has
A semiconductor chip or pellet 6 is housed inside, and electrodes of the chip and external leads 2a, 3a are connected by wires (not shown).

When stacking the semiconductor devices 1, 2, and 3 in a stacked structure, as shown in FIG. Storage semiconductor devices 2 and 3 are arranged, and each external lead 1a, 2a, 3a
Electrical connections are made using the connecting portions 1c, 2c, and 3c. In this case, a heat dissipation fin 5 is integrally attached to the upper surface of the uppermost semiconductor device 1.

Therefore, according to the above configuration, since the logic semiconductor device 1 which generates a large amount of heat is provided at the top position of the stack structure, its heat dissipation performance is good. It is easy to attach, and the overall heat dissipation is improved. This solves the problem of heat dissipation,
It is possible to improve the packaging density by using the stack structure.

In addition, since the storage semiconductor devices 2 and 3 are provided with idle leads 4, these leads act as internal wiring of each semiconductor device when a stacked structure is formed, thereby eliminating the need for external wiring and improving the wiring characteristics. It is also possible to improve the

In the present invention, as shown in FIG. 3, a plurality of memory semiconductor devices 2 and 3 may be arranged in parallel on the same plane, and a logic semiconductor device 1 may be stacked thereon.

As described above, according to the semiconductor device of the present invention, the package body of the logic semiconductor which generates a large amount of heat is located at the topmost position, the package body of the memory semiconductor is disposed below it, and the package body of the logic semiconductor is disposed below it. Since heat dissipation fins are provided on the top surface of the package, problems with heat dissipation can be solved and packaging density can be improved. Furthermore, since the package bodies are electrically connected to each other using external leads, the length of wiring for these connections can be shortened, and the wiring characteristics can be improved. Further, by providing loose leads, it is possible to improve the wiring characteristics.

[Brief explanation of the drawing]

FIG. 1 is a front view of the device of the present invention, FIG. 2 is a partially cutaway perspective view, and FIG. 3 is a front view of a modified example. 1... Logic semiconductor device, 2, 3... Memory semiconductor device, 4... Idle lead, 5... Heat dissipation fin.

Claims (1)

[Scope of Claims] 1. A package body of a logic semiconductor that generates a large amount of heat and has a large number of external leads protruding from the side surface below the bottom surface; at least one storage semiconductor package body with a small heat generation value and provided with a lead, the logic semiconductor package body being positioned at the top stage, and the storage semiconductor package body being placed below the package body. the logic semiconductor package located at the top stage; A semiconductor device characterized in that a heat dissipation fin is provided on the top surface of the main body. 2. The semiconductor device according to claim 1, characterized in that a plurality of lower storage semiconductor package bodies are arranged on the same plane.